MPC8610HPCD.h 23 KB

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  1. /*
  2. * Copyright 2007 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. /*
  9. * MPC8610HPCD board configuration file
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /* High Level Configuration Options */
  14. #define CONFIG_MPC86xx 1 /* MPC86xx */
  15. #define CONFIG_MPC8610 1 /* MPC8610 specific */
  16. #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
  17. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  18. #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
  19. /* video */
  20. #undef CONFIG_VIDEO
  21. #if defined(CONFIG_VIDEO)
  22. #define CONFIG_CFB_CONSOLE
  23. #define CONFIG_VGA_AS_SINGLE_DEVICE
  24. #endif
  25. #ifdef RUN_DIAG
  26. #define CONFIG_SYS_DIAG_ADDR 0xff800000
  27. #endif
  28. /*
  29. * virtual address to be used for temporary mappings. There
  30. * should be 128k free at this VA.
  31. */
  32. #define CONFIG_SYS_SCRATCH_VA 0xc0000000
  33. #define CONFIG_PCI 1 /* Enable PCI/PCIE*/
  34. #define CONFIG_PCI1 1 /* PCI controler 1 */
  35. #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
  36. #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
  37. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  38. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  39. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  40. #define CONFIG_ENV_OVERWRITE
  41. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  42. #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
  43. #define CONFIG_ALTIVEC 1
  44. /*
  45. * L2CR setup -- make sure this is right for your board!
  46. */
  47. #define CONFIG_SYS_L2
  48. #define L2_INIT 0
  49. #define L2_ENABLE (L2CR_L2E |0x00100000 )
  50. #ifndef CONFIG_SYS_CLK_FREQ
  51. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  52. #endif
  53. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  54. #define CONFIG_MISC_INIT_R 1
  55. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  56. #define CONFIG_SYS_MEMTEST_END 0x00400000
  57. /*
  58. * Base addresses -- Note these are effective addresses where the
  59. * actual resources get mapped (not physical addresses)
  60. */
  61. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  62. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  63. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  64. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  65. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  66. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
  67. #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
  68. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
  69. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
  70. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000)
  71. /* DDR Setup */
  72. #define CONFIG_FSL_DDR2
  73. #undef CONFIG_FSL_DDR_INTERACTIVE
  74. #define CONFIG_SPD_EEPROM /* Use SPD for DDR */
  75. #define CONFIG_DDR_SPD
  76. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  77. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  78. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  79. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  80. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  81. #define CONFIG_VERY_BIG_RAM
  82. #define CONFIG_NUM_DDR_CONTROLLERS 1
  83. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  84. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  85. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  86. /* These are used when DDR doesn't use SPD. */
  87. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  88. #if 0 /* TODO */
  89. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  90. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
  91. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  92. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  93. #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  94. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  95. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  96. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  97. #define CONFIG_SYS_DDR_INTERVAL 0x06180100
  98. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  99. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  100. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  101. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  102. #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
  103. #define CONFIG_SYS_DDR_CONTROL2 0x04400010
  104. #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
  105. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  106. #define CONFIG_SYS_DDR_SBE 0x000f0000
  107. #endif
  108. #define CONFIG_ID_EEPROM
  109. #define CONFIG_SYS_I2C_EEPROM_NXID
  110. #define CONFIG_ID_EEPROM
  111. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  112. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  113. #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
  114. #define CONFIG_SYS_FLASH_BASE2 0xf8000000
  115. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  116. #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
  117. #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
  118. #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
  119. #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
  120. #if 0 /* TODO */
  121. #define CONFIG_SYS_BR2_PRELIM 0xf0000000
  122. #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
  123. #endif
  124. #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
  125. #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
  126. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  127. #define PIXIS_BASE 0xe8000000 /* PIXIS registers */
  128. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  129. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  130. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  131. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  132. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
  133. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  134. #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
  135. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  136. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  137. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  138. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  139. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  140. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  141. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  142. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  143. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/
  144. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  145. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  146. #undef CONFIG_SYS_FLASH_CHECKSUM
  147. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  148. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  149. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  150. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  151. #define CONFIG_FLASH_CFI_DRIVER
  152. #define CONFIG_SYS_FLASH_CFI
  153. #define CONFIG_SYS_FLASH_EMPTY_INFO
  154. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  155. #define CONFIG_SYS_RAMBOOT
  156. #else
  157. #undef CONFIG_SYS_RAMBOOT
  158. #endif
  159. #if defined(CONFIG_SYS_RAMBOOT)
  160. #undef CONFIG_SPD_EEPROM
  161. #define CONFIG_SYS_SDRAM_SIZE 256
  162. #endif
  163. #undef CONFIG_CLOCKS_IN_MHZ
  164. #define CONFIG_SYS_INIT_RAM_LOCK 1
  165. #ifndef CONFIG_SYS_INIT_RAM_LOCK
  166. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  167. #else
  168. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
  169. #endif
  170. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
  171. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  172. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  173. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  174. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  175. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
  176. /* Serial Port */
  177. #define CONFIG_CONS_INDEX 1
  178. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  179. #define CONFIG_SYS_NS16550
  180. #define CONFIG_SYS_NS16550_SERIAL
  181. #define CONFIG_SYS_NS16550_REG_SIZE 1
  182. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  183. #define CONFIG_SYS_BAUDRATE_TABLE \
  184. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  185. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  186. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  187. /* Use the HUSH parser */
  188. #define CONFIG_SYS_HUSH_PARSER
  189. #ifdef CONFIG_SYS_HUSH_PARSER
  190. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  191. #endif
  192. /*
  193. * Pass open firmware flat tree to kernel
  194. */
  195. #define CONFIG_OF_LIBFDT 1
  196. #define CONFIG_OF_BOARD_SETUP 1
  197. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  198. /* maximum size of the flat tree (8K) */
  199. #define OF_FLAT_TREE_MAX_SIZE 8192
  200. /*
  201. * I2C
  202. */
  203. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  204. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  205. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  206. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  207. #define CONFIG_SYS_I2C_SLAVE 0x7F
  208. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  209. #define CONFIG_SYS_I2C_OFFSET 0x3000
  210. /*
  211. * General PCI
  212. * Addresses are mapped 1-1.
  213. */
  214. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  215. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  216. #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
  217. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  218. #define CONFIG_SYS_PCI1_IO_BUS 0x0000000
  219. #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
  220. #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
  221. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  222. /* controller 1, Base address 0xa000 */
  223. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  224. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  225. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  226. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  227. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
  228. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
  229. /* controller 2, Base Address 0x9000 */
  230. #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
  231. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
  232. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  233. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
  234. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
  235. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
  236. #if defined(CONFIG_PCI)
  237. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  238. #define CONFIG_NET_MULTI
  239. #define CONFIG_CMD_NET
  240. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  241. #define CONFIG_CMD_REGINFO
  242. #define CONFIG_ULI526X
  243. #ifdef CONFIG_ULI526X
  244. #define CONFIG_ETHADDR 00:E0:0C:00:00:01
  245. #endif
  246. /************************************************************
  247. * USB support
  248. ************************************************************/
  249. #define CONFIG_PCI_OHCI 1
  250. #define CONFIG_USB_OHCI_NEW 1
  251. #define CONFIG_USB_KEYBOARD 1
  252. #define CONFIG_SYS_STDIO_DEREGISTER
  253. #define CONFIG_SYS_USB_EVENT_POLL 1
  254. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  255. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  256. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  257. #if !defined(CONFIG_PCI_PNP)
  258. #define PCI_ENET0_IOADDR 0xe0000000
  259. #define PCI_ENET0_MEMADDR 0xe0000000
  260. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  261. #endif
  262. #define CONFIG_DOS_PARTITION
  263. #define CONFIG_SCSI_AHCI
  264. #ifdef CONFIG_SCSI_AHCI
  265. #define CONFIG_SATA_ULI5288
  266. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  267. #define CONFIG_SYS_SCSI_MAX_LUN 1
  268. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  269. #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
  270. #endif
  271. #endif /* CONFIG_PCI */
  272. /*
  273. * BAT0 2G Cacheable, non-guarded
  274. * 0x0000_0000 2G DDR
  275. */
  276. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  277. #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
  278. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
  279. #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
  280. /*
  281. * BAT1 1G Cache-inhibited, guarded
  282. * 0x8000_0000 256M PCI-1 Memory
  283. * 0xa000_0000 256M PCI-Express 1 Memory
  284. * 0x9000_0000 256M PCI-Express 2 Memory
  285. */
  286. #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
  287. | BATL_GUARDEDSTORAGE)
  288. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
  289. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  290. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  291. /*
  292. * BAT2 16M Cache-inhibited, guarded
  293. * 0xe100_0000 1M PCI-1 I/O
  294. */
  295. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
  296. | BATL_GUARDEDSTORAGE)
  297. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
  298. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  299. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  300. /*
  301. * BAT3 4M Cache-inhibited, guarded
  302. * 0xe000_0000 4M CCSR
  303. */
  304. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
  305. | BATL_GUARDEDSTORAGE)
  306. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
  307. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
  308. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  309. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  310. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  311. | BATL_PP_RW | BATL_CACHEINHIBIT \
  312. | BATL_GUARDEDSTORAGE)
  313. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
  314. | BATU_BL_1M | BATU_VS | BATU_VP)
  315. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  316. | BATL_PP_RW | BATL_CACHEINHIBIT)
  317. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  318. #endif
  319. /*
  320. * BAT4 32M Cache-inhibited, guarded
  321. * 0xe200_0000 1M PCI-Express 2 I/O
  322. * 0xe300_0000 1M PCI-Express 1 I/O
  323. */
  324. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
  325. | BATL_GUARDEDSTORAGE)
  326. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
  327. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  328. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  329. /*
  330. * BAT5 128K Cacheable, non-guarded
  331. * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
  332. */
  333. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  334. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  335. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  336. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  337. /*
  338. * BAT6 256M Cache-inhibited, guarded
  339. * 0xf000_0000 256M FLASH
  340. */
  341. #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
  342. | BATL_GUARDEDSTORAGE)
  343. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  344. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
  345. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  346. /* Map the last 1M of flash where we're running from reset */
  347. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  348. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  349. #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  350. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  351. | BATL_MEMCOHERENCE)
  352. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  353. /*
  354. * BAT7 4M Cache-inhibited, guarded
  355. * 0xe800_0000 4M PIXIS
  356. */
  357. #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
  358. | BATL_GUARDEDSTORAGE)
  359. #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  360. #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  361. #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
  362. /*
  363. * Environment
  364. */
  365. #ifndef CONFIG_SYS_RAMBOOT
  366. #define CONFIG_ENV_IS_IN_FLASH 1
  367. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  368. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
  369. #define CONFIG_ENV_SIZE 0x2000
  370. #else
  371. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  372. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  373. #define CONFIG_ENV_SIZE 0x2000
  374. #endif
  375. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  376. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  377. /*
  378. * BOOTP options
  379. */
  380. #define CONFIG_BOOTP_BOOTFILESIZE
  381. #define CONFIG_BOOTP_BOOTPATH
  382. #define CONFIG_BOOTP_GATEWAY
  383. #define CONFIG_BOOTP_HOSTNAME
  384. /*
  385. * Command line configuration.
  386. */
  387. #include <config_cmd_default.h>
  388. #define CONFIG_CMD_PING
  389. #define CONFIG_CMD_I2C
  390. #define CONFIG_CMD_MII
  391. #if defined(CONFIG_SYS_RAMBOOT)
  392. #undef CONFIG_CMD_SAVEENV
  393. #endif
  394. #if defined(CONFIG_PCI)
  395. #define CONFIG_CMD_PCI
  396. #define CONFIG_CMD_SCSI
  397. #define CONFIG_CMD_EXT2
  398. #define CONFIG_CMD_USB
  399. #endif
  400. #define CONFIG_WATCHDOG /* watchdog enabled */
  401. #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
  402. /*DIU Configuration*/
  403. #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/
  404. /*
  405. * Miscellaneous configurable options
  406. */
  407. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  408. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  409. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  410. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  411. #if defined(CONFIG_CMD_KGDB)
  412. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  413. #else
  414. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  415. #endif
  416. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  417. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  418. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  419. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  420. /*
  421. * For booting Linux, the board info and command line data
  422. * have to be in the first 8 MB of memory, since this is
  423. * the maximum mapped by the Linux kernel during initialization.
  424. */
  425. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  426. /*
  427. * Internal Definitions
  428. *
  429. * Boot Flags
  430. */
  431. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  432. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  433. #if defined(CONFIG_CMD_KGDB)
  434. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  435. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  436. #endif
  437. /*
  438. * Environment Configuration
  439. */
  440. #define CONFIG_IPADDR 192.168.1.100
  441. #define CONFIG_HOSTNAME unknown
  442. #define CONFIG_ROOTPATH /opt/nfsroot
  443. #define CONFIG_BOOTFILE uImage
  444. #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
  445. #define CONFIG_SERVERIP 192.168.1.1
  446. #define CONFIG_GATEWAYIP 192.168.1.1
  447. #define CONFIG_NETMASK 255.255.255.0
  448. /* default location for tftp and bootm */
  449. #define CONFIG_LOADADDR 1000000
  450. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  451. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  452. #define CONFIG_BAUDRATE 115200
  453. #if defined(CONFIG_PCI1)
  454. #define PCI_ENV \
  455. "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
  456. "echo e;md ${a}e00 9\0" \
  457. "pci1regs=setenv a e0008; run pcireg\0" \
  458. "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
  459. "pci d.w $b.0 56 1\0" \
  460. "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
  461. "pci w.w $b.0 56 ffff\0" \
  462. "pci1err=setenv a e0008; run pcierr\0" \
  463. "pci1errc=setenv a e0008; run pcierrc\0"
  464. #else
  465. #define PCI_ENV ""
  466. #endif
  467. #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
  468. #define PCIE_ENV \
  469. "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
  470. "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
  471. "pcie1regs=setenv a e000a; run pciereg\0" \
  472. "pcie2regs=setenv a e0009; run pciereg\0" \
  473. "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
  474. "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
  475. "pci d $b.0 130 1\0" \
  476. "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
  477. "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
  478. "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
  479. "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
  480. "pcie1err=setenv a e000a; run pcieerr\0" \
  481. "pcie2err=setenv a e0009; run pcieerr\0" \
  482. "pcie1errc=setenv a e000a; run pcieerrc\0" \
  483. "pcie2errc=setenv a e0009; run pcieerrc\0"
  484. #else
  485. #define PCIE_ENV ""
  486. #endif
  487. #define DMA_ENV \
  488. "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
  489. "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
  490. "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
  491. "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
  492. "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
  493. "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
  494. "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
  495. "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
  496. #ifdef ENV_DEBUG
  497. #define CONFIG_EXTRA_ENV_SETTINGS \
  498. "netdev=eth0\0" \
  499. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  500. "tftpflash=tftpboot $loadaddr $uboot; " \
  501. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  502. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  503. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  504. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  505. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  506. "consoledev=ttyS0\0" \
  507. "ramdiskaddr=2000000\0" \
  508. "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
  509. "fdtaddr=c00000\0" \
  510. "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
  511. "bdev=sda3\0" \
  512. "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
  513. "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
  514. "maxcpus=1" \
  515. "eoi=mw e00400b0 0\0" \
  516. "iack=md e00400a0 1\0" \
  517. "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
  518. "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
  519. "md ${a}f00 5\0" \
  520. "ddr1regs=setenv a e0002; run ddrreg\0" \
  521. "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
  522. "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
  523. "md ${a}e60 1; md ${a}ef0 1d\0" \
  524. "guregs=setenv a e00e0; run gureg\0" \
  525. "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
  526. "mcmregs=setenv a e0001; run mcmreg\0" \
  527. "diuregs=md e002c000 1d\0" \
  528. "dium=mw e002c01c\0" \
  529. "diuerr=md e002c014 1\0" \
  530. "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
  531. "monitor=0-DVI\0" \
  532. "pmregs=md e00e1000 2b\0" \
  533. "lawregs=md e0000c08 4b\0" \
  534. "lbcregs=md e0005000 36\0" \
  535. "dma0regs=md e0021100 12\0" \
  536. "dma1regs=md e0021180 12\0" \
  537. "dma2regs=md e0021200 12\0" \
  538. "dma3regs=md e0021280 12\0" \
  539. PCI_ENV \
  540. PCIE_ENV \
  541. DMA_ENV
  542. #else
  543. #define CONFIG_EXTRA_ENV_SETTINGS \
  544. "netdev=eth0\0" \
  545. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  546. "consoledev=ttyS0\0" \
  547. "ramdiskaddr=2000000\0" \
  548. "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
  549. "fdtaddr=c00000\0" \
  550. "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
  551. "bdev=sda3\0" \
  552. "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
  553. "monitor=0-DVI\0"
  554. #endif
  555. #define CONFIG_NFSBOOTCOMMAND \
  556. "setenv bootargs root=/dev/nfs rw " \
  557. "nfsroot=$serverip:$rootpath " \
  558. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  559. "console=$consoledev,$baudrate $othbootargs;" \
  560. "tftp $loadaddr $bootfile;" \
  561. "tftp $fdtaddr $fdtfile;" \
  562. "bootm $loadaddr - $fdtaddr"
  563. #define CONFIG_RAMBOOTCOMMAND \
  564. "setenv bootargs root=/dev/ram rw " \
  565. "console=$consoledev,$baudrate $othbootargs;" \
  566. "tftp $ramdiskaddr $ramdiskfile;" \
  567. "tftp $loadaddr $bootfile;" \
  568. "tftp $fdtaddr $fdtfile;" \
  569. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  570. #define CONFIG_BOOTCOMMAND \
  571. "setenv bootargs root=/dev/$bdev rw " \
  572. "console=$consoledev,$baudrate $othbootargs;" \
  573. "tftp $loadaddr $bootfile;" \
  574. "tftp $fdtaddr $fdtfile;" \
  575. "bootm $loadaddr - $fdtaddr"
  576. #endif /* __CONFIG_H */