MPC8572DS.h 23 KB

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  1. /*
  2. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8572ds board configuration file
  24. *
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #ifdef CONFIG_MK_36BIT
  29. #define CONFIG_PHYS_64BIT
  30. #endif
  31. /* High Level Configuration Options */
  32. #define CONFIG_BOOKE 1 /* BOOKE */
  33. #define CONFIG_E500 1 /* BOOKE e500 family */
  34. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  35. #define CONFIG_MPC8572 1
  36. #define CONFIG_MPC8572DS 1
  37. #define CONFIG_MP 1 /* support multiple processors */
  38. #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
  39. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  40. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  41. #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
  42. #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
  43. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  44. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  45. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  46. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  47. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  48. #define CONFIG_ENV_OVERWRITE
  49. #ifndef __ASSEMBLY__
  50. extern unsigned long get_board_sys_clk(unsigned long dummy);
  51. extern unsigned long get_board_ddr_clk(unsigned long dummy);
  52. #endif
  53. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  54. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  55. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  56. #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
  57. from ICS307 instead of switches */
  58. /*
  59. * These can be toggled for performance analysis, otherwise use default.
  60. */
  61. #define CONFIG_L2_CACHE /* toggle L2 cache */
  62. #define CONFIG_BTB /* toggle branch predition */
  63. #define CONFIG_ENABLE_36BIT_PHYS 1
  64. #ifdef CONFIG_PHYS_64BIT
  65. #define CONFIG_ADDR_MAP 1
  66. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  67. #endif
  68. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
  69. #define CONFIG_SYS_MEMTEST_END 0x7fffffff
  70. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  71. /*
  72. * Base addresses -- Note these are effective addresses where the
  73. * actual resources get mapped (not physical addresses)
  74. */
  75. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  76. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  77. #ifdef CONFIG_PHYS_64BIT
  78. #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
  79. #else
  80. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  81. #endif
  82. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  83. #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
  84. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
  85. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
  86. /* DDR Setup */
  87. #define CONFIG_SYS_DDR_TLB_START 9
  88. #define CONFIG_VERY_BIG_RAM
  89. #define CONFIG_FSL_DDR2
  90. #undef CONFIG_FSL_DDR_INTERACTIVE
  91. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  92. #define CONFIG_DDR_SPD
  93. #undef CONFIG_DDR_DLL
  94. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  95. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  96. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  97. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  98. #define CONFIG_NUM_DDR_CONTROLLERS 2
  99. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  100. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  101. /* I2C addresses of SPD EEPROMs */
  102. #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
  103. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  104. #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
  105. /* These are used when DDR doesn't use SPD. */
  106. #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
  107. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
  108. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
  109. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  110. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  111. #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
  112. #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
  113. #define CONFIG_SYS_DDR_MODE_1 0x00440462
  114. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  115. #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
  116. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  117. #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
  118. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  119. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  120. #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
  121. #define CONFIG_SYS_DDR_CONTROL2 0x24400000
  122. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  123. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  124. #define CONFIG_SYS_DDR_SBE 0x00010000
  125. /*
  126. * Make sure required options are set
  127. */
  128. #ifndef CONFIG_SPD_EEPROM
  129. #error ("CONFIG_SPD_EEPROM is required")
  130. #endif
  131. #undef CONFIG_CLOCKS_IN_MHZ
  132. /*
  133. * Memory map
  134. *
  135. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  136. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  137. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  138. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  139. *
  140. * Localbus cacheable (TBD)
  141. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  142. *
  143. * Localbus non-cacheable
  144. * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
  145. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  146. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  147. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  148. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  149. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  150. */
  151. /*
  152. * Local Bus Definitions
  153. */
  154. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  155. #ifdef CONFIG_PHYS_64BIT
  156. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  157. #else
  158. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  159. #endif
  160. #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
  161. #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
  162. #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  163. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  164. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  165. #define CONFIG_SYS_FLASH_QUIET_TEST
  166. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  167. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  168. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  169. #undef CONFIG_SYS_FLASH_CHECKSUM
  170. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  171. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  172. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  173. #define CONFIG_FLASH_CFI_DRIVER
  174. #define CONFIG_SYS_FLASH_CFI
  175. #define CONFIG_SYS_FLASH_EMPTY_INFO
  176. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  177. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  178. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  179. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  180. #ifdef CONFIG_PHYS_64BIT
  181. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  182. #else
  183. #define PIXIS_BASE_PHYS PIXIS_BASE
  184. #endif
  185. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  186. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  187. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  188. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  189. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  190. #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
  191. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  192. #define PIXIS_PWR 0x5 /* PIXIS Power status register */
  193. #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
  194. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  195. #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
  196. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  197. #define PIXIS_VSTAT 0x11 /* VELA Status Register */
  198. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  199. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  200. #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
  201. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  202. #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
  203. #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
  204. #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
  205. #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
  206. #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
  207. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  208. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  209. #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
  210. #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
  211. #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
  212. #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
  213. #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
  214. #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
  215. #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
  216. #define PIXIS_VWATCH 0x24 /* Watchdog Register */
  217. #define PIXIS_LED 0x25 /* LED Register */
  218. /* old pixis referenced names */
  219. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  220. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  221. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
  222. #define PIXIS_VSPEED2_TSEC1SER 0x8
  223. #define PIXIS_VSPEED2_TSEC2SER 0x4
  224. #define PIXIS_VSPEED2_TSEC3SER 0x2
  225. #define PIXIS_VSPEED2_TSEC4SER 0x1
  226. #define PIXIS_VCFGEN1_TSEC1SER 0x20
  227. #define PIXIS_VCFGEN1_TSEC2SER 0x20
  228. #define PIXIS_VCFGEN1_TSEC3SER 0x20
  229. #define PIXIS_VCFGEN1_TSEC4SER 0x20
  230. #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
  231. | PIXIS_VSPEED2_TSEC2SER \
  232. | PIXIS_VSPEED2_TSEC3SER \
  233. | PIXIS_VSPEED2_TSEC4SER)
  234. #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
  235. | PIXIS_VCFGEN1_TSEC2SER \
  236. | PIXIS_VCFGEN1_TSEC3SER \
  237. | PIXIS_VCFGEN1_TSEC4SER)
  238. #define CONFIG_SYS_INIT_RAM_LOCK 1
  239. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  240. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  241. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  242. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  243. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  244. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  245. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  246. #define CONFIG_SYS_NAND_BASE 0xffa00000
  247. #ifdef CONFIG_PHYS_64BIT
  248. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  249. #else
  250. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  251. #endif
  252. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
  253. CONFIG_SYS_NAND_BASE + 0x40000, \
  254. CONFIG_SYS_NAND_BASE + 0x80000,\
  255. CONFIG_SYS_NAND_BASE + 0xC0000}
  256. #define CONFIG_SYS_MAX_NAND_DEVICE 4
  257. #define CONFIG_MTD_NAND_VERIFY_WRITE
  258. #define CONFIG_CMD_NAND 1
  259. #define CONFIG_NAND_FSL_ELBC 1
  260. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  261. /* NAND flash config */
  262. #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  263. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  264. | BR_PS_8 /* Port Size = 8 bit */ \
  265. | BR_MS_FCM /* MSEL = FCM */ \
  266. | BR_V) /* valid */
  267. #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  268. | OR_FCM_PGS /* Large Page*/ \
  269. | OR_FCM_CSCT \
  270. | OR_FCM_CST \
  271. | OR_FCM_CHT \
  272. | OR_FCM_SCY_1 \
  273. | OR_FCM_TRLX \
  274. | OR_FCM_EHTR)
  275. #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  276. #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  277. #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
  278. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  279. | BR_PS_8 /* Port Size = 8 bit */ \
  280. | BR_MS_FCM /* MSEL = FCM */ \
  281. | BR_V) /* valid */
  282. #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  283. #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
  284. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  285. | BR_PS_8 /* Port Size = 8 bit */ \
  286. | BR_MS_FCM /* MSEL = FCM */ \
  287. | BR_V) /* valid */
  288. #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  289. #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
  290. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  291. | BR_PS_8 /* Port Size = 8 bit */ \
  292. | BR_MS_FCM /* MSEL = FCM */ \
  293. | BR_V) /* valid */
  294. #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  295. /* Serial Port - controlled on board with jumper J8
  296. * open - index 2
  297. * shorted - index 1
  298. */
  299. #define CONFIG_CONS_INDEX 1
  300. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  301. #define CONFIG_SYS_NS16550
  302. #define CONFIG_SYS_NS16550_SERIAL
  303. #define CONFIG_SYS_NS16550_REG_SIZE 1
  304. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  305. #define CONFIG_SYS_BAUDRATE_TABLE \
  306. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  307. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  308. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  309. /* Use the HUSH parser */
  310. #define CONFIG_SYS_HUSH_PARSER
  311. #ifdef CONFIG_SYS_HUSH_PARSER
  312. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  313. #endif
  314. /*
  315. * Pass open firmware flat tree
  316. */
  317. #define CONFIG_OF_LIBFDT 1
  318. #define CONFIG_OF_BOARD_SETUP 1
  319. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  320. /* new uImage format support */
  321. #define CONFIG_FIT 1
  322. #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
  323. /* I2C */
  324. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  325. #define CONFIG_HARD_I2C /* I2C with hardware support */
  326. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  327. #define CONFIG_I2C_MULTI_BUS
  328. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  329. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  330. #define CONFIG_SYS_I2C_SLAVE 0x7F
  331. #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
  332. #define CONFIG_SYS_I2C_OFFSET 0x3000
  333. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  334. /*
  335. * I2C2 EEPROM
  336. */
  337. #define CONFIG_ID_EEPROM
  338. #ifdef CONFIG_ID_EEPROM
  339. #define CONFIG_SYS_I2C_EEPROM_NXID
  340. #endif
  341. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  342. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  343. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  344. /*
  345. * General PCI
  346. * Memory space is mapped 1-1, but I/O space must start from 0.
  347. */
  348. /* controller 3, direct to uli, tgtid 3, Base address 8000 */
  349. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  350. #ifdef CONFIG_PHYS_64BIT
  351. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  352. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
  353. #else
  354. #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  355. #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  356. #endif
  357. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  358. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  359. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  360. #ifdef CONFIG_PHYS_64BIT
  361. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
  362. #else
  363. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  364. #endif
  365. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  366. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  367. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  368. #ifdef CONFIG_PHYS_64BIT
  369. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  370. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  371. #else
  372. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  373. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  374. #endif
  375. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  376. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  377. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  378. #ifdef CONFIG_PHYS_64BIT
  379. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  380. #else
  381. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  382. #endif
  383. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  384. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  385. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  386. #ifdef CONFIG_PHYS_64BIT
  387. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  388. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  389. #else
  390. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  391. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  392. #endif
  393. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  394. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  395. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  396. #ifdef CONFIG_PHYS_64BIT
  397. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  398. #else
  399. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  400. #endif
  401. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  402. #if defined(CONFIG_PCI)
  403. /*PCIE video card used*/
  404. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
  405. /* video */
  406. #define CONFIG_VIDEO
  407. #if defined(CONFIG_VIDEO)
  408. #define CONFIG_BIOSEMU
  409. #define CONFIG_CFB_CONSOLE
  410. #define CONFIG_VIDEO_SW_CURSOR
  411. #define CONFIG_VGA_AS_SINGLE_DEVICE
  412. #define CONFIG_ATI_RADEON_FB
  413. #define CONFIG_VIDEO_LOGO
  414. /*#define CONFIG_CONSOLE_CURSOR*/
  415. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  416. #endif
  417. #define CONFIG_NET_MULTI
  418. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  419. #undef CONFIG_EEPRO100
  420. #undef CONFIG_TULIP
  421. #undef CONFIG_RTL8139
  422. #ifndef CONFIG_PCI_PNP
  423. #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
  424. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
  425. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  426. #endif
  427. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  428. #define CONFIG_DOS_PARTITION
  429. #define CONFIG_SCSI_AHCI
  430. #ifdef CONFIG_SCSI_AHCI
  431. #define CONFIG_SATA_ULI5288
  432. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  433. #define CONFIG_SYS_SCSI_MAX_LUN 1
  434. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  435. #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
  436. #endif /* SCSI */
  437. #endif /* CONFIG_PCI */
  438. #if defined(CONFIG_TSEC_ENET)
  439. #ifndef CONFIG_NET_MULTI
  440. #define CONFIG_NET_MULTI 1
  441. #endif
  442. #define CONFIG_MII 1 /* MII PHY management */
  443. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  444. #define CONFIG_TSEC1 1
  445. #define CONFIG_TSEC1_NAME "eTSEC1"
  446. #define CONFIG_TSEC2 1
  447. #define CONFIG_TSEC2_NAME "eTSEC2"
  448. #define CONFIG_TSEC3 1
  449. #define CONFIG_TSEC3_NAME "eTSEC3"
  450. #define CONFIG_TSEC4 1
  451. #define CONFIG_TSEC4_NAME "eTSEC4"
  452. #define CONFIG_PIXIS_SGMII_CMD
  453. #define CONFIG_FSL_SGMII_RISER 1
  454. #define SGMII_RISER_PHY_OFFSET 0x1c
  455. #ifdef CONFIG_FSL_SGMII_RISER
  456. #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
  457. #endif
  458. #define TSEC1_PHY_ADDR 0
  459. #define TSEC2_PHY_ADDR 1
  460. #define TSEC3_PHY_ADDR 2
  461. #define TSEC4_PHY_ADDR 3
  462. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  463. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  464. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  465. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  466. #define TSEC1_PHYIDX 0
  467. #define TSEC2_PHYIDX 0
  468. #define TSEC3_PHYIDX 0
  469. #define TSEC4_PHYIDX 0
  470. #define CONFIG_ETHPRIME "eTSEC1"
  471. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  472. #endif /* CONFIG_TSEC_ENET */
  473. /*
  474. * Environment
  475. */
  476. #define CONFIG_ENV_IS_IN_FLASH 1
  477. #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
  478. #define CONFIG_ENV_ADDR 0xfff80000
  479. #else
  480. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  481. #endif
  482. #define CONFIG_ENV_SIZE 0x2000
  483. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  484. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  485. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  486. /*
  487. * Command line configuration.
  488. */
  489. #include <config_cmd_default.h>
  490. #define CONFIG_CMD_IRQ
  491. #define CONFIG_CMD_PING
  492. #define CONFIG_CMD_I2C
  493. #define CONFIG_CMD_MII
  494. #define CONFIG_CMD_ELF
  495. #define CONFIG_CMD_IRQ
  496. #define CONFIG_CMD_SETEXPR
  497. #if defined(CONFIG_PCI)
  498. #define CONFIG_CMD_PCI
  499. #define CONFIG_CMD_NET
  500. #define CONFIG_CMD_SCSI
  501. #define CONFIG_CMD_EXT2
  502. #endif
  503. #undef CONFIG_WATCHDOG /* watchdog disabled */
  504. /*
  505. * Miscellaneous configurable options
  506. */
  507. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  508. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  509. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  510. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  511. #if defined(CONFIG_CMD_KGDB)
  512. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  513. #else
  514. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  515. #endif
  516. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  517. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  518. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  519. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  520. /*
  521. * For booting Linux, the board info and command line data
  522. * have to be in the first 16 MB of memory, since this is
  523. * the maximum mapped by the Linux kernel during initialization.
  524. */
  525. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  526. /*
  527. * Internal Definitions
  528. *
  529. * Boot Flags
  530. */
  531. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  532. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  533. #if defined(CONFIG_CMD_KGDB)
  534. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  535. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  536. #endif
  537. /*
  538. * Environment Configuration
  539. */
  540. /* The mac addresses for all ethernet interface */
  541. #if defined(CONFIG_TSEC_ENET)
  542. #define CONFIG_HAS_ETH0
  543. #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
  544. #define CONFIG_HAS_ETH1
  545. #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
  546. #define CONFIG_HAS_ETH2
  547. #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
  548. #define CONFIG_HAS_ETH3
  549. #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
  550. #endif
  551. #define CONFIG_IPADDR 192.168.1.254
  552. #define CONFIG_HOSTNAME unknown
  553. #define CONFIG_ROOTPATH /opt/nfsroot
  554. #define CONFIG_BOOTFILE uImage
  555. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  556. #define CONFIG_SERVERIP 192.168.1.1
  557. #define CONFIG_GATEWAYIP 192.168.1.1
  558. #define CONFIG_NETMASK 255.255.255.0
  559. /* default location for tftp and bootm */
  560. #define CONFIG_LOADADDR 1000000
  561. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  562. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  563. #define CONFIG_BAUDRATE 115200
  564. #define CONFIG_EXTRA_ENV_SETTINGS \
  565. "memctl_intlv_ctl=2\0" \
  566. "netdev=eth0\0" \
  567. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  568. "tftpflash=tftpboot $loadaddr $uboot; " \
  569. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  570. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  571. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  572. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  573. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  574. "consoledev=ttyS0\0" \
  575. "ramdiskaddr=2000000\0" \
  576. "ramdiskfile=8572ds/ramdisk.uboot\0" \
  577. "fdtaddr=c00000\0" \
  578. "fdtfile=8572ds/mpc8572ds.dtb\0" \
  579. "bdev=sda3\0"
  580. #define CONFIG_HDBOOT \
  581. "setenv bootargs root=/dev/$bdev rw " \
  582. "console=$consoledev,$baudrate $othbootargs;" \
  583. "tftp $loadaddr $bootfile;" \
  584. "tftp $fdtaddr $fdtfile;" \
  585. "bootm $loadaddr - $fdtaddr"
  586. #define CONFIG_NFSBOOTCOMMAND \
  587. "setenv bootargs root=/dev/nfs rw " \
  588. "nfsroot=$serverip:$rootpath " \
  589. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  590. "console=$consoledev,$baudrate $othbootargs;" \
  591. "tftp $loadaddr $bootfile;" \
  592. "tftp $fdtaddr $fdtfile;" \
  593. "bootm $loadaddr - $fdtaddr"
  594. #define CONFIG_RAMBOOTCOMMAND \
  595. "setenv bootargs root=/dev/ram rw " \
  596. "console=$consoledev,$baudrate $othbootargs;" \
  597. "tftp $ramdiskaddr $ramdiskfile;" \
  598. "tftp $loadaddr $bootfile;" \
  599. "tftp $fdtaddr $fdtfile;" \
  600. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  601. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  602. #endif /* __CONFIG_H */