MPC8569MDS.h 19 KB

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  1. /*
  2. * Copyright (C) 2009 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8569mds board configuration file
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. /* High Level Configuration Options */
  28. #define CONFIG_BOOKE 1 /* BOOKE */
  29. #define CONFIG_E500 1 /* BOOKE e500 family */
  30. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
  31. #define CONFIG_MPC8569 1 /* MPC8569 specific */
  32. #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
  33. #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
  34. #define CONFIG_PCI 1 /* Disable PCI/PCIE */
  35. #define CONFIG_PCIE1 1 /* PCIE controller */
  36. #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
  37. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  38. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  39. #define CONFIG_QE /* Enable QE */
  40. #define CONFIG_ENV_OVERWRITE
  41. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  42. #ifndef __ASSEMBLY__
  43. extern unsigned long get_clock_freq(void);
  44. #endif
  45. /* Replace a call to get_clock_freq (after it is implemented)*/
  46. #define CONFIG_SYS_CLK_FREQ 66666666
  47. #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
  48. /*
  49. * These can be toggled for performance analysis, otherwise use default.
  50. */
  51. #define CONFIG_L2_CACHE /* toggle L2 cache */
  52. #define CONFIG_BTB /* toggle branch predition */
  53. /*
  54. * Only possible on E500 Version 2 or newer cores.
  55. */
  56. #define CONFIG_ENABLE_36BIT_PHYS 1
  57. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  58. #define CONFIG_HWCONFIG
  59. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  60. #define CONFIG_SYS_MEMTEST_END 0x00400000
  61. /*
  62. * Base addresses -- Note these are effective addresses where the
  63. * actual resources get mapped (not physical addresses)
  64. */
  65. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  66. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  67. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  68. /* physical addr of CCSRBAR */
  69. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  70. /* PQII uses CONFIG_SYS_IMMR */
  71. #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
  72. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
  73. /* DDR Setup */
  74. #define CONFIG_FSL_DDR3
  75. #undef CONFIG_FSL_DDR_INTERACTIVE
  76. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  77. #define CONFIG_DDR_SPD
  78. #define CONFIG_DDR_DLL /* possible DLL fix needed */
  79. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  80. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  81. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  82. /* DDR is system memory*/
  83. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  84. #define CONFIG_NUM_DDR_CONTROLLERS 1
  85. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  86. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  87. /* I2C addresses of SPD EEPROMs */
  88. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  89. #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
  90. /* These are used when DDR doesn't use SPD. */
  91. #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
  92. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  93. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
  94. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  95. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  96. #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
  97. #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
  98. #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
  99. #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
  100. #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
  101. #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
  102. #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
  103. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  104. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
  105. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  106. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  107. #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
  108. #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
  109. #define CONFIG_SYS_DDR_CDR_1 0x80040000
  110. #define CONFIG_SYS_DDR_CDR_2 0x00000000
  111. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  112. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  113. #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
  114. #define CONFIG_SYS_DDR_CONTROL2 0x24400000
  115. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  116. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  117. #define CONFIG_SYS_DDR_SBE 0x00010000
  118. #undef CONFIG_CLOCKS_IN_MHZ
  119. /*
  120. * Local Bus Definitions
  121. */
  122. #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
  123. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  124. #define CONFIG_SYS_BCSR_BASE 0xf8000000
  125. #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
  126. /*Chip select 0 - Flash*/
  127. #define CONFIG_SYS_BR0_PRELIM 0xfe000801
  128. #define CONFIG_SYS_OR0_PRELIM 0xfe000ff7
  129. /*Chip select 1 - BCSR*/
  130. #define CONFIG_SYS_BR1_PRELIM 0xf8000801
  131. #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
  132. /*Chip select 4 - PIB*/
  133. #define CONFIG_SYS_BR4_PRELIM 0xf8008801
  134. #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
  135. /*Chip select 5 - PIB*/
  136. #define CONFIG_SYS_BR5_PRELIM 0xf8010801
  137. #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
  138. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  139. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  140. #undef CONFIG_SYS_FLASH_CHECKSUM
  141. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  142. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  143. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  144. #define CONFIG_FLASH_CFI_DRIVER
  145. #define CONFIG_SYS_FLASH_CFI
  146. #define CONFIG_SYS_FLASH_EMPTY_INFO
  147. /* Chip select 3 - NAND */
  148. #define CONFIG_SYS_NAND_BASE 0xFC000000
  149. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  150. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
  151. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  152. #define CONFIG_MTD_NAND_VERIFY_WRITE 1
  153. #define CONFIG_CMD_NAND 1
  154. #define CONFIG_NAND_FSL_ELBC 1
  155. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  156. #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  157. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  158. | BR_PS_8 /* Port Size = 8 bit */ \
  159. | BR_MS_FCM /* MSEL = FCM */ \
  160. | BR_V) /* valid */
  161. #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  162. | OR_FCM_CSCT \
  163. | OR_FCM_CST \
  164. | OR_FCM_CHT \
  165. | OR_FCM_SCY_1 \
  166. | OR_FCM_TRLX \
  167. | OR_FCM_EHTR)
  168. #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  169. #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  170. /*
  171. * SDRAM on the LocalBus
  172. */
  173. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  174. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  175. #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
  176. #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
  177. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  178. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  179. #define CONFIG_SYS_INIT_RAM_LOCK 1
  180. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  181. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
  182. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  183. #define CONFIG_SYS_GBL_DATA_OFFSET \
  184. (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  185. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  186. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  187. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  188. /* Serial Port */
  189. #define CONFIG_CONS_INDEX 1
  190. #define CONFIG_SERIAL_MULTI 1
  191. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  192. #define CONFIG_SYS_NS16550
  193. #define CONFIG_SYS_NS16550_SERIAL
  194. #define CONFIG_SYS_NS16550_REG_SIZE 1
  195. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  196. #define CONFIG_SYS_BAUDRATE_TABLE \
  197. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  198. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  199. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  200. /* Use the HUSH parser*/
  201. #define CONFIG_SYS_HUSH_PARSER
  202. #ifdef CONFIG_SYS_HUSH_PARSER
  203. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  204. #endif
  205. /* pass open firmware flat tree */
  206. #define CONFIG_OF_LIBFDT 1
  207. #define CONFIG_OF_BOARD_SETUP 1
  208. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  209. /*
  210. * I2C
  211. */
  212. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  213. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  214. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  215. #define CONFIG_I2C_MULTI_BUS
  216. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  217. #define CONFIG_SYS_I2C_SLAVE 0x7F
  218. #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
  219. #define CONFIG_SYS_I2C_OFFSET 0x3000
  220. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  221. /*
  222. * I2C2 EEPROM
  223. */
  224. #define CONFIG_ID_EEPROM
  225. #ifdef CONFIG_ID_EEPROM
  226. #define CONFIG_SYS_I2C_EEPROM_NXID
  227. #endif
  228. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  229. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  230. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  231. #define PLPPAR1_I2C_BIT_MASK 0x0000000F
  232. #define PLPPAR1_I2C2_VAL 0x00000000
  233. #define PLPPAR1_ESDHC_VAL 0x0000000A
  234. #define PLPDIR1_I2C_BIT_MASK 0x0000000F
  235. #define PLPDIR1_I2C2_VAL 0x0000000F
  236. #define PLPDIR1_ESDHC_VAL 0x00000006
  237. /*
  238. * General PCI
  239. * Memory Addresses are mapped 1-1. I/O is mapped from 0
  240. */
  241. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  242. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  243. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  244. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  245. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  246. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  247. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
  248. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  249. #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
  250. #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
  251. #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
  252. #ifdef CONFIG_QE
  253. /*
  254. * QE UEC ethernet configuration
  255. */
  256. #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
  257. #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
  258. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  259. #define CONFIG_UEC_ETH
  260. #define CONFIG_ETHPRIME "FSL UEC0"
  261. #define CONFIG_PHY_MODE_NEED_CHANGE
  262. #define CONFIG_UEC_ETH1 /* GETH1 */
  263. #define CONFIG_HAS_ETH0
  264. #ifdef CONFIG_UEC_ETH1
  265. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  266. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
  267. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  268. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
  269. #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
  270. #define CONFIG_SYS_UEC1_PHY_ADDR 7
  271. #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
  272. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  273. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
  274. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  275. #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
  276. #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
  277. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  278. #endif /* CONFIG_UEC_ETH1 */
  279. #define CONFIG_UEC_ETH2 /* GETH2 */
  280. #define CONFIG_HAS_ETH1
  281. #ifdef CONFIG_UEC_ETH2
  282. #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
  283. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
  284. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  285. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
  286. #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
  287. #define CONFIG_SYS_UEC2_PHY_ADDR 1
  288. #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
  289. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  290. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
  291. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  292. #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
  293. #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
  294. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  295. #endif /* CONFIG_UEC_ETH2 */
  296. #define CONFIG_UEC_ETH3 /* GETH3 */
  297. #define CONFIG_HAS_ETH2
  298. #ifdef CONFIG_UEC_ETH3
  299. #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
  300. #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
  301. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  302. #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
  303. #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
  304. #define CONFIG_SYS_UEC3_PHY_ADDR 2
  305. #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
  306. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  307. #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
  308. #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
  309. #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
  310. #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
  311. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  312. #endif /* CONFIG_UEC_ETH3 */
  313. #define CONFIG_UEC_ETH4 /* GETH4 */
  314. #define CONFIG_HAS_ETH3
  315. #ifdef CONFIG_UEC_ETH4
  316. #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
  317. #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
  318. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  319. #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
  320. #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
  321. #define CONFIG_SYS_UEC4_PHY_ADDR 3
  322. #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
  323. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  324. #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
  325. #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
  326. #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
  327. #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
  328. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  329. #endif /* CONFIG_UEC_ETH4 */
  330. #undef CONFIG_UEC_ETH6 /* GETH6 */
  331. #define CONFIG_HAS_ETH5
  332. #ifdef CONFIG_UEC_ETH6
  333. #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
  334. #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
  335. #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
  336. #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
  337. #define CONFIG_SYS_UEC6_PHY_ADDR 4
  338. #define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
  339. #endif /* CONFIG_UEC_ETH6 */
  340. #undef CONFIG_UEC_ETH8 /* GETH8 */
  341. #define CONFIG_HAS_ETH7
  342. #ifdef CONFIG_UEC_ETH8
  343. #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
  344. #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
  345. #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
  346. #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
  347. #define CONFIG_SYS_UEC8_PHY_ADDR 6
  348. #define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
  349. #endif /* CONFIG_UEC_ETH8 */
  350. #endif /* CONFIG_QE */
  351. #if defined(CONFIG_PCI)
  352. #define CONFIG_NET_MULTI
  353. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  354. #undef CONFIG_EEPRO100
  355. #undef CONFIG_TULIP
  356. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  357. #endif /* CONFIG_PCI */
  358. #ifndef CONFIG_NET_MULTI
  359. #define CONFIG_NET_MULTI 1
  360. #endif
  361. /*
  362. * Environment
  363. */
  364. #define CONFIG_ENV_IS_IN_FLASH 1
  365. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  366. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
  367. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  368. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  369. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  370. /* QE microcode/firmware address */
  371. #define CONFIG_SYS_QE_FW_ADDR 0xfff00000
  372. /*
  373. * BOOTP options
  374. */
  375. #define CONFIG_BOOTP_BOOTFILESIZE
  376. #define CONFIG_BOOTP_BOOTPATH
  377. #define CONFIG_BOOTP_GATEWAY
  378. #define CONFIG_BOOTP_HOSTNAME
  379. /*
  380. * Command line configuration.
  381. */
  382. #include <config_cmd_default.h>
  383. #define CONFIG_CMD_PING
  384. #define CONFIG_CMD_I2C
  385. #define CONFIG_CMD_MII
  386. #define CONFIG_CMD_ELF
  387. #define CONFIG_CMD_IRQ
  388. #define CONFIG_CMD_SETEXPR
  389. #if defined(CONFIG_PCI)
  390. #define CONFIG_CMD_PCI
  391. #endif
  392. #undef CONFIG_WATCHDOG /* watchdog disabled */
  393. #define CONFIG_MMC 1
  394. #ifdef CONFIG_MMC
  395. #define CONFIG_FSL_ESDHC
  396. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  397. #define CONFIG_CMD_MMC
  398. #define CONFIG_GENERIC_MMC
  399. #define CONFIG_CMD_EXT2
  400. #define CONFIG_CMD_FAT
  401. #define CONFIG_DOS_PARTITION
  402. #endif
  403. /*
  404. * Miscellaneous configurable options
  405. */
  406. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  407. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  408. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  409. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  410. #if defined(CONFIG_CMD_KGDB)
  411. #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
  412. #else
  413. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  414. #endif
  415. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  416. /* Print Buffer Size */
  417. #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  418. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  419. /* Boot Argument Buffer Size */
  420. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  421. /*
  422. * For booting Linux, the board info and command line data
  423. * have to be in the first 16 MB of memory, since this is
  424. * the maximum mapped by the Linux kernel during initialization.
  425. */
  426. #define CONFIG_SYS_BOOTMAPSZ (16 << 20)
  427. /* Initial Memory map for Linux*/
  428. /*
  429. * Internal Definitions
  430. *
  431. * Boot Flags
  432. */
  433. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  434. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  435. #if defined(CONFIG_CMD_KGDB)
  436. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  437. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  438. #endif
  439. /*
  440. * Environment Configuration
  441. */
  442. #define CONFIG_HOSTNAME mpc8569mds
  443. #define CONFIG_ROOTPATH /nfsroot
  444. #define CONFIG_BOOTFILE your.uImage
  445. #define CONFIG_SERVERIP 192.168.1.1
  446. #define CONFIG_GATEWAYIP 192.168.1.1
  447. #define CONFIG_NETMASK 255.255.255.0
  448. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  449. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  450. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  451. #define CONFIG_BAUDRATE 115200
  452. #define CONFIG_EXTRA_ENV_SETTINGS \
  453. "netdev=eth0\0" \
  454. "consoledev=ttyS0\0" \
  455. "ramdiskaddr=600000\0" \
  456. "ramdiskfile=your.ramdisk.u-boot\0" \
  457. "fdtaddr=400000\0" \
  458. "fdtfile=your.fdt.dtb\0" \
  459. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  460. "nfsroot=$serverip:$rootpath " \
  461. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  462. "console=$consoledev,$baudrate $othbootargs\0" \
  463. "ramargs=setenv bootargs root=/dev/ram rw " \
  464. "console=$consoledev,$baudrate $othbootargs\0" \
  465. #define CONFIG_NFSBOOTCOMMAND \
  466. "run nfsargs;" \
  467. "tftp $loadaddr $bootfile;" \
  468. "tftp $fdtaddr $fdtfile;" \
  469. "bootm $loadaddr - $fdtaddr"
  470. #define CONFIG_RAMBOOTCOMMAND \
  471. "run ramargs;" \
  472. "tftp $ramdiskaddr $ramdiskfile;" \
  473. "tftp $loadaddr $bootfile;" \
  474. "bootm $loadaddr $ramdiskaddr"
  475. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  476. #endif /* __CONFIG_H */