MPC8568MDS.h 17 KB

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  1. /*
  2. * Copyright 2004-2007 Freescale Semiconductor.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8568mds board configuration file
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. /* High Level Configuration Options */
  28. #define CONFIG_BOOKE 1 /* BOOKE */
  29. #define CONFIG_E500 1 /* BOOKE e500 family */
  30. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
  31. #define CONFIG_MPC8568 1 /* MPC8568 specific */
  32. #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
  33. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  34. #define CONFIG_PCI1 1 /* PCI controller */
  35. #define CONFIG_PCIE1 1 /* PCIE controller */
  36. #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
  37. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  38. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  39. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  40. #define CONFIG_QE /* Enable QE */
  41. #define CONFIG_ENV_OVERWRITE
  42. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  43. #ifndef __ASSEMBLY__
  44. extern unsigned long get_clock_freq(void);
  45. #endif /*Replace a call to get_clock_freq (after it is implemented)*/
  46. #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
  47. /*
  48. * These can be toggled for performance analysis, otherwise use default.
  49. */
  50. #define CONFIG_L2_CACHE /* toggle L2 cache */
  51. #define CONFIG_BTB /* toggle branch predition */
  52. /*
  53. * Only possible on E500 Version 2 or newer cores.
  54. */
  55. #define CONFIG_ENABLE_36BIT_PHYS 1
  56. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  57. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  58. #define CONFIG_SYS_MEMTEST_END 0x00400000
  59. /*
  60. * Base addresses -- Note these are effective addresses where the
  61. * actual resources get mapped (not physical addresses)
  62. */
  63. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  64. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  65. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  66. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  67. #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
  68. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
  69. /* DDR Setup */
  70. #define CONFIG_FSL_DDR2
  71. #undef CONFIG_FSL_DDR_INTERACTIVE
  72. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  73. #define CONFIG_DDR_SPD
  74. #define CONFIG_DDR_DLL /* possible DLL fix needed */
  75. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  76. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  77. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  78. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  79. #define CONFIG_NUM_DDR_CONTROLLERS 1
  80. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  81. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  82. /* I2C addresses of SPD EEPROMs */
  83. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  84. /* Make sure required options are set */
  85. #ifndef CONFIG_SPD_EEPROM
  86. #error ("CONFIG_SPD_EEPROM is required")
  87. #endif
  88. #undef CONFIG_CLOCKS_IN_MHZ
  89. /*
  90. * Local Bus Definitions
  91. */
  92. /*
  93. * FLASH on the Local Bus
  94. * Two banks, 8M each, using the CFI driver.
  95. * Boot from BR0/OR0 bank at 0xff00_0000
  96. * Alternate BR1/OR1 bank at 0xff80_0000
  97. *
  98. * BR0, BR1:
  99. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  100. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  101. * Port Size = 16 bits = BRx[19:20] = 10
  102. * Use GPCM = BRx[24:26] = 000
  103. * Valid = BRx[31] = 1
  104. *
  105. * 0 4 8 12 16 20 24 28
  106. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  107. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  108. *
  109. * OR0, OR1:
  110. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  111. * Reserved ORx[17:18] = 11, confusion here?
  112. * CSNT = ORx[20] = 1
  113. * ACS = half cycle delay = ORx[21:22] = 11
  114. * SCY = 6 = ORx[24:27] = 0110
  115. * TRLX = use relaxed timing = ORx[29] = 1
  116. * EAD = use external address latch delay = OR[31] = 1
  117. *
  118. * 0 4 8 12 16 20 24 28
  119. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  120. */
  121. #define CONFIG_SYS_BCSR_BASE 0xf8000000
  122. #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
  123. /*Chip select 0 - Flash*/
  124. #define CONFIG_SYS_BR0_PRELIM 0xfe001001
  125. #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
  126. /*Chip slelect 1 - BCSR*/
  127. #define CONFIG_SYS_BR1_PRELIM 0xf8000801
  128. #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
  129. /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
  130. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  131. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  132. #undef CONFIG_SYS_FLASH_CHECKSUM
  133. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  134. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  135. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  136. #define CONFIG_FLASH_CFI_DRIVER
  137. #define CONFIG_SYS_FLASH_CFI
  138. #define CONFIG_SYS_FLASH_EMPTY_INFO
  139. /*
  140. * SDRAM on the LocalBus
  141. */
  142. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  143. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  144. /*Chip select 2 - SDRAM*/
  145. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  146. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  147. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  148. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  149. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  150. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  151. /*
  152. * Common settings for all Local Bus SDRAM commands.
  153. * At run time, either BSMA1516 (for CPU 1.1)
  154. * or BSMA1617 (for CPU 1.0) (old)
  155. * is OR'ed in too.
  156. */
  157. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  158. | LSDMR_PRETOACT7 \
  159. | LSDMR_ACTTORW7 \
  160. | LSDMR_BL8 \
  161. | LSDMR_WRC4 \
  162. | LSDMR_CL3 \
  163. | LSDMR_RFEN \
  164. )
  165. /*
  166. * The bcsr registers are connected to CS3 on MDS.
  167. * The new memory map places bcsr at 0xf8000000.
  168. *
  169. * For BR3, need:
  170. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  171. * port-size = 8-bits = BR[19:20] = 01
  172. * no parity checking = BR[21:22] = 00
  173. * GPMC for MSEL = BR[24:26] = 000
  174. * Valid = BR[31] = 1
  175. *
  176. * 0 4 8 12 16 20 24 28
  177. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  178. *
  179. * For OR3, need:
  180. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  181. * disable buffer ctrl OR[19] = 0
  182. * CSNT OR[20] = 1
  183. * ACS OR[21:22] = 11
  184. * XACS OR[23] = 1
  185. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  186. * SETA OR[28] = 0
  187. * TRLX OR[29] = 1
  188. * EHTR OR[30] = 1
  189. * EAD extra time OR[31] = 1
  190. *
  191. * 0 4 8 12 16 20 24 28
  192. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  193. */
  194. #define CONFIG_SYS_BCSR (0xf8000000)
  195. /*Chip slelect 4 - PIB*/
  196. #define CONFIG_SYS_BR4_PRELIM 0xf8008801
  197. #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
  198. /*Chip select 5 - PIB*/
  199. #define CONFIG_SYS_BR5_PRELIM 0xf8010801
  200. #define CONFIG_SYS_OR5_PRELIM 0xffff69f7
  201. #define CONFIG_SYS_INIT_RAM_LOCK 1
  202. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  203. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
  204. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  205. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  206. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  207. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  208. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  209. /* Serial Port */
  210. #define CONFIG_CONS_INDEX 1
  211. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  212. #define CONFIG_SYS_NS16550
  213. #define CONFIG_SYS_NS16550_SERIAL
  214. #define CONFIG_SYS_NS16550_REG_SIZE 1
  215. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  216. #define CONFIG_SYS_BAUDRATE_TABLE \
  217. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  218. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  219. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  220. /* Use the HUSH parser*/
  221. #define CONFIG_SYS_HUSH_PARSER
  222. #ifdef CONFIG_SYS_HUSH_PARSER
  223. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  224. #endif
  225. /* pass open firmware flat tree */
  226. #define CONFIG_OF_LIBFDT 1
  227. #define CONFIG_OF_BOARD_SETUP 1
  228. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  229. /*
  230. * I2C
  231. */
  232. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  233. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  234. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  235. #define CONFIG_I2C_MULTI_BUS
  236. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  237. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  238. #define CONFIG_SYS_I2C_SLAVE 0x7F
  239. #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
  240. #define CONFIG_SYS_I2C_OFFSET 0x3000
  241. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  242. /*
  243. * General PCI
  244. * Memory Addresses are mapped 1-1. I/O is mapped from 0
  245. */
  246. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  247. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  248. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  249. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  250. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  251. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  252. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  253. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
  254. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  255. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  256. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  257. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  258. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  259. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  260. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
  261. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  262. #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
  263. #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
  264. #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
  265. #ifdef CONFIG_QE
  266. /*
  267. * QE UEC ethernet configuration
  268. */
  269. #define CONFIG_UEC_ETH
  270. #ifndef CONFIG_TSEC_ENET
  271. #define CONFIG_ETHPRIME "FSL UEC0"
  272. #endif
  273. #define CONFIG_PHY_MODE_NEED_CHANGE
  274. #define CONFIG_eTSEC_MDIO_BUS
  275. #ifdef CONFIG_eTSEC_MDIO_BUS
  276. #define CONFIG_MIIM_ADDRESS 0xE0024520
  277. #endif
  278. #define CONFIG_UEC_ETH1 /* GETH1 */
  279. #ifdef CONFIG_UEC_ETH1
  280. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  281. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
  282. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
  283. #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
  284. #define CONFIG_SYS_UEC1_PHY_ADDR 7
  285. #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
  286. #endif
  287. #define CONFIG_UEC_ETH2 /* GETH2 */
  288. #ifdef CONFIG_UEC_ETH2
  289. #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
  290. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
  291. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
  292. #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
  293. #define CONFIG_SYS_UEC2_PHY_ADDR 1
  294. #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
  295. #endif
  296. #endif /* CONFIG_QE */
  297. #if defined(CONFIG_PCI)
  298. #define CONFIG_NET_MULTI
  299. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  300. #undef CONFIG_EEPRO100
  301. #undef CONFIG_TULIP
  302. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  303. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  304. #endif /* CONFIG_PCI */
  305. #ifndef CONFIG_NET_MULTI
  306. #define CONFIG_NET_MULTI 1
  307. #endif
  308. #if defined(CONFIG_TSEC_ENET)
  309. #define CONFIG_MII 1 /* MII PHY management */
  310. #define CONFIG_TSEC1 1
  311. #define CONFIG_TSEC1_NAME "eTSEC0"
  312. #define CONFIG_TSEC2 1
  313. #define CONFIG_TSEC2_NAME "eTSEC1"
  314. #define TSEC1_PHY_ADDR 2
  315. #define TSEC2_PHY_ADDR 3
  316. #define TSEC1_PHYIDX 0
  317. #define TSEC2_PHYIDX 0
  318. #define TSEC1_FLAGS TSEC_GIGABIT
  319. #define TSEC2_FLAGS TSEC_GIGABIT
  320. /* Options are: eTSEC[0-1] */
  321. #define CONFIG_ETHPRIME "eTSEC0"
  322. #endif /* CONFIG_TSEC_ENET */
  323. /*
  324. * Environment
  325. */
  326. #define CONFIG_ENV_IS_IN_FLASH 1
  327. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  328. #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  329. #define CONFIG_ENV_SIZE 0x2000
  330. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  331. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  332. /*
  333. * BOOTP options
  334. */
  335. #define CONFIG_BOOTP_BOOTFILESIZE
  336. #define CONFIG_BOOTP_BOOTPATH
  337. #define CONFIG_BOOTP_GATEWAY
  338. #define CONFIG_BOOTP_HOSTNAME
  339. /*
  340. * Command line configuration.
  341. */
  342. #include <config_cmd_default.h>
  343. #define CONFIG_CMD_PING
  344. #define CONFIG_CMD_I2C
  345. #define CONFIG_CMD_MII
  346. #define CONFIG_CMD_ELF
  347. #define CONFIG_CMD_IRQ
  348. #define CONFIG_CMD_SETEXPR
  349. #if defined(CONFIG_PCI)
  350. #define CONFIG_CMD_PCI
  351. #endif
  352. #undef CONFIG_WATCHDOG /* watchdog disabled */
  353. /*
  354. * Miscellaneous configurable options
  355. */
  356. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  357. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  358. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  359. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  360. #if defined(CONFIG_CMD_KGDB)
  361. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  362. #else
  363. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  364. #endif
  365. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  366. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  367. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  368. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  369. /*
  370. * For booting Linux, the board info and command line data
  371. * have to be in the first 16 MB of memory, since this is
  372. * the maximum mapped by the Linux kernel during initialization.
  373. */
  374. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  375. /*
  376. * Internal Definitions
  377. *
  378. * Boot Flags
  379. */
  380. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  381. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  382. #if defined(CONFIG_CMD_KGDB)
  383. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  384. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  385. #endif
  386. /*
  387. * Environment Configuration
  388. */
  389. /* The mac addresses for all ethernet interface */
  390. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
  391. #define CONFIG_HAS_ETH0
  392. #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  393. #define CONFIG_HAS_ETH1
  394. #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  395. #define CONFIG_HAS_ETH2
  396. #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  397. #define CONFIG_HAS_ETH3
  398. #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
  399. #endif
  400. #define CONFIG_IPADDR 192.168.1.253
  401. #define CONFIG_HOSTNAME unknown
  402. #define CONFIG_ROOTPATH /nfsroot
  403. #define CONFIG_BOOTFILE your.uImage
  404. #define CONFIG_SERVERIP 192.168.1.1
  405. #define CONFIG_GATEWAYIP 192.168.1.1
  406. #define CONFIG_NETMASK 255.255.255.0
  407. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  408. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  409. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  410. #define CONFIG_BAUDRATE 115200
  411. #define CONFIG_EXTRA_ENV_SETTINGS \
  412. "netdev=eth0\0" \
  413. "consoledev=ttyS0\0" \
  414. "ramdiskaddr=600000\0" \
  415. "ramdiskfile=your.ramdisk.u-boot\0" \
  416. "fdtaddr=400000\0" \
  417. "fdtfile=your.fdt.dtb\0" \
  418. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  419. "nfsroot=$serverip:$rootpath " \
  420. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  421. "console=$consoledev,$baudrate $othbootargs\0" \
  422. "ramargs=setenv bootargs root=/dev/ram rw " \
  423. "console=$consoledev,$baudrate $othbootargs\0" \
  424. #define CONFIG_NFSBOOTCOMMAND \
  425. "run nfsargs;" \
  426. "tftp $loadaddr $bootfile;" \
  427. "tftp $fdtaddr $fdtfile;" \
  428. "bootm $loadaddr - $fdtaddr"
  429. #define CONFIG_RAMBOOTCOMMAND \
  430. "run ramargs;" \
  431. "tftp $ramdiskaddr $ramdiskfile;" \
  432. "tftp $loadaddr $bootfile;" \
  433. "bootm $loadaddr $ramdiskaddr"
  434. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  435. #endif /* __CONFIG_H */