MPC8544DS.h 17 KB

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  1. /*
  2. * Copyright 2007 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8544ds board configuration file
  24. *
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /* High Level Configuration Options */
  29. #define CONFIG_BOOKE 1 /* BOOKE */
  30. #define CONFIG_E500 1 /* BOOKE e500 family */
  31. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  32. #define CONFIG_MPC8544 1
  33. #define CONFIG_MPC8544DS 1
  34. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  35. #define CONFIG_PCI1 1 /* PCI controller 1 */
  36. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  37. #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
  38. #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
  39. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  40. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  41. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  42. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  43. #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
  44. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  45. #define CONFIG_ENV_OVERWRITE
  46. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  47. #ifndef __ASSEMBLY__
  48. extern unsigned long get_board_sys_clk(unsigned long dummy);
  49. #endif
  50. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  51. /*
  52. * These can be toggled for performance analysis, otherwise use default.
  53. */
  54. #define CONFIG_L2_CACHE /* toggle L2 cache */
  55. #define CONFIG_BTB /* toggle branch predition */
  56. /*
  57. * Only possible on E500 Version 2 or newer cores.
  58. */
  59. #define CONFIG_ENABLE_36BIT_PHYS 1
  60. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  61. #define CONFIG_SYS_MEMTEST_END 0x00400000
  62. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  63. /*
  64. * Base addresses -- Note these are effective addresses where the
  65. * actual resources get mapped (not physical addresses)
  66. */
  67. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  68. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  69. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  70. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  71. #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
  72. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
  73. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
  74. #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
  75. /* DDR Setup */
  76. #define CONFIG_FSL_DDR2
  77. #undef CONFIG_FSL_DDR_INTERACTIVE
  78. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  79. #define CONFIG_DDR_SPD
  80. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  81. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  82. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  83. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  84. #define CONFIG_VERY_BIG_RAM
  85. #define CONFIG_NUM_DDR_CONTROLLERS 1
  86. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  87. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  88. /* I2C addresses of SPD EEPROMs */
  89. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  90. /* Make sure required options are set */
  91. #ifndef CONFIG_SPD_EEPROM
  92. #error ("CONFIG_SPD_EEPROM is required")
  93. #endif
  94. #undef CONFIG_CLOCKS_IN_MHZ
  95. /*
  96. * Memory map
  97. *
  98. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  99. *
  100. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  101. *
  102. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  103. *
  104. * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
  105. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  106. *
  107. * Localbus cacheable
  108. *
  109. * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
  110. * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
  111. *
  112. * Localbus non-cacheable
  113. *
  114. * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
  115. * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
  116. * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
  117. *
  118. */
  119. /*
  120. * Local Bus Definitions
  121. */
  122. #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
  123. #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
  124. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  125. #define CONFIG_SYS_BR1_PRELIM 0xfe801001
  126. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  127. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  128. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  129. #define CONFIG_SYS_FLASH_QUIET_TEST
  130. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  131. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  132. #undef CONFIG_SYS_FLASH_CHECKSUM
  133. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  134. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  135. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  136. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  137. #define CONFIG_FLASH_CFI_DRIVER
  138. #define CONFIG_SYS_FLASH_CFI
  139. #define CONFIG_SYS_FLASH_EMPTY_INFO
  140. #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
  141. #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
  142. #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
  143. #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
  144. #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
  145. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  146. #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
  147. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  148. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  149. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  150. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  151. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
  152. * register */
  153. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  154. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  155. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  156. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  157. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  158. #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
  159. #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
  160. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  161. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  162. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  163. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  164. #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
  165. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
  166. #define PIXIS_VSPEED2_TSEC1SER 0x2
  167. #define PIXIS_VSPEED2_TSEC3SER 0x1
  168. #define PIXIS_VCFGEN1_TSEC1SER 0x20
  169. #define PIXIS_VCFGEN1_TSEC3SER 0x40
  170. #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
  171. #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
  172. #define CONFIG_SYS_INIT_RAM_LOCK 1
  173. #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
  174. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  175. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  176. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  177. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  178. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  179. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  180. /* Serial Port - controlled on board with jumper J8
  181. * open - index 2
  182. * shorted - index 1
  183. */
  184. #define CONFIG_CONS_INDEX 1
  185. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  186. #define CONFIG_SYS_NS16550
  187. #define CONFIG_SYS_NS16550_SERIAL
  188. #define CONFIG_SYS_NS16550_REG_SIZE 1
  189. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  190. #define CONFIG_SYS_BAUDRATE_TABLE \
  191. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  192. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  193. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  194. /* Use the HUSH parser */
  195. #define CONFIG_SYS_HUSH_PARSER
  196. #ifdef CONFIG_SYS_HUSH_PARSER
  197. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  198. #endif
  199. /* pass open firmware flat tree */
  200. #define CONFIG_OF_LIBFDT 1
  201. #define CONFIG_OF_BOARD_SETUP 1
  202. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  203. /* I2C */
  204. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  205. #define CONFIG_HARD_I2C /* I2C with hardware support */
  206. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  207. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  208. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  209. #define CONFIG_SYS_I2C_SLAVE 0x7F
  210. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  211. #define CONFIG_SYS_I2C_OFFSET 0x3100
  212. /*
  213. * General PCI
  214. * Memory space is mapped 1-1, but I/O space must start from 0.
  215. */
  216. #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
  217. #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
  218. #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
  219. #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
  220. #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
  221. #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
  222. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
  223. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  224. #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
  225. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  226. #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
  227. #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
  228. /* controller 2, Slot 1, tgtid 1, Base address 9000 */
  229. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
  230. #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
  231. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
  232. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  233. #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
  234. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  235. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
  236. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  237. /* controller 1, Slot 2,tgtid 2, Base address a000 */
  238. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  239. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  240. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  241. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  242. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
  243. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  244. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
  245. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  246. /* controller 3, direct to uli, tgtid 3, Base address b000 */
  247. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  248. #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
  249. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
  250. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
  251. #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
  252. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  253. #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
  254. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
  255. #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
  256. #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
  257. #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
  258. #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
  259. #if defined(CONFIG_PCI)
  260. /*PCIE video card used*/
  261. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
  262. /*PCI video card used*/
  263. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
  264. /* video */
  265. #define CONFIG_VIDEO
  266. #if defined(CONFIG_VIDEO)
  267. #define CONFIG_BIOSEMU
  268. #define CONFIG_CFB_CONSOLE
  269. #define CONFIG_VIDEO_SW_CURSOR
  270. #define CONFIG_VGA_AS_SINGLE_DEVICE
  271. #define CONFIG_ATI_RADEON_FB
  272. #define CONFIG_VIDEO_LOGO
  273. /*#define CONFIG_CONSOLE_CURSOR*/
  274. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  275. #endif
  276. #define CONFIG_NET_MULTI
  277. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  278. #undef CONFIG_EEPRO100
  279. #undef CONFIG_TULIP
  280. #define CONFIG_RTL8139
  281. #ifndef CONFIG_PCI_PNP
  282. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  283. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
  284. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  285. #endif
  286. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  287. #define CONFIG_DOS_PARTITION
  288. #define CONFIG_SCSI_AHCI
  289. #ifdef CONFIG_SCSI_AHCI
  290. #define CONFIG_SATA_ULI5288
  291. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  292. #define CONFIG_SYS_SCSI_MAX_LUN 1
  293. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  294. #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
  295. #endif /* SCSCI */
  296. #endif /* CONFIG_PCI */
  297. #if defined(CONFIG_TSEC_ENET)
  298. #ifndef CONFIG_NET_MULTI
  299. #define CONFIG_NET_MULTI 1
  300. #endif
  301. #define CONFIG_MII 1 /* MII PHY management */
  302. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  303. #define CONFIG_TSEC1 1
  304. #define CONFIG_TSEC1_NAME "eTSEC1"
  305. #define CONFIG_TSEC3 1
  306. #define CONFIG_TSEC3_NAME "eTSEC3"
  307. #define CONFIG_PIXIS_SGMII_CMD
  308. #define CONFIG_FSL_SGMII_RISER 1
  309. #define SGMII_RISER_PHY_OFFSET 0x1c
  310. #define TSEC1_PHY_ADDR 0
  311. #define TSEC3_PHY_ADDR 1
  312. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  313. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  314. #define TSEC1_PHYIDX 0
  315. #define TSEC3_PHYIDX 0
  316. #define CONFIG_ETHPRIME "eTSEC1"
  317. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  318. #endif /* CONFIG_TSEC_ENET */
  319. /*
  320. * Environment
  321. */
  322. #define CONFIG_ENV_IS_IN_FLASH 1
  323. #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
  324. #define CONFIG_ENV_ADDR 0xfff80000
  325. #else
  326. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
  327. #endif
  328. #define CONFIG_ENV_SIZE 0x2000
  329. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
  330. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  331. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  332. /*
  333. * BOOTP options
  334. */
  335. #define CONFIG_BOOTP_BOOTFILESIZE
  336. #define CONFIG_BOOTP_BOOTPATH
  337. #define CONFIG_BOOTP_GATEWAY
  338. #define CONFIG_BOOTP_HOSTNAME
  339. /*
  340. * Command line configuration.
  341. */
  342. #include <config_cmd_default.h>
  343. #define CONFIG_CMD_PING
  344. #define CONFIG_CMD_I2C
  345. #define CONFIG_CMD_MII
  346. #define CONFIG_CMD_ELF
  347. #define CONFIG_CMD_IRQ
  348. #define CONFIG_CMD_SETEXPR
  349. #if defined(CONFIG_PCI)
  350. #define CONFIG_CMD_PCI
  351. #define CONFIG_CMD_NET
  352. #define CONFIG_CMD_SCSI
  353. #define CONFIG_CMD_EXT2
  354. #endif
  355. #undef CONFIG_WATCHDOG /* watchdog disabled */
  356. /*
  357. * Miscellaneous configurable options
  358. */
  359. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  360. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  361. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  362. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  363. #if defined(CONFIG_CMD_KGDB)
  364. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  365. #else
  366. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  367. #endif
  368. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  369. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  370. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  371. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  372. /*
  373. * For booting Linux, the board info and command line data
  374. * have to be in the first 16 MB of memory, since this is
  375. * the maximum mapped by the Linux kernel during initialization.
  376. */
  377. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  378. /*
  379. * Internal Definitions
  380. *
  381. * Boot Flags
  382. */
  383. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  384. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  385. #if defined(CONFIG_CMD_KGDB)
  386. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  387. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  388. #endif
  389. /*
  390. * Environment Configuration
  391. */
  392. /* The mac addresses for all ethernet interface */
  393. #if defined(CONFIG_TSEC_ENET)
  394. #define CONFIG_HAS_ETH0
  395. #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
  396. #define CONFIG_HAS_ETH1
  397. #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
  398. #endif
  399. #define CONFIG_IPADDR 192.168.1.251
  400. #define CONFIG_HOSTNAME 8544ds_unknown
  401. #define CONFIG_ROOTPATH /nfs/mpc85xx
  402. #define CONFIG_BOOTFILE 8544ds/uImage.uboot
  403. #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
  404. #define CONFIG_SERVERIP 192.168.1.1
  405. #define CONFIG_GATEWAYIP 192.168.1.1
  406. #define CONFIG_NETMASK 255.255.0.0
  407. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  408. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  409. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  410. #define CONFIG_BAUDRATE 115200
  411. #define CONFIG_EXTRA_ENV_SETTINGS \
  412. "netdev=eth0\0" \
  413. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  414. "tftpflash=tftpboot $loadaddr $uboot; " \
  415. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  416. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  417. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  418. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  419. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  420. "consoledev=ttyS0\0" \
  421. "ramdiskaddr=2000000\0" \
  422. "ramdiskfile=8544ds/ramdisk.uboot\0" \
  423. "fdtaddr=c00000\0" \
  424. "fdtfile=8544ds/mpc8544ds.dtb\0" \
  425. "bdev=sda3\0"
  426. #define CONFIG_NFSBOOTCOMMAND \
  427. "setenv bootargs root=/dev/nfs rw " \
  428. "nfsroot=$serverip:$rootpath " \
  429. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  430. "console=$consoledev,$baudrate $othbootargs;" \
  431. "tftp $loadaddr $bootfile;" \
  432. "tftp $fdtaddr $fdtfile;" \
  433. "bootm $loadaddr - $fdtaddr"
  434. #define CONFIG_RAMBOOTCOMMAND \
  435. "setenv bootargs root=/dev/ram rw " \
  436. "console=$consoledev,$baudrate $othbootargs;" \
  437. "tftp $ramdiskaddr $ramdiskfile;" \
  438. "tftp $loadaddr $bootfile;" \
  439. "tftp $fdtaddr $fdtfile;" \
  440. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  441. #define CONFIG_BOOTCOMMAND \
  442. "setenv bootargs root=/dev/$bdev rw " \
  443. "console=$consoledev,$baudrate $othbootargs;" \
  444. "tftp $loadaddr $bootfile;" \
  445. "tftp $fdtaddr $fdtfile;" \
  446. "bootm $loadaddr - $fdtaddr"
  447. #endif /* __CONFIG_H */