MPC8541CDS.h 16 KB

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  1. /*
  2. * Copyright 2004 Freescale Semiconductor.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8541cds board configuration file
  24. *
  25. * Please refer to doc/README.mpc85xxcds for more info.
  26. *
  27. */
  28. #ifndef __CONFIG_H
  29. #define __CONFIG_H
  30. /* High Level Configuration Options */
  31. #define CONFIG_BOOKE 1 /* BOOKE */
  32. #define CONFIG_E500 1 /* BOOKE e500 family */
  33. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
  34. #define CONFIG_CPM2 1 /* has CPM2 */
  35. #define CONFIG_MPC8541 1 /* MPC8541 specific */
  36. #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
  37. #define CONFIG_PCI
  38. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  39. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  40. #define CONFIG_ENV_OVERWRITE
  41. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  42. #define CONFIG_FSL_VIA
  43. #ifndef __ASSEMBLY__
  44. extern unsigned long get_clock_freq(void);
  45. #endif
  46. #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  47. /*
  48. * These can be toggled for performance analysis, otherwise use default.
  49. */
  50. #define CONFIG_L2_CACHE /* toggle L2 cache */
  51. #define CONFIG_BTB /* toggle branch predition */
  52. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  53. #define CONFIG_SYS_MEMTEST_END 0x00400000
  54. /*
  55. * Base addresses -- Note these are effective addresses where the
  56. * actual resources get mapped (not physical addresses)
  57. */
  58. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  59. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  60. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  61. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  62. /* DDR Setup */
  63. #define CONFIG_FSL_DDR1
  64. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  65. #define CONFIG_DDR_SPD
  66. #undef CONFIG_FSL_DDR_INTERACTIVE
  67. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  68. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  69. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  70. #define CONFIG_NUM_DDR_CONTROLLERS 1
  71. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  72. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  73. /* I2C addresses of SPD EEPROMs */
  74. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  75. /*
  76. * Make sure required options are set
  77. */
  78. #ifndef CONFIG_SPD_EEPROM
  79. #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  80. #endif
  81. #undef CONFIG_CLOCKS_IN_MHZ
  82. /*
  83. * Local Bus Definitions
  84. */
  85. /*
  86. * FLASH on the Local Bus
  87. * Two banks, 8M each, using the CFI driver.
  88. * Boot from BR0/OR0 bank at 0xff00_0000
  89. * Alternate BR1/OR1 bank at 0xff80_0000
  90. *
  91. * BR0, BR1:
  92. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  93. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  94. * Port Size = 16 bits = BRx[19:20] = 10
  95. * Use GPCM = BRx[24:26] = 000
  96. * Valid = BRx[31] = 1
  97. *
  98. * 0 4 8 12 16 20 24 28
  99. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  100. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  101. *
  102. * OR0, OR1:
  103. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  104. * Reserved ORx[17:18] = 11, confusion here?
  105. * CSNT = ORx[20] = 1
  106. * ACS = half cycle delay = ORx[21:22] = 11
  107. * SCY = 6 = ORx[24:27] = 0110
  108. * TRLX = use relaxed timing = ORx[29] = 1
  109. * EAD = use external address latch delay = OR[31] = 1
  110. *
  111. * 0 4 8 12 16 20 24 28
  112. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  113. */
  114. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
  115. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  116. #define CONFIG_SYS_BR1_PRELIM 0xff001001
  117. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  118. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  119. #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
  120. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  121. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  122. #undef CONFIG_SYS_FLASH_CHECKSUM
  123. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  124. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  125. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  126. #define CONFIG_FLASH_CFI_DRIVER
  127. #define CONFIG_SYS_FLASH_CFI
  128. #define CONFIG_SYS_FLASH_EMPTY_INFO
  129. /*
  130. * SDRAM on the Local Bus
  131. */
  132. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  133. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  134. /*
  135. * Base Register 2 and Option Register 2 configure SDRAM.
  136. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  137. *
  138. * For BR2, need:
  139. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  140. * port-size = 32-bits = BR2[19:20] = 11
  141. * no parity checking = BR2[21:22] = 00
  142. * SDRAM for MSEL = BR2[24:26] = 011
  143. * Valid = BR[31] = 1
  144. *
  145. * 0 4 8 12 16 20 24 28
  146. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  147. *
  148. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  149. * FIXME: the top 17 bits of BR2.
  150. */
  151. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  152. /*
  153. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  154. *
  155. * For OR2, need:
  156. * 64MB mask for AM, OR2[0:7] = 1111 1100
  157. * XAM, OR2[17:18] = 11
  158. * 9 columns OR2[19-21] = 010
  159. * 13 rows OR2[23-25] = 100
  160. * EAD set for extra time OR[31] = 1
  161. *
  162. * 0 4 8 12 16 20 24 28
  163. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  164. */
  165. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  166. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  167. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  168. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  169. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  170. /*
  171. * Common settings for all Local Bus SDRAM commands.
  172. * At run time, either BSMA1516 (for CPU 1.1)
  173. * or BSMA1617 (for CPU 1.0) (old)
  174. * is OR'ed in too.
  175. */
  176. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  177. | LSDMR_PRETOACT7 \
  178. | LSDMR_ACTTORW7 \
  179. | LSDMR_BL8 \
  180. | LSDMR_WRC4 \
  181. | LSDMR_CL3 \
  182. | LSDMR_RFEN \
  183. )
  184. /*
  185. * The CADMUS registers are connected to CS3 on CDS.
  186. * The new memory map places CADMUS at 0xf8000000.
  187. *
  188. * For BR3, need:
  189. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  190. * port-size = 8-bits = BR[19:20] = 01
  191. * no parity checking = BR[21:22] = 00
  192. * GPMC for MSEL = BR[24:26] = 000
  193. * Valid = BR[31] = 1
  194. *
  195. * 0 4 8 12 16 20 24 28
  196. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  197. *
  198. * For OR3, need:
  199. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  200. * disable buffer ctrl OR[19] = 0
  201. * CSNT OR[20] = 1
  202. * ACS OR[21:22] = 11
  203. * XACS OR[23] = 1
  204. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  205. * SETA OR[28] = 0
  206. * TRLX OR[29] = 1
  207. * EHTR OR[30] = 1
  208. * EAD extra time OR[31] = 1
  209. *
  210. * 0 4 8 12 16 20 24 28
  211. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  212. */
  213. #define CONFIG_FSL_CADMUS
  214. #define CADMUS_BASE_ADDR 0xf8000000
  215. #define CONFIG_SYS_BR3_PRELIM 0xf8000801
  216. #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
  217. #define CONFIG_SYS_INIT_RAM_LOCK 1
  218. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  219. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
  220. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  221. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  222. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  223. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  224. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  225. /* Serial Port */
  226. #define CONFIG_CONS_INDEX 2
  227. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  228. #define CONFIG_SYS_NS16550
  229. #define CONFIG_SYS_NS16550_SERIAL
  230. #define CONFIG_SYS_NS16550_REG_SIZE 1
  231. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  232. #define CONFIG_SYS_BAUDRATE_TABLE \
  233. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  234. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  235. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  236. /* Use the HUSH parser */
  237. #define CONFIG_SYS_HUSH_PARSER
  238. #ifdef CONFIG_SYS_HUSH_PARSER
  239. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  240. #endif
  241. /* pass open firmware flat tree */
  242. #define CONFIG_OF_LIBFDT 1
  243. #define CONFIG_OF_BOARD_SETUP 1
  244. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  245. /*
  246. * I2C
  247. */
  248. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  249. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  250. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  251. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  252. #define CONFIG_SYS_I2C_SLAVE 0x7F
  253. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  254. #define CONFIG_SYS_I2C_OFFSET 0x3000
  255. /* EEPROM */
  256. #define CONFIG_ID_EEPROM
  257. #define CONFIG_SYS_I2C_EEPROM_CCID
  258. #define CONFIG_SYS_ID_EEPROM
  259. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  260. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  261. /*
  262. * General PCI
  263. * Memory space is mapped 1-1, but I/O space must start from 0.
  264. */
  265. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  266. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  267. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  268. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  269. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  270. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  271. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  272. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  273. #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  274. #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  275. #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
  276. #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
  277. #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
  278. #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
  279. #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
  280. #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
  281. #ifdef CONFIG_LEGACY
  282. #define BRIDGE_ID 17
  283. #define VIA_ID 2
  284. #else
  285. #define BRIDGE_ID 28
  286. #define VIA_ID 4
  287. #endif
  288. #if defined(CONFIG_PCI)
  289. #define CONFIG_MPC85XX_PCI2
  290. #define CONFIG_NET_MULTI
  291. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  292. #undef CONFIG_EEPRO100
  293. #undef CONFIG_TULIP
  294. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  295. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  296. #endif /* CONFIG_PCI */
  297. #if defined(CONFIG_TSEC_ENET)
  298. #ifndef CONFIG_NET_MULTI
  299. #define CONFIG_NET_MULTI 1
  300. #endif
  301. #define CONFIG_MII 1 /* MII PHY management */
  302. #define CONFIG_TSEC1 1
  303. #define CONFIG_TSEC1_NAME "TSEC0"
  304. #define CONFIG_TSEC2 1
  305. #define CONFIG_TSEC2_NAME "TSEC1"
  306. #define TSEC1_PHY_ADDR 0
  307. #define TSEC2_PHY_ADDR 1
  308. #define TSEC1_PHYIDX 0
  309. #define TSEC2_PHYIDX 0
  310. #define TSEC1_FLAGS TSEC_GIGABIT
  311. #define TSEC2_FLAGS TSEC_GIGABIT
  312. /* Options are: TSEC[0-1] */
  313. #define CONFIG_ETHPRIME "TSEC0"
  314. #endif /* CONFIG_TSEC_ENET */
  315. /*
  316. * Environment
  317. */
  318. #define CONFIG_ENV_IS_IN_FLASH 1
  319. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  320. #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  321. #define CONFIG_ENV_SIZE 0x2000
  322. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  323. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  324. /*
  325. * BOOTP options
  326. */
  327. #define CONFIG_BOOTP_BOOTFILESIZE
  328. #define CONFIG_BOOTP_BOOTPATH
  329. #define CONFIG_BOOTP_GATEWAY
  330. #define CONFIG_BOOTP_HOSTNAME
  331. /*
  332. * Command line configuration.
  333. */
  334. #include <config_cmd_default.h>
  335. #define CONFIG_CMD_PING
  336. #define CONFIG_CMD_I2C
  337. #define CONFIG_CMD_MII
  338. #define CONFIG_CMD_ELF
  339. #define CONFIG_CMD_IRQ
  340. #define CONFIG_CMD_SETEXPR
  341. #if defined(CONFIG_PCI)
  342. #define CONFIG_CMD_PCI
  343. #endif
  344. #undef CONFIG_WATCHDOG /* watchdog disabled */
  345. /*
  346. * Miscellaneous configurable options
  347. */
  348. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  349. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  350. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  351. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  352. #if defined(CONFIG_CMD_KGDB)
  353. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  354. #else
  355. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  356. #endif
  357. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  358. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  359. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  360. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  361. /*
  362. * For booting Linux, the board info and command line data
  363. * have to be in the first 16 MB of memory, since this is
  364. * the maximum mapped by the Linux kernel during initialization.
  365. */
  366. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  367. /*
  368. * Internal Definitions
  369. *
  370. * Boot Flags
  371. */
  372. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  373. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  374. #if defined(CONFIG_CMD_KGDB)
  375. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  376. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  377. #endif
  378. /*
  379. * Environment Configuration
  380. */
  381. /* The mac addresses for all ethernet interface */
  382. #if defined(CONFIG_TSEC_ENET)
  383. #define CONFIG_HAS_ETH0
  384. #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  385. #define CONFIG_HAS_ETH1
  386. #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  387. #define CONFIG_HAS_ETH2
  388. #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  389. #endif
  390. #define CONFIG_IPADDR 192.168.1.253
  391. #define CONFIG_HOSTNAME unknown
  392. #define CONFIG_ROOTPATH /nfsroot
  393. #define CONFIG_BOOTFILE your.uImage
  394. #define CONFIG_SERVERIP 192.168.1.1
  395. #define CONFIG_GATEWAYIP 192.168.1.1
  396. #define CONFIG_NETMASK 255.255.255.0
  397. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  398. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  399. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  400. #define CONFIG_BAUDRATE 115200
  401. #define CONFIG_EXTRA_ENV_SETTINGS \
  402. "netdev=eth0\0" \
  403. "consoledev=ttyS1\0" \
  404. "ramdiskaddr=600000\0" \
  405. "ramdiskfile=your.ramdisk.u-boot\0" \
  406. "fdtaddr=400000\0" \
  407. "fdtfile=your.fdt.dtb\0"
  408. #define CONFIG_NFSBOOTCOMMAND \
  409. "setenv bootargs root=/dev/nfs rw " \
  410. "nfsroot=$serverip:$rootpath " \
  411. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  412. "console=$consoledev,$baudrate $othbootargs;" \
  413. "tftp $loadaddr $bootfile;" \
  414. "tftp $fdtaddr $fdtfile;" \
  415. "bootm $loadaddr - $fdtaddr"
  416. #define CONFIG_RAMBOOTCOMMAND \
  417. "setenv bootargs root=/dev/ram rw " \
  418. "console=$consoledev,$baudrate $othbootargs;" \
  419. "tftp $ramdiskaddr $ramdiskfile;" \
  420. "tftp $loadaddr $bootfile;" \
  421. "bootm $loadaddr $ramdiskaddr"
  422. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  423. #endif /* __CONFIG_H */