MPC837XERDB.h 21 KB

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  1. /*
  2. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  3. * Kevin Lam <kevin.lam@freescale.com>
  4. * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #ifndef __CONFIG_H
  22. #define __CONFIG_H
  23. /*
  24. * High Level Configuration Options
  25. */
  26. #define CONFIG_E300 1 /* E300 family */
  27. #define CONFIG_MPC83xx 1 /* MPC83xx family */
  28. #define CONFIG_MPC837x 1 /* MPC837x CPU specific */
  29. #define CONFIG_MPC837XERDB 1
  30. #define CONFIG_PCI 1
  31. #define CONFIG_BOARD_EARLY_INIT_F
  32. #define CONFIG_MISC_INIT_R
  33. #define CONFIG_HWCONFIG
  34. /*
  35. * On-board devices
  36. */
  37. #define CONFIG_TSEC_ENET /* TSEC Ethernet support */
  38. #define CONFIG_VSC7385_ENET
  39. /*
  40. * System Clock Setup
  41. */
  42. #ifdef CONFIG_PCISLAVE
  43. #define CONFIG_83XX_PCICLK 66666667 /* in HZ */
  44. #else
  45. #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
  46. #define CONFIG_PCIE
  47. #endif
  48. #ifndef CONFIG_SYS_CLK_FREQ
  49. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  50. #endif
  51. /*
  52. * Hardware Reset Configuration Word
  53. */
  54. #define CONFIG_SYS_HRCW_LOW (\
  55. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  56. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  57. HRCWL_SVCOD_DIV_2 |\
  58. HRCWL_CSB_TO_CLKIN_5X1 |\
  59. HRCWL_CORE_TO_CSB_2X1)
  60. #ifdef CONFIG_PCISLAVE
  61. #define CONFIG_SYS_HRCW_HIGH (\
  62. HRCWH_PCI_AGENT |\
  63. HRCWH_PCI1_ARBITER_DISABLE |\
  64. HRCWH_CORE_ENABLE |\
  65. HRCWH_FROM_0XFFF00100 |\
  66. HRCWH_BOOTSEQ_DISABLE |\
  67. HRCWH_SW_WATCHDOG_DISABLE |\
  68. HRCWH_ROM_LOC_LOCAL_16BIT |\
  69. HRCWH_RL_EXT_LEGACY |\
  70. HRCWH_TSEC1M_IN_RGMII |\
  71. HRCWH_TSEC2M_IN_RGMII |\
  72. HRCWH_BIG_ENDIAN |\
  73. HRCWH_LDP_CLEAR)
  74. #else
  75. #define CONFIG_SYS_HRCW_HIGH (\
  76. HRCWH_PCI_HOST |\
  77. HRCWH_PCI1_ARBITER_ENABLE |\
  78. HRCWH_CORE_ENABLE |\
  79. HRCWH_FROM_0X00000100 |\
  80. HRCWH_BOOTSEQ_DISABLE |\
  81. HRCWH_SW_WATCHDOG_DISABLE |\
  82. HRCWH_ROM_LOC_LOCAL_16BIT |\
  83. HRCWH_RL_EXT_LEGACY |\
  84. HRCWH_TSEC1M_IN_RGMII |\
  85. HRCWH_TSEC2M_IN_RGMII |\
  86. HRCWH_BIG_ENDIAN |\
  87. HRCWH_LDP_CLEAR)
  88. #endif
  89. /* System performance - define the value i.e. CONFIG_SYS_XXX
  90. */
  91. /* Arbiter Configuration Register */
  92. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  93. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  94. /* System Priority Control Regsiter */
  95. #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
  96. /* System Clock Configuration Register */
  97. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
  98. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
  99. #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
  100. /*
  101. * System IO Config
  102. */
  103. #define CONFIG_SYS_SICRH 0x08200000
  104. #define CONFIG_SYS_SICRL 0x00000000
  105. /*
  106. * Output Buffer Impedance
  107. */
  108. #define CONFIG_SYS_OBIR 0x30100000
  109. /*
  110. * IMMR new address
  111. */
  112. #define CONFIG_SYS_IMMR 0xE0000000
  113. /*
  114. * Device configurations
  115. */
  116. /* Vitesse 7385 */
  117. #ifdef CONFIG_VSC7385_ENET
  118. #define CONFIG_TSEC2
  119. /* The flash address and size of the VSC7385 firmware image */
  120. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  121. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  122. #endif
  123. /*
  124. * DDR Setup
  125. */
  126. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
  127. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  128. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  129. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
  130. #define CONFIG_SYS_83XX_DDR_USES_CS0
  131. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  132. #undef CONFIG_DDR_ECC /* support DDR ECC function */
  133. #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
  134. #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  135. /*
  136. * Manually set up DDR parameters
  137. */
  138. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  139. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
  140. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
  141. | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  142. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  143. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  144. | (0 << TIMING_CFG0_WRT_SHIFT) \
  145. | (0 << TIMING_CFG0_RRT_SHIFT) \
  146. | (0 << TIMING_CFG0_WWT_SHIFT) \
  147. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  148. | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  149. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  150. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  151. /* 0x00220802 */
  152. /* 0x00260802 */ /* DDR400 */
  153. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  154. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  155. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  156. | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  157. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  158. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  159. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  160. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  161. /* 0x3935d322 */
  162. /* 0x3937d322 */
  163. #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
  164. #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
  165. | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  166. /* 0x06090100 */
  167. #if defined(CONFIG_DDR_2T_TIMING)
  168. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  169. | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
  170. | SDRAM_CFG_2T_EN \
  171. | SDRAM_CFG_DBW_32)
  172. #else
  173. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  174. | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
  175. /* 0x43000000 */
  176. #endif
  177. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
  178. #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
  179. | (0x0442 << SDRAM_MODE_SD_SHIFT))
  180. /* 0x04400442 */ /* DDR400 */
  181. #define CONFIG_SYS_DDR_MODE2 0x00000000
  182. /*
  183. * Memory test
  184. */
  185. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  186. #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
  187. #define CONFIG_SYS_MEMTEST_END 0x0ef70010
  188. /*
  189. * The reserved memory
  190. */
  191. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  192. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  193. #define CONFIG_SYS_RAMBOOT
  194. #else
  195. #undef CONFIG_SYS_RAMBOOT
  196. #endif
  197. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  198. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  199. /*
  200. * Initial RAM Base Address Setup
  201. */
  202. #define CONFIG_SYS_INIT_RAM_LOCK 1
  203. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  204. #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
  205. #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  206. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  207. /*
  208. * Local Bus Configuration & Clock Setup
  209. */
  210. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  211. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
  212. #define CONFIG_SYS_LBC_LBCR 0x00000000
  213. /*
  214. * FLASH on the Local Bus
  215. */
  216. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  217. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  218. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  219. #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
  220. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  221. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  222. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
  223. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
  224. #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
  225. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
  226. (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
  227. BR_V) /* valid */
  228. #define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
  229. | OR_GPCM_XACS \
  230. | OR_GPCM_SCY_9 \
  231. | OR_GPCM_EHTR \
  232. | OR_GPCM_EAD)
  233. /* 0xFF806FF7 TODO SLOW 8 MB flash size */
  234. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  235. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  236. #undef CONFIG_SYS_FLASH_CHECKSUM
  237. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  238. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  239. /*
  240. * NAND Flash on the Local Bus
  241. */
  242. #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
  243. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \
  244. (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
  245. BR_PS_8 | /* Port Size = 8 bit */ \
  246. BR_MS_FCM | /* MSEL = FCM */ \
  247. BR_V) /* valid */
  248. #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \
  249. OR_FCM_CSCT | \
  250. OR_FCM_CST | \
  251. OR_FCM_CHT | \
  252. OR_FCM_SCY_1 | \
  253. OR_FCM_TRLX | \
  254. OR_FCM_EHTR)
  255. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  256. #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
  257. /* Vitesse 7385 */
  258. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  259. #ifdef CONFIG_VSC7385_ENET
  260. #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
  261. #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
  262. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */
  263. #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
  264. #endif
  265. /*
  266. * Serial Port
  267. */
  268. #define CONFIG_CONS_INDEX 1
  269. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  270. #define CONFIG_SYS_NS16550
  271. #define CONFIG_SYS_NS16550_SERIAL
  272. #define CONFIG_SYS_NS16550_REG_SIZE 1
  273. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  274. #define CONFIG_SYS_BAUDRATE_TABLE \
  275. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  276. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  277. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  278. /* SERDES */
  279. #define CONFIG_FSL_SERDES
  280. #define CONFIG_FSL_SERDES1 0xe3000
  281. #define CONFIG_FSL_SERDES2 0xe3100
  282. /* Use the HUSH parser */
  283. #define CONFIG_SYS_HUSH_PARSER
  284. #ifdef CONFIG_SYS_HUSH_PARSER
  285. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  286. #endif
  287. /* Pass open firmware flat tree */
  288. #define CONFIG_OF_LIBFDT 1
  289. #define CONFIG_OF_BOARD_SETUP 1
  290. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  291. /* I2C */
  292. #define CONFIG_HARD_I2C /* I2C with hardware support */
  293. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  294. #define CONFIG_FSL_I2C
  295. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  296. #define CONFIG_SYS_I2C_SLAVE 0x7F
  297. #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
  298. #define CONFIG_SYS_I2C_OFFSET 0x3000
  299. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  300. /*
  301. * Config on-board RTC
  302. */
  303. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  304. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  305. /*
  306. * General PCI
  307. * Addresses are mapped 1-1.
  308. */
  309. #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
  310. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  311. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  312. #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
  313. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  314. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  315. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  316. #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
  317. #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
  318. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  319. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  320. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  321. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  322. #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
  323. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
  324. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
  325. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
  326. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  327. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  328. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
  329. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  330. #define CONFIG_SYS_PCIE2_BASE 0xC0000000
  331. #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
  332. #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
  333. #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
  334. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
  335. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
  336. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  337. #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
  338. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
  339. #ifdef CONFIG_PCI
  340. #define CONFIG_NET_MULTI
  341. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  342. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  343. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  344. #endif /* CONFIG_PCI */
  345. /*
  346. * TSEC
  347. */
  348. #ifdef CONFIG_TSEC_ENET
  349. #define CONFIG_NET_MULTI
  350. #define CONFIG_GMII /* MII PHY management */
  351. #define CONFIG_TSEC1
  352. #ifdef CONFIG_TSEC1
  353. #define CONFIG_HAS_ETH0
  354. #define CONFIG_TSEC1_NAME "TSEC0"
  355. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  356. #define TSEC1_PHY_ADDR 2
  357. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  358. #define TSEC1_PHYIDX 0
  359. #endif
  360. #ifdef CONFIG_TSEC2
  361. #define CONFIG_HAS_ETH1
  362. #define CONFIG_TSEC2_NAME "TSEC1"
  363. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  364. #define TSEC2_PHY_ADDR 0x1c
  365. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  366. #define TSEC2_PHYIDX 0
  367. #endif
  368. /* Options are: TSEC[0-1] */
  369. #define CONFIG_ETHPRIME "TSEC0"
  370. #endif
  371. /*
  372. * SATA
  373. */
  374. #define CONFIG_LIBATA
  375. #define CONFIG_FSL_SATA
  376. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  377. #define CONFIG_SATA1
  378. #define CONFIG_SYS_SATA1_OFFSET 0x18000
  379. #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
  380. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  381. #define CONFIG_SATA2
  382. #define CONFIG_SYS_SATA2_OFFSET 0x19000
  383. #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
  384. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  385. #ifdef CONFIG_FSL_SATA
  386. #define CONFIG_LBA48
  387. #define CONFIG_CMD_SATA
  388. #define CONFIG_DOS_PARTITION
  389. #define CONFIG_CMD_EXT2
  390. #endif
  391. /*
  392. * Environment
  393. */
  394. #ifndef CONFIG_SYS_RAMBOOT
  395. #define CONFIG_ENV_IS_IN_FLASH 1
  396. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
  397. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
  398. #define CONFIG_ENV_SIZE 0x4000
  399. #else
  400. #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
  401. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  402. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
  403. #define CONFIG_ENV_SIZE 0x2000
  404. #endif
  405. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  406. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  407. /*
  408. * BOOTP options
  409. */
  410. #define CONFIG_BOOTP_BOOTFILESIZE
  411. #define CONFIG_BOOTP_BOOTPATH
  412. #define CONFIG_BOOTP_GATEWAY
  413. #define CONFIG_BOOTP_HOSTNAME
  414. /*
  415. * Command line configuration.
  416. */
  417. #include <config_cmd_default.h>
  418. #define CONFIG_CMD_PING
  419. #define CONFIG_CMD_I2C
  420. #define CONFIG_CMD_MII
  421. #define CONFIG_CMD_DATE
  422. #if defined(CONFIG_PCI)
  423. #define CONFIG_CMD_PCI
  424. #endif
  425. #if defined(CONFIG_SYS_RAMBOOT)
  426. #undef CONFIG_CMD_SAVEENV
  427. #undef CONFIG_CMD_LOADS
  428. #endif
  429. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  430. #undef CONFIG_WATCHDOG /* watchdog disabled */
  431. #define CONFIG_MMC 1
  432. #ifdef CONFIG_MMC
  433. #define CONFIG_FSL_ESDHC
  434. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  435. #define CONFIG_CMD_MMC
  436. #define CONFIG_GENERIC_MMC
  437. #define CONFIG_CMD_EXT2
  438. #define CONFIG_CMD_FAT
  439. #define CONFIG_DOS_PARTITION
  440. #endif
  441. /*
  442. * Miscellaneous configurable options
  443. */
  444. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  445. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  446. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  447. #if defined(CONFIG_CMD_KGDB)
  448. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  449. #else
  450. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  451. #endif
  452. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  453. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  454. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  455. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  456. /*
  457. * For booting Linux, the board info and command line data
  458. * have to be in the first 8 MB of memory, since this is
  459. * the maximum mapped by the Linux kernel during initialization.
  460. */
  461. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  462. /*
  463. * Core HID Setup
  464. */
  465. #define CONFIG_SYS_HID0_INIT 0x000000000
  466. #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
  467. #define CONFIG_SYS_HID2 HID2_HBE
  468. /*
  469. * MMU Setup
  470. */
  471. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  472. /* DDR: cache cacheable */
  473. #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
  474. #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
  475. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
  476. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
  477. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  478. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  479. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
  480. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
  481. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  482. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  483. /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
  484. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
  485. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  486. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
  487. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  488. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  489. /* L2 Switch: cache-inhibit and guarded */
  490. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \
  491. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  492. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
  493. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  494. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  495. /* FLASH: icache cacheable, but dcache-inhibit and guarded */
  496. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  497. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
  498. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
  499. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  500. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  501. /* Stack in dcache: cacheable, no memory coherence */
  502. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
  503. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  504. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  505. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  506. #ifdef CONFIG_PCI
  507. /* PCI MEM space: cacheable */
  508. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
  509. #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
  510. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  511. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  512. /* PCI MMIO space: cache-inhibit and guarded */
  513. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
  514. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  515. #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
  516. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  517. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  518. #else
  519. #define CONFIG_SYS_IBAT6L (0)
  520. #define CONFIG_SYS_IBAT6U (0)
  521. #define CONFIG_SYS_IBAT7L (0)
  522. #define CONFIG_SYS_IBAT7U (0)
  523. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  524. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  525. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  526. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  527. #endif
  528. /*
  529. * Internal Definitions
  530. *
  531. * Boot Flags
  532. */
  533. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  534. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  535. #if defined(CONFIG_CMD_KGDB)
  536. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  537. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  538. #endif
  539. /*
  540. * Environment Configuration
  541. */
  542. #define CONFIG_ENV_OVERWRITE
  543. #ifdef CONFIG_HAS_ETH0
  544. #define CONFIG_ETHADDR 00:04:9f:ef:04:01
  545. #endif
  546. #ifdef CONFIG_HAS_ETH1
  547. #define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
  548. #endif
  549. #define CONFIG_HAS_FSL_DR_USB
  550. #define CONFIG_IPADDR 10.0.0.2
  551. #define CONFIG_SERVERIP 10.0.0.1
  552. #define CONFIG_GATEWAYIP 10.0.0.1
  553. #define CONFIG_NETMASK 255.0.0.0
  554. #define CONFIG_NETDEV eth1
  555. #define CONFIG_HOSTNAME mpc837x_rdb
  556. #define CONFIG_ROOTPATH /nfsroot
  557. #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
  558. #define CONFIG_BOOTFILE uImage
  559. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  560. #define CONFIG_FDTFILE mpc8379_rdb.dtb
  561. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  562. #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
  563. #define CONFIG_BAUDRATE 115200
  564. #define XMK_STR(x) #x
  565. #define MK_STR(x) XMK_STR(x)
  566. #define CONFIG_EXTRA_ENV_SETTINGS \
  567. "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
  568. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  569. "tftpflash=tftp $loadaddr $uboot;" \
  570. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  571. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  572. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  573. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  574. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  575. "fdtaddr=780000\0" \
  576. "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
  577. "ramdiskaddr=1000000\0" \
  578. "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
  579. "console=ttyS0\0" \
  580. "setbootargs=setenv bootargs " \
  581. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  582. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  583. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  584. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  585. #define CONFIG_NFSBOOTCOMMAND \
  586. "setenv rootdev /dev/nfs;" \
  587. "run setbootargs;" \
  588. "run setipargs;" \
  589. "tftp $loadaddr $bootfile;" \
  590. "tftp $fdtaddr $fdtfile;" \
  591. "bootm $loadaddr - $fdtaddr"
  592. #define CONFIG_RAMBOOTCOMMAND \
  593. "setenv rootdev /dev/ram;" \
  594. "run setbootargs;" \
  595. "tftp $ramdiskaddr $ramdiskfile;" \
  596. "tftp $loadaddr $bootfile;" \
  597. "tftp $fdtaddr $fdtfile;" \
  598. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  599. #undef MK_STR
  600. #undef XMK_STR
  601. #endif /* __CONFIG_H */