MPC8313ERDB.h 20 KB

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  1. /*
  2. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8313epb board configuration file
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. /*
  28. * High Level Configuration Options
  29. */
  30. #define CONFIG_E300 1
  31. #define CONFIG_MPC83xx 1
  32. #define CONFIG_MPC831x 1
  33. #define CONFIG_MPC8313 1
  34. #define CONFIG_MPC8313ERDB 1
  35. #define CONFIG_PCI
  36. #define CONFIG_MISC_INIT_R
  37. /*
  38. * On-board devices
  39. *
  40. * TSEC1 is VSC switch
  41. * TSEC2 is SoC TSEC
  42. */
  43. #define CONFIG_VSC7385_ENET
  44. #define CONFIG_TSEC2
  45. #ifdef CONFIG_SYS_66MHZ
  46. #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
  47. #elif defined(CONFIG_SYS_33MHZ)
  48. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  49. #else
  50. #error Unknown oscillator frequency.
  51. #endif
  52. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  53. #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  54. #define CONFIG_SYS_IMMR 0xE0000000
  55. #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  56. #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
  57. #endif
  58. #define CONFIG_SYS_MEMTEST_START 0x00001000
  59. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  60. /* Early revs of this board will lock up hard when attempting
  61. * to access the PMC registers, unless a JTAG debugger is
  62. * connected, or some resistor modifications are made.
  63. */
  64. #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  65. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  66. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  67. /*
  68. * Device configurations
  69. */
  70. /* Vitesse 7385 */
  71. #ifdef CONFIG_VSC7385_ENET
  72. #define CONFIG_TSEC1
  73. /* The flash address and size of the VSC7385 firmware image */
  74. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  75. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  76. #endif
  77. /*
  78. * DDR Setup
  79. */
  80. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  81. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  82. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  83. /*
  84. * Manually set up DDR parameters, as this board does not
  85. * seem to have the SPD connected to I2C.
  86. */
  87. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  88. #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
  89. | 0x00010000 /* TODO */ \
  90. | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
  91. /* 0x80010102 */
  92. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  93. #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
  94. | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
  95. | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
  96. | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
  97. | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
  98. | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
  99. | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
  100. | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
  101. /* 0x00220802 */
  102. #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
  103. | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
  104. | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
  105. | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
  106. | (10 << TIMING_CFG1_REFREC_SHIFT ) \
  107. | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
  108. | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
  109. | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
  110. /* 0x3835a322 */
  111. #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
  112. | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
  113. | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
  114. | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
  115. | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
  116. | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
  117. | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
  118. /* 0x129048c6 */ /* P9-45,may need tuning */
  119. #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
  120. | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
  121. /* 0x05100500 */
  122. #if defined(CONFIG_DDR_2T_TIMING)
  123. #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
  124. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  125. | SDRAM_CFG_2T_EN \
  126. | SDRAM_CFG_DBW_32 )
  127. #else
  128. #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
  129. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  130. | SDRAM_CFG_32_BE )
  131. /* 0x43080000 */
  132. #endif
  133. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  134. /* set burst length to 8 for 32-bit data path */
  135. #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
  136. | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
  137. /* 0x44480632 */
  138. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  139. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  140. /*0x02000000*/
  141. #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
  142. | DDRCDR_PZ_NOMZ \
  143. | DDRCDR_NZ_NOMZ \
  144. | DDRCDR_M_ODR )
  145. /*
  146. * FLASH on the Local Bus
  147. */
  148. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  149. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  150. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  151. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  152. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  153. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  154. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
  155. #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
  156. (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
  157. BR_V) /* valid */
  158. #define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \
  159. | OR_GPCM_XACS \
  160. | OR_GPCM_SCY_9 \
  161. | OR_GPCM_EHTR \
  162. | OR_GPCM_EAD )
  163. /* 0xFF006FF7 TODO SLOW 16 MB flash size */
  164. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
  165. #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
  166. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  167. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
  168. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  169. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  170. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  171. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
  172. #define CONFIG_SYS_RAMBOOT
  173. #endif
  174. #define CONFIG_SYS_INIT_RAM_LOCK 1
  175. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
  176. #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
  177. #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  178. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  179. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  180. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  181. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  182. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  183. /*
  184. * Local Bus LCRR and LBCR regs
  185. */
  186. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  187. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  188. #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \
  189. | (0xFF << LBCR_BMT_SHIFT) \
  190. | 0xF ) /* 0x0004ff0f */
  191. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
  192. /* drivers/mtd/nand/nand.c */
  193. #ifdef CONFIG_NAND_SPL
  194. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  195. #else
  196. #define CONFIG_SYS_NAND_BASE 0xE2800000
  197. #endif
  198. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  199. #define CONFIG_MTD_NAND_VERIFY_WRITE
  200. #define CONFIG_CMD_NAND 1
  201. #define CONFIG_NAND_FSL_ELBC 1
  202. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  203. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  204. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  205. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  206. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  207. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  208. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  209. #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
  210. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  211. | BR_PS_8 /* Port Size = 8 bit */ \
  212. | BR_MS_FCM /* MSEL = FCM */ \
  213. | BR_V ) /* valid */
  214. #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
  215. | OR_FCM_CSCT \
  216. | OR_FCM_CST \
  217. | OR_FCM_CHT \
  218. | OR_FCM_SCY_1 \
  219. | OR_FCM_TRLX \
  220. | OR_FCM_EHTR )
  221. /* 0xFFFF8396 */
  222. #ifdef CONFIG_NAND_U_BOOT
  223. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  224. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  225. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  226. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  227. #else
  228. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  229. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  230. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  231. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  232. #endif
  233. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  234. #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
  235. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  236. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  237. /* local bus read write buffer mapping */
  238. #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
  239. #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
  240. #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000
  241. #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
  242. /* Vitesse 7385 */
  243. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  244. #ifdef CONFIG_VSC7385_ENET
  245. #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
  246. #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
  247. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
  248. #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
  249. #endif
  250. /* pass open firmware flat tree */
  251. #define CONFIG_OF_LIBFDT 1
  252. #define CONFIG_OF_BOARD_SETUP 1
  253. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  254. /*
  255. * Serial Port
  256. */
  257. #define CONFIG_CONS_INDEX 1
  258. #define CONFIG_SYS_NS16550
  259. #define CONFIG_SYS_NS16550_SERIAL
  260. #define CONFIG_SYS_NS16550_REG_SIZE 1
  261. #define CONFIG_SYS_BAUDRATE_TABLE \
  262. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  263. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  264. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  265. /* Use the HUSH parser */
  266. #define CONFIG_SYS_HUSH_PARSER
  267. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  268. /* I2C */
  269. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  270. #define CONFIG_FSL_I2C
  271. #define CONFIG_I2C_MULTI_BUS
  272. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  273. #define CONFIG_SYS_I2C_SLAVE 0x7F
  274. #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
  275. #define CONFIG_SYS_I2C_OFFSET 0x3000
  276. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  277. /*
  278. * General PCI
  279. * Addresses are mapped 1-1.
  280. */
  281. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  282. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  283. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  284. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  285. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  286. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  287. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  288. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  289. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  290. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  291. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  292. /*
  293. * TSEC
  294. */
  295. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  296. #define CONFIG_NET_MULTI
  297. #define CONFIG_GMII /* MII PHY management */
  298. #ifdef CONFIG_TSEC1
  299. #define CONFIG_HAS_ETH0
  300. #define CONFIG_TSEC1_NAME "TSEC0"
  301. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  302. #define TSEC1_PHY_ADDR 0x1c
  303. #define TSEC1_FLAGS TSEC_GIGABIT
  304. #define TSEC1_PHYIDX 0
  305. #endif
  306. #ifdef CONFIG_TSEC2
  307. #define CONFIG_HAS_ETH1
  308. #define CONFIG_TSEC2_NAME "TSEC1"
  309. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  310. #define TSEC2_PHY_ADDR 4
  311. #define TSEC2_FLAGS TSEC_GIGABIT
  312. #define TSEC2_PHYIDX 0
  313. #endif
  314. /* Options are: TSEC[0-1] */
  315. #define CONFIG_ETHPRIME "TSEC1"
  316. /*
  317. * Configure on-board RTC
  318. */
  319. #define CONFIG_RTC_DS1337
  320. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  321. /*
  322. * Environment
  323. */
  324. #if defined(CONFIG_NAND_U_BOOT)
  325. #define CONFIG_ENV_IS_IN_NAND 1
  326. #define CONFIG_ENV_OFFSET (512 * 1024)
  327. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  328. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  329. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  330. #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
  331. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  332. #elif !defined(CONFIG_SYS_RAMBOOT)
  333. #define CONFIG_ENV_IS_IN_FLASH 1
  334. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  335. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  336. #define CONFIG_ENV_SIZE 0x2000
  337. /* Address and size of Redundant Environment Sector */
  338. #else
  339. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  340. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  341. #define CONFIG_ENV_SIZE 0x2000
  342. #endif
  343. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  344. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  345. /*
  346. * BOOTP options
  347. */
  348. #define CONFIG_BOOTP_BOOTFILESIZE
  349. #define CONFIG_BOOTP_BOOTPATH
  350. #define CONFIG_BOOTP_GATEWAY
  351. #define CONFIG_BOOTP_HOSTNAME
  352. /*
  353. * Command line configuration.
  354. */
  355. #include <config_cmd_default.h>
  356. #define CONFIG_CMD_PING
  357. #define CONFIG_CMD_DHCP
  358. #define CONFIG_CMD_I2C
  359. #define CONFIG_CMD_MII
  360. #define CONFIG_CMD_DATE
  361. #define CONFIG_CMD_PCI
  362. #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
  363. #undef CONFIG_CMD_SAVEENV
  364. #undef CONFIG_CMD_LOADS
  365. #endif
  366. #define CONFIG_CMDLINE_EDITING 1
  367. /*
  368. * Miscellaneous configurable options
  369. */
  370. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  371. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  372. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  373. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  374. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  375. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  376. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  377. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  378. /*
  379. * For booting Linux, the board info and command line data
  380. * have to be in the first 8 MB of memory, since this is
  381. * the maximum mapped by the Linux kernel during initialization.
  382. */
  383. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  384. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  385. #ifdef CONFIG_SYS_66MHZ
  386. /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
  387. /* 0x62040000 */
  388. #define CONFIG_SYS_HRCW_LOW (\
  389. 0x20000000 /* reserved, must be set */ |\
  390. HRCWL_DDRCM |\
  391. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  392. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  393. HRCWL_CSB_TO_CLKIN_2X1 |\
  394. HRCWL_CORE_TO_CSB_2X1)
  395. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
  396. #elif defined(CONFIG_SYS_33MHZ)
  397. /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
  398. /* 0x65040000 */
  399. #define CONFIG_SYS_HRCW_LOW (\
  400. 0x20000000 /* reserved, must be set */ |\
  401. HRCWL_DDRCM |\
  402. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  403. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  404. HRCWL_CSB_TO_CLKIN_5X1 |\
  405. HRCWL_CORE_TO_CSB_2X1)
  406. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
  407. #endif
  408. #define CONFIG_SYS_HRCW_HIGH_BASE (\
  409. HRCWH_PCI_HOST |\
  410. HRCWH_PCI1_ARBITER_ENABLE |\
  411. HRCWH_CORE_ENABLE |\
  412. HRCWH_BOOTSEQ_DISABLE |\
  413. HRCWH_SW_WATCHDOG_DISABLE |\
  414. HRCWH_TSEC1M_IN_RGMII |\
  415. HRCWH_TSEC2M_IN_RGMII |\
  416. HRCWH_BIG_ENDIAN)
  417. #ifdef CONFIG_NAND_SPL
  418. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  419. HRCWH_FROM_0XFFF00100 |\
  420. HRCWH_ROM_LOC_NAND_SP_8BIT |\
  421. HRCWH_RL_EXT_NAND)
  422. #else
  423. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  424. HRCWH_FROM_0X00000100 |\
  425. HRCWH_ROM_LOC_LOCAL_16BIT |\
  426. HRCWH_RL_EXT_LEGACY)
  427. #endif
  428. /* System IO Config */
  429. #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
  430. #define CONFIG_SYS_SICRL SICRL_USBDR /* Enable Internal USB Phy */
  431. #define CONFIG_SYS_HID0_INIT 0x000000000
  432. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  433. HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
  434. #define CONFIG_SYS_HID2 HID2_HBE
  435. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  436. /* DDR @ 0x00000000 */
  437. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
  438. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  439. /* PCI @ 0x80000000 */
  440. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
  441. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  442. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  443. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  444. /* PCI2 not supported on 8313 */
  445. #define CONFIG_SYS_IBAT3L (0)
  446. #define CONFIG_SYS_IBAT3U (0)
  447. #define CONFIG_SYS_IBAT4L (0)
  448. #define CONFIG_SYS_IBAT4U (0)
  449. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  450. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  451. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
  452. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  453. #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
  454. #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  455. #define CONFIG_SYS_IBAT7L (0)
  456. #define CONFIG_SYS_IBAT7U (0)
  457. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  458. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  459. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  460. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  461. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  462. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  463. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  464. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  465. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  466. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  467. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  468. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  469. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  470. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  471. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  472. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  473. /*
  474. * Internal Definitions
  475. *
  476. * Boot Flags
  477. */
  478. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  479. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  480. /*
  481. * Environment Configuration
  482. */
  483. #define CONFIG_ENV_OVERWRITE
  484. #define CONFIG_ETHADDR 00:E0:0C:00:95:01
  485. #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
  486. #define CONFIG_IPADDR 10.0.0.2
  487. #define CONFIG_SERVERIP 10.0.0.1
  488. #define CONFIG_GATEWAYIP 10.0.0.1
  489. #define CONFIG_NETMASK 255.0.0.0
  490. #define CONFIG_NETDEV eth1
  491. #define CONFIG_HOSTNAME mpc8313erdb
  492. #define CONFIG_ROOTPATH /nfs/root/path
  493. #define CONFIG_BOOTFILE uImage
  494. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  495. #define CONFIG_FDTFILE mpc8313erdb.dtb
  496. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  497. #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
  498. #define CONFIG_BAUDRATE 115200
  499. #define XMK_STR(x) #x
  500. #define MK_STR(x) XMK_STR(x)
  501. #define CONFIG_EXTRA_ENV_SETTINGS \
  502. "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
  503. "ethprime=TSEC1\0" \
  504. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  505. "tftpflash=tftpboot $loadaddr $uboot; " \
  506. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  507. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  508. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  509. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  510. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  511. "fdtaddr=780000\0" \
  512. "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
  513. "console=ttyS0\0" \
  514. "setbootargs=setenv bootargs " \
  515. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  516. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  517. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  518. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  519. #define CONFIG_NFSBOOTCOMMAND \
  520. "setenv rootdev /dev/nfs;" \
  521. "run setbootargs;" \
  522. "run setipargs;" \
  523. "tftp $loadaddr $bootfile;" \
  524. "tftp $fdtaddr $fdtfile;" \
  525. "bootm $loadaddr - $fdtaddr"
  526. #define CONFIG_RAMBOOTCOMMAND \
  527. "setenv rootdev /dev/ram;" \
  528. "run setbootargs;" \
  529. "tftp $ramdiskaddr $ramdiskfile;" \
  530. "tftp $loadaddr $bootfile;" \
  531. "tftp $fdtaddr $fdtfile;" \
  532. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  533. #undef MK_STR
  534. #undef XMK_STR
  535. #endif /* __CONFIG_H */