IDS8247.h 17 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
  33. #define CONFIG_MPC8272_FAMILY 1
  34. #define CONFIG_IDS8247 1
  35. #define CPU_ID_STR "MPC8247"
  36. #define CONFIG_CPM2 1 /* Has a CPM2 */
  37. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  38. #define CONFIG_BOOTCOUNT_LIMIT
  39. #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  40. #undef CONFIG_BOOTARGS
  41. #define CONFIG_EXTRA_ENV_SETTINGS \
  42. "netdev=eth0\0" \
  43. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  44. "nfsroot=${serverip}:${rootpath}\0" \
  45. "ramargs=setenv bootargs root=/dev/ram rw " \
  46. "console=ttyS0,115200\0" \
  47. "addip=setenv bootargs ${bootargs} " \
  48. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  49. ":${hostname}:${netdev}:off panic=1\0" \
  50. "flash_nfs=run nfsargs addip;" \
  51. "bootm ${kernel_addr}\0" \
  52. "flash_self=run ramargs addip;" \
  53. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  54. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
  55. "rootpath=/opt/eldk/ppc_82xx\0" \
  56. "bootfile=/tftpboot/IDS8247/uImage\0" \
  57. "kernel_addr=ff800000\0" \
  58. "ramdisk_addr=ffa00000\0" \
  59. ""
  60. #define CONFIG_BOOTCOMMAND "run flash_self"
  61. #define CONFIG_MISC_INIT_R 1
  62. /* enable I2C and select the hardware/software driver */
  63. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  64. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  65. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  66. #define CONFIG_SYS_I2C_SLAVE 0x7F
  67. /*
  68. * Software (bit-bang) I2C driver configuration
  69. */
  70. #define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
  71. #define I2C_ACTIVE (iop->pdir |= 0x00000080)
  72. #define I2C_TRISTATE (iop->pdir &= ~0x00000080)
  73. #define I2C_READ ((iop->pdat & 0x00000080) != 0)
  74. #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
  75. else iop->pdat &= ~0x00000080
  76. #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
  77. else iop->pdat &= ~0x00000100
  78. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  79. #if 0
  80. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  81. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  82. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  83. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  84. #define CONFIG_I2C_X
  85. #endif
  86. /*
  87. * select serial console configuration
  88. * use the extern UART for the console
  89. */
  90. #define CONFIG_CONS_INDEX 1
  91. #define CONFIG_BAUDRATE 115200
  92. /*
  93. * NS16550 Configuration
  94. */
  95. #define CONFIG_SYS_NS16550
  96. #define CONFIG_SYS_NS16550_SERIAL
  97. #define CONFIG_SYS_NS16550_REG_SIZE 1
  98. #define CONFIG_SYS_NS16550_CLK 14745600
  99. #define CONFIG_SYS_UART_BASE 0xE0000000
  100. #define CONFIG_SYS_UART_SIZE 0x10000
  101. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
  102. /* pass open firmware flat tree */
  103. #define CONFIG_OF_LIBFDT 1
  104. #define CONFIG_OF_BOARD_SETUP 1
  105. #define OF_TBCLK (bd->bi_busfreq / 4)
  106. #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
  107. /*
  108. * select ethernet configuration
  109. *
  110. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  111. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  112. * for FCC)
  113. *
  114. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  115. * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  116. */
  117. #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
  118. #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  119. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  120. #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
  121. #define CONFIG_ETHER_ON_FCC1
  122. #define FCC_ENET
  123. /*
  124. * - Rx-CLK is CLK10
  125. * - Tx-CLK is CLK9
  126. * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  127. * - Enable Full Duplex in FSMR
  128. */
  129. # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  130. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
  131. # define CONFIG_SYS_CPMFCR_RAMTYPE 0
  132. # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
  133. /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  134. #define CONFIG_8260_CLKIN 66666666 /* in Hz */
  135. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  136. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  137. #undef CONFIG_WATCHDOG /* watchdog disabled */
  138. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  139. /*
  140. * BOOTP options
  141. */
  142. #define CONFIG_BOOTP_SUBNETMASK
  143. #define CONFIG_BOOTP_GATEWAY
  144. #define CONFIG_BOOTP_HOSTNAME
  145. #define CONFIG_BOOTP_BOOTPATH
  146. #define CONFIG_BOOTP_BOOTFILESIZE
  147. #define CONFIG_RTC_PCF8563
  148. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  149. /*
  150. * Command line configuration.
  151. */
  152. #include <config_cmd_default.h>
  153. #define CONFIG_CMD_DHCP
  154. #define CONFIG_CMD_NFS
  155. #define CONFIG_CMD_NAND
  156. #define CONFIG_CMD_I2C
  157. #define CONFIG_CMD_SNTP
  158. /*
  159. * Miscellaneous configurable options
  160. */
  161. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  162. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  163. #if defined(CONFIG_CMD_KGDB)
  164. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  165. #else
  166. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  167. #endif
  168. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  169. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  170. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  171. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  172. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  173. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  174. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  175. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  176. #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
  177. /*
  178. * For booting Linux, the board info and command line data
  179. * have to be in the first 8 MB of memory, since this is
  180. * the maximum mapped by the Linux kernel during initialization.
  181. */
  182. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  183. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  184. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  185. #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
  186. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
  187. /* What should the base address of the main FLASH be and how big is
  188. * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
  189. * The main FLASH is whichever is connected to *CS0.
  190. */
  191. #define CONFIG_SYS_FLASH0_BASE 0xFFF00000
  192. #define CONFIG_SYS_FLASH0_SIZE 8
  193. /* Flash bank size (for preliminary settings)
  194. */
  195. #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
  196. /*-----------------------------------------------------------------------
  197. * FLASH organization
  198. */
  199. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  200. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
  201. #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  202. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  203. /* Environment in flash */
  204. #define CONFIG_ENV_IS_IN_FLASH 1
  205. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
  206. #define CONFIG_ENV_SIZE 0x20000
  207. #define CONFIG_ENV_SECT_SIZE 0x20000
  208. /*-----------------------------------------------------------------------
  209. * NAND-FLASH stuff
  210. *-----------------------------------------------------------------------
  211. */
  212. #if defined(CONFIG_CMD_NAND)
  213. #define CONFIG_SYS_NAND0_BASE 0xE1000000
  214. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  215. #endif /* CONFIG_CMD_NAND */
  216. /*-----------------------------------------------------------------------
  217. * Hard Reset Configuration Words
  218. *
  219. * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  220. * defines for the various registers affected by the HRCW e.g. changing
  221. * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  222. */
  223. #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
  224. /* no slaves so just fill with zeros */
  225. #define CONFIG_SYS_HRCW_SLAVE1 0
  226. #define CONFIG_SYS_HRCW_SLAVE2 0
  227. #define CONFIG_SYS_HRCW_SLAVE3 0
  228. #define CONFIG_SYS_HRCW_SLAVE4 0
  229. #define CONFIG_SYS_HRCW_SLAVE5 0
  230. #define CONFIG_SYS_HRCW_SLAVE6 0
  231. #define CONFIG_SYS_HRCW_SLAVE7 0
  232. /*-----------------------------------------------------------------------
  233. * Internal Memory Mapped Register
  234. */
  235. #define CONFIG_SYS_IMMR 0xF0000000
  236. /*-----------------------------------------------------------------------
  237. * Definitions for initial stack pointer and data area (in DPRAM)
  238. */
  239. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  240. #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
  241. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
  242. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  243. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  244. /*-----------------------------------------------------------------------
  245. * Start addresses for the final memory configuration
  246. * (Set up by the startup code)
  247. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  248. *
  249. * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
  250. */
  251. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  252. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
  253. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  254. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  255. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
  256. /*
  257. * Internal Definitions
  258. *
  259. * Boot Flags
  260. */
  261. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
  262. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  263. /*-----------------------------------------------------------------------
  264. * Cache Configuration
  265. */
  266. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  267. #if defined(CONFIG_CMD_KGDB)
  268. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  269. #endif
  270. /*-----------------------------------------------------------------------
  271. * HIDx - Hardware Implementation-dependent Registers 2-11
  272. *-----------------------------------------------------------------------
  273. * HID0 also contains cache control - initially enable both caches and
  274. * invalidate contents, then the final state leaves only the instruction
  275. * cache enabled. Note that Power-On and Hard reset invalidate the caches,
  276. * but Soft reset does not.
  277. *
  278. * HID1 has only read-only information - nothing to set.
  279. */
  280. #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
  281. #define CONFIG_SYS_HID0_FINAL 0
  282. #define CONFIG_SYS_HID2 0
  283. /*-----------------------------------------------------------------------
  284. * RMR - Reset Mode Register 5-5
  285. *-----------------------------------------------------------------------
  286. * turn on Checkstop Reset Enable
  287. */
  288. #define CONFIG_SYS_RMR 0
  289. /*-----------------------------------------------------------------------
  290. * BCR - Bus Configuration 4-25
  291. *-----------------------------------------------------------------------
  292. */
  293. #define CONFIG_SYS_BCR 0
  294. /*-----------------------------------------------------------------------
  295. * SIUMCR - SIU Module Configuration 4-31
  296. *-----------------------------------------------------------------------
  297. */
  298. #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
  299. /*-----------------------------------------------------------------------
  300. * SYPCR - System Protection Control 4-35
  301. * SYPCR can only be written once after reset!
  302. *-----------------------------------------------------------------------
  303. * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  304. */
  305. #if defined(CONFIG_WATCHDOG)
  306. #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  307. SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
  308. #else
  309. #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  310. SYPCR_SWRI|SYPCR_SWP)
  311. #endif /* CONFIG_WATCHDOG */
  312. /*-----------------------------------------------------------------------
  313. * TMCNTSC - Time Counter Status and Control 4-40
  314. *-----------------------------------------------------------------------
  315. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  316. * and enable Time Counter
  317. */
  318. #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  319. /*-----------------------------------------------------------------------
  320. * PISCR - Periodic Interrupt Status and Control 4-42
  321. *-----------------------------------------------------------------------
  322. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  323. * Periodic timer
  324. */
  325. #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  326. /*-----------------------------------------------------------------------
  327. * SCCR - System Clock Control 9-8
  328. *-----------------------------------------------------------------------
  329. * Ensure DFBRG is Divide by 16
  330. */
  331. #define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
  332. /*-----------------------------------------------------------------------
  333. * RCCR - RISC Controller Configuration 13-7
  334. *-----------------------------------------------------------------------
  335. */
  336. #define CONFIG_SYS_RCCR 0
  337. /*
  338. * Init Memory Controller:
  339. *
  340. * Bank Bus Machine PortSz Device
  341. * ---- --- ------- ------ ------
  342. * 0 60x GPCM 16 bit FLASH
  343. * 1 60x GPCM 8 bit NAND
  344. * 2 60x SDRAM 32 bit SDRAM
  345. * 3 60x GPCM 8 bit UART
  346. *
  347. */
  348. #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
  349. /* Minimum mask to separate preliminary
  350. * address ranges for CS[0:2]
  351. */
  352. #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
  353. #define CONFIG_SYS_MPTPR 0x6600
  354. /*-----------------------------------------------------------------------------
  355. * Address for Mode Register Set (MRS) command
  356. *-----------------------------------------------------------------------------
  357. */
  358. #define CONFIG_SYS_MRS_OFFS 0x00000110
  359. /* Bank 0 - FLASH
  360. */
  361. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
  362. BRx_PS_8 |\
  363. BRx_MS_GPCM_P |\
  364. BRx_V)
  365. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  366. ORxG_SCY_6_CLK )
  367. #if defined(CONFIG_CMD_NAND)
  368. /* Bank 1 - NAND Flash
  369. */
  370. #define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
  371. #define CONFIG_SYS_NAND_SIZE 0x8000
  372. #define CONFIG_SYS_OR_TIMING_NAND 0x000036
  373. #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
  374. #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
  375. #endif
  376. /* Bank 2 - 60x bus SDRAM
  377. */
  378. #define CONFIG_SYS_PSRT 0x20
  379. #define CONFIG_SYS_LSRT 0x20
  380. #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
  381. BRx_PS_32 |\
  382. BRx_MS_SDRAM_P |\
  383. BRx_V)
  384. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
  385. /* SDRAM initialization values
  386. */
  387. #define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
  388. ORxS_BPD_4 |\
  389. ORxS_ROWST_PBI0_A9 |\
  390. ORxS_NUMR_12)
  391. #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
  392. PSDMR_BSMA_A15_A17 |\
  393. PSDMR_SDA10_PBI0_A10 |\
  394. PSDMR_RFRC_5_CLK |\
  395. PSDMR_PRETOACT_2W |\
  396. PSDMR_ACTTORW_2W |\
  397. PSDMR_BL |\
  398. PSDMR_LDOTOPRE_2C |\
  399. PSDMR_WRC_3C |\
  400. PSDMR_CL_3)
  401. /* Bank 3 - UART
  402. */
  403. #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
  404. #define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
  405. #endif /* __CONFIG_H */