HH405.h 20 KB

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  1. /*
  2. * (C) Copyright 2001-2004
  3. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  4. *
  5. * (C) Copyright 2005
  6. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7. *
  8. * (C) Copyright 2006
  9. * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  39. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  40. #define CONFIG_HH405 1 /* ...on a HH405 board */
  41. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  42. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  43. #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
  44. #define CONFIG_BOARD_TYPES 1 /* support board types */
  45. #define CONFIG_BAUDRATE 9600
  46. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  47. #undef CONFIG_BOOTARGS
  48. #undef CONFIG_BOOTCOMMAND
  49. #define CONFIG_PREBOOT "autoupd"
  50. #define CONFIG_EXTRA_ENV_SETTINGS \
  51. "pciconfighost=1\0" \
  52. ""
  53. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  54. #define CONFIG_PPC4xx_EMAC
  55. #define CONFIG_NET_MULTI 1
  56. #undef CONFIG_HAS_ETH1
  57. #define CONFIG_MII 1 /* MII PHY management */
  58. #define CONFIG_PHY_ADDR 0 /* PHY address */
  59. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  60. #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
  61. #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  62. /*
  63. * Video console
  64. */
  65. #define CONFIG_VIDEO /* for sm501 video support */
  66. #ifdef CONFIG_VIDEO
  67. #define CONFIG_VIDEO_SM501
  68. #if 0
  69. #define CONFIG_VIDEO_SM501_32BPP
  70. #else
  71. #define CONFIG_VIDEO_SM501_16BPP
  72. #endif
  73. #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
  74. #define CONFIG_CFB_CONSOLE
  75. #define CONFIG_VIDEO_LOGO
  76. #define CONFIG_VGA_AS_SINGLE_DEVICE
  77. #define CONFIG_CONSOLE_EXTRA_INFO
  78. #define CONFIG_VIDEO_SW_CURSOR
  79. #define CONFIG_SPLASH_SCREEN
  80. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  81. #define CONFIG_SPLASH_SCREEN
  82. #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
  83. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
  84. #endif /* CONFIG_VIDEO */
  85. /*
  86. * BOOTP options
  87. */
  88. #define CONFIG_BOOTP_BOOTFILESIZE
  89. #define CONFIG_BOOTP_BOOTPATH
  90. #define CONFIG_BOOTP_GATEWAY
  91. #define CONFIG_BOOTP_HOSTNAME
  92. /*
  93. * Command line configuration.
  94. */
  95. #include <config_cmd_default.h>
  96. #define CONFIG_CMD_DHCP
  97. #define CONFIG_CMD_PCI
  98. #define CONFIG_CMD_IRQ
  99. #define CONFIG_CMD_IDE
  100. #define CONFIG_CMD_FAT
  101. #define CONFIG_CMD_EXT2
  102. #define CONFIG_CMD_ELF
  103. #define CONFIG_CMD_NAND
  104. #define CONFIG_CMD_I2C
  105. #define CONFIG_CMD_DATE
  106. #define CONFIG_CMD_MII
  107. #define CONFIG_CMD_PING
  108. #define CONFIG_CMD_EEPROM
  109. #ifdef CONFIG_VIDEO
  110. #define CONFIG_CMD_BMP
  111. #endif
  112. #define CONFIG_MAC_PARTITION
  113. #define CONFIG_DOS_PARTITION
  114. #define CONFIG_SUPPORT_VFAT
  115. #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
  116. #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
  117. #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
  118. #undef CONFIG_WATCHDOG /* watchdog disabled */
  119. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  120. /*
  121. * Miscellaneous configurable options
  122. */
  123. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  124. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  125. #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  126. #ifdef CONFIG_SYS_HUSH_PARSER
  127. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  128. #endif
  129. #if defined(CONFIG_CMD_KGDB)
  130. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  131. #else
  132. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  133. #endif
  134. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  135. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  136. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  137. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  138. #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */
  139. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  140. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  141. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  142. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  143. #define CONFIG_SYS_BASE_BAUD 691200
  144. #define CONFIG_UART1_CONSOLE /* define for uart1 as console */
  145. /* The following table includes the supported baudrates */
  146. #define CONFIG_SYS_BAUDRATE_TABLE \
  147. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  148. 57600, 115200, 230400, 460800, 921600 }
  149. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  150. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  151. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  152. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  153. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  154. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  155. /*-----------------------------------------------------------------------
  156. * RTC stuff
  157. *-----------------------------------------------------------------------
  158. */
  159. #define CONFIG_RTC_DS1338
  160. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  161. /*-----------------------------------------------------------------------
  162. * NAND-FLASH stuff
  163. *-----------------------------------------------------------------------
  164. */
  165. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  166. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  167. #define NAND_BIG_DELAY_US 25
  168. #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
  169. #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
  170. #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
  171. #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
  172. #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
  173. #define CONFIG_SYS_NAND_QUIET 1
  174. /*-----------------------------------------------------------------------
  175. * PCI stuff
  176. *-----------------------------------------------------------------------
  177. */
  178. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  179. #define PCI_HOST_FORCE 1 /* configure as pci host */
  180. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  181. #define CONFIG_PCI /* include pci support */
  182. #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
  183. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  184. /* resource configuration */
  185. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  186. #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
  187. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  188. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
  189. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  190. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  191. #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
  192. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  193. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  194. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  195. #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  196. /*-----------------------------------------------------------------------
  197. * IDE/ATA stuff
  198. *-----------------------------------------------------------------------
  199. */
  200. #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
  201. #undef CONFIG_IDE_LED /* no led for ide supported */
  202. #define CONFIG_IDE_RESET 1 /* reset for ide supported */
  203. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
  204. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
  205. #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
  206. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  207. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
  208. #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
  209. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
  210. /*
  211. * For booting Linux, the board info and command line data
  212. * have to be in the first 8 MB of memory, since this is
  213. * the maximum mapped by the Linux kernel during initialization.
  214. */
  215. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  216. /*-----------------------------------------------------------------------
  217. * FLASH organization
  218. */
  219. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  220. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  221. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  222. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  223. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  224. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  225. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  226. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  227. /*
  228. * The following defines are added for buggy IOP480 byte interface.
  229. * All other boards should use the standard values (CPCI405 etc.)
  230. */
  231. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  232. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  233. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  234. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  235. #if 0 /* test-only */
  236. #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
  237. #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
  238. #endif
  239. /*-----------------------------------------------------------------------
  240. * Start addresses for the final memory configuration
  241. * (Set up by the startup code)
  242. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  243. */
  244. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  245. #define CONFIG_SYS_FLASH_BASE 0xFFF80000
  246. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  247. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
  248. #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
  249. #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
  250. # define CONFIG_SYS_RAMBOOT 1
  251. #else
  252. # undef CONFIG_SYS_RAMBOOT
  253. #endif
  254. /*-----------------------------------------------------------------------
  255. * Environment Variable setup
  256. */
  257. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  258. #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
  259. #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
  260. /* total size of a CAT24WC16 is 2048 bytes */
  261. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
  262. #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
  263. /*-----------------------------------------------------------------------
  264. * I2C EEPROM (CAT24WC16) for environment
  265. */
  266. #define CONFIG_HARD_I2C /* I2c with hardware support */
  267. #if 0 /* test-only */
  268. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  269. #else
  270. #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
  271. #endif
  272. #define CONFIG_SYS_I2C_SLAVE 0x7F
  273. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
  274. #define CONFIG_SYS_EEPROM_WREN 1
  275. #if 1 /* test-only */
  276. /* CAT24WC08/16... */
  277. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  278. /* mask of address bits that overflow into the "EEPROM chip address" */
  279. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  280. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  281. /* 16 byte page write mode using*/
  282. /* last 4 bits of the address */
  283. #else
  284. /* CAT24WC32/64... */
  285. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
  286. /* mask of address bits that overflow into the "EEPROM chip address" */
  287. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
  288. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
  289. /* 32 byte page write mode using*/
  290. /* last 5 bits of the address */
  291. #endif
  292. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  293. /*-----------------------------------------------------------------------
  294. * External Bus Controller (EBC) Setup
  295. */
  296. #define CAN_BA 0xF0000000 /* CAN Base Address */
  297. #define LCD_BA 0xF1000000 /* Epson LCD Base Address */
  298. #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
  299. #define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
  300. /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
  301. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  302. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  303. /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
  304. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  305. #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
  306. /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
  307. #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  308. #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  309. /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
  310. #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  311. #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
  312. /* Memory Bank 4 (Epson LCD) initialization */
  313. #define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
  314. #define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
  315. /*-----------------------------------------------------------------------
  316. * LCD Setup
  317. */
  318. #define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
  319. #define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
  320. #define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
  321. #define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
  322. /*-----------------------------------------------------------------------
  323. * Universal Interrupt Controller (UIC) Setup
  324. */
  325. /*
  326. * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
  327. */
  328. #define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
  329. /*-----------------------------------------------------------------------
  330. * FPGA stuff
  331. */
  332. #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
  333. #define LCD_CLK_OFF 0x0000 /* Off */
  334. #define LCD_CLK_02083 0x1000 /* 2.083 MHz */
  335. #define LCD_CLK_03135 0x2000 /* 3.135 MHz */
  336. #define LCD_CLK_04165 0x3000 /* 4.165 MHz */
  337. #define LCD_CLK_06250 0x4000 /* 6.250 MHz */
  338. #define LCD_CLK_08330 0x5000 /* 8.330 MHz */
  339. #define LCD_CLK_12500 0x6000 /* 12.50 MHz */
  340. #define LCD_CLK_25000 0x7000 /* 25.00 MHz */
  341. #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  342. #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
  343. /* FPGA program pin configuration */
  344. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  345. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  346. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  347. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  348. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  349. /*-----------------------------------------------------------------------
  350. * Definitions for initial stack pointer and data area (in data cache)
  351. */
  352. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  353. #define CONFIG_SYS_TEMP_STACK_OCM 1
  354. /* On Chip Memory location */
  355. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  356. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  357. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  358. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  359. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  360. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  361. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  362. /*-----------------------------------------------------------------------
  363. * Definitions for GPIO setup (PPC405EP specific)
  364. *
  365. * GPIO0[0] - External Bus Controller BLAST output
  366. * GPIO0[1-9] - Instruction trace outputs -> GPIO
  367. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  368. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  369. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  370. * GPIO0[24-27] - UART0 control signal inputs/outputs
  371. * GPIO0[28-29] - UART1 data signal input/output
  372. * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  373. */
  374. #define CONFIG_SYS_GPIO0_OSRH 0x40000550
  375. #define CONFIG_SYS_GPIO0_OSRL 0x00000110
  376. #define CONFIG_SYS_GPIO0_ISR1H 0x00000000
  377. #define CONFIG_SYS_GPIO0_ISR1L 0x15555440
  378. #define CONFIG_SYS_GPIO0_TSRH 0x00000000
  379. #define CONFIG_SYS_GPIO0_TSRL 0x00000000
  380. #define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
  381. #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
  382. #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
  383. #define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
  384. #define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
  385. #define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
  386. /*
  387. * Internal Definitions
  388. *
  389. * Boot Flags
  390. */
  391. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  392. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  393. /*
  394. * Default speed selection (cpu_plb_opb_ebc) in mhz.
  395. * This value will be set if iic boot eprom is disabled.
  396. */
  397. #if 0
  398. #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  399. #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  400. #endif
  401. #if 0
  402. #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
  403. #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
  404. #endif
  405. #if 1
  406. #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
  407. #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
  408. #endif
  409. #endif /* __CONFIG_H */