CMS700.h 12 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * CMS700.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_VOM405 1 /* ...on a VOM405 board */
  35. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  36. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  37. #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
  38. #define CONFIG_BAUDRATE 9600
  39. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  40. #undef CONFIG_BOOTARGS
  41. #undef CONFIG_BOOTCOMMAND
  42. #define CONFIG_PREBOOT /* enable preboot variable */
  43. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  44. #define CONFIG_PPC4xx_EMAC
  45. #define CONFIG_NET_MULTI 1
  46. #undef CONFIG_HAS_ETH1
  47. #define CONFIG_MII 1 /* MII PHY management */
  48. #define CONFIG_PHY_ADDR 0 /* PHY address */
  49. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  50. #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
  51. /*
  52. * BOOTP options
  53. */
  54. #define CONFIG_BOOTP_SUBNETMASK
  55. #define CONFIG_BOOTP_GATEWAY
  56. #define CONFIG_BOOTP_HOSTNAME
  57. #define CONFIG_BOOTP_BOOTPATH
  58. #define CONFIG_BOOTP_DNS
  59. #define CONFIG_BOOTP_DNS2
  60. #define CONFIG_BOOTP_SEND_HOSTNAME
  61. /*
  62. * Command line configuration.
  63. */
  64. #include <config_cmd_default.h>
  65. #define CONFIG_CMD_DHCP
  66. #define CONFIG_CMD_BSP
  67. #define CONFIG_CMD_ELF
  68. #define CONFIG_CMD_NAND
  69. #define CONFIG_CMD_I2C
  70. #define CONFIG_CMD_DATE
  71. #define CONFIG_CMD_MII
  72. #define CONFIG_CMD_PING
  73. #define CONFIG_CMD_EEPROM
  74. #undef CONFIG_WATCHDOG /* watchdog disabled */
  75. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  76. #undef CONFIG_PRAM /* no "protected RAM" */
  77. /*
  78. * Miscellaneous configurable options
  79. */
  80. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  81. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  82. #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  83. #ifdef CONFIG_SYS_HUSH_PARSER
  84. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  85. #endif
  86. #if defined(CONFIG_CMD_KGDB)
  87. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  88. #else
  89. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  90. #endif
  91. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  92. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  93. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  94. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  95. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  96. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  97. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  98. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  99. #define CONFIG_SYS_BASE_BAUD 691200
  100. #define CONFIG_UART1_CONSOLE /* define for uart1 as console */
  101. /* The following table includes the supported baudrates */
  102. #define CONFIG_SYS_BAUDRATE_TABLE \
  103. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  104. 57600, 115200, 230400, 460800, 921600 }
  105. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  106. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  107. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  108. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  109. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  110. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  111. /*-----------------------------------------------------------------------
  112. * RTC stuff
  113. *-----------------------------------------------------------------------
  114. */
  115. #define CONFIG_RTC_DS1337
  116. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  117. /*-----------------------------------------------------------------------
  118. * NAND-FLASH stuff
  119. *-----------------------------------------------------------------------
  120. */
  121. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  122. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  123. #define NAND_BIG_DELAY_US 25
  124. #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
  125. #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
  126. #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
  127. #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
  128. #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
  129. #define CONFIG_SYS_NAND_QUIET 1
  130. /*
  131. * For booting Linux, the board info and command line data
  132. * have to be in the first 8 MB of memory, since this is
  133. * the maximum mapped by the Linux kernel during initialization.
  134. */
  135. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  136. /*-----------------------------------------------------------------------
  137. * FLASH organization
  138. */
  139. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  140. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  141. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  142. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  143. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  144. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  145. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  146. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  147. /*
  148. * The following defines are added for buggy IOP480 byte interface.
  149. * All other boards should use the standard values (CPCI405 etc.)
  150. */
  151. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  152. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  153. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  154. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  155. /*-----------------------------------------------------------------------
  156. * Start addresses for the final memory configuration
  157. * (Set up by the startup code)
  158. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  159. */
  160. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  161. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
  162. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  163. #define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
  164. #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
  165. #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
  166. # define CONFIG_SYS_RAMBOOT 1
  167. #else
  168. # undef CONFIG_SYS_RAMBOOT
  169. #endif
  170. /*-----------------------------------------------------------------------
  171. * Environment Variable setup
  172. */
  173. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  174. #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
  175. #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
  176. /* total size of a CAT24WC16 is 2048 bytes */
  177. /*-----------------------------------------------------------------------
  178. * I2C EEPROM (CAT24WC16) for environment
  179. */
  180. #define CONFIG_HARD_I2C /* I2c with hardware support */
  181. #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
  182. #define CONFIG_SYS_I2C_SLAVE 0x7F
  183. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  184. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  185. /* mask of address bits that overflow into the "EEPROM chip address" */
  186. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  187. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  188. /* 16 byte page write mode using*/
  189. /* last 4 bits of the address */
  190. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  191. #define CONFIG_SYS_EEPROM_WREN 1
  192. /*-----------------------------------------------------------------------
  193. * External Bus Controller (EBC) Setup
  194. */
  195. #define CONFIG_SYS_PLD_BASE 0xf0000000
  196. #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
  197. /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
  198. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  199. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  200. /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
  201. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  202. #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
  203. /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
  204. #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  205. #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  206. /*-----------------------------------------------------------------------
  207. * FPGA stuff
  208. */
  209. #define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
  210. /* FPGA program pin configuration */
  211. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
  212. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
  213. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
  214. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
  215. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
  216. /*-----------------------------------------------------------------------
  217. * Definitions for initial stack pointer and data area (in data cache)
  218. */
  219. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  220. #define CONFIG_SYS_TEMP_STACK_OCM 1
  221. /* On Chip Memory location */
  222. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  223. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  224. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  225. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  226. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  227. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  228. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  229. /*-----------------------------------------------------------------------
  230. * Definitions for GPIO setup (PPC405EP specific)
  231. *
  232. * GPIO0[0] - External Bus Controller BLAST output
  233. * GPIO0[1-9] - Instruction trace outputs -> GPIO
  234. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  235. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  236. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  237. * GPIO0[24-27] - UART0 control signal inputs/outputs
  238. * GPIO0[28-29] - UART1 data signal input/output
  239. * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  240. */
  241. /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
  242. /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
  243. /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
  244. /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
  245. #define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
  246. #define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
  247. #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
  248. #define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
  249. #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
  250. #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
  251. #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
  252. #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
  253. #define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
  254. /*
  255. * Internal Definitions
  256. *
  257. * Boot Flags
  258. */
  259. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  260. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  261. /*
  262. * Default speed selection (cpu_plb_opb_ebc) in mhz.
  263. * This value will be set if iic boot eprom is disabled.
  264. */
  265. #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
  266. #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
  267. #endif /* __CONFIG_H */