board_common.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) Aspeed Technology Inc.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <ram.h>
  8. #include <timer.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/timer.h>
  11. #include <linux/bitops.h>
  12. #include <linux/err.h>
  13. #include <dm/uclass.h>
  14. #include <asm/arch/scu_ast2600.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* Memory Control registers */
  17. #define MCR_BASE 0x1e6e0000
  18. #define MCR_CONF (MCR_BASE + 0x004)
  19. /* bit fields of MCR_CONF */
  20. #define MCR_CONF_ECC_EN BIT(7)
  21. #define MCR_CONF_VGA_MEMSZ_MASK GENMASK(3, 2)
  22. #define MCR_CONF_VGA_MEMSZ_SHIFT 2
  23. #define MCR_CONF_MEMSZ_MASK GENMASK(1, 0)
  24. #define MCR_CONF_MEMSZ_SHIFT 0
  25. int dram_init(void)
  26. {
  27. int ret;
  28. struct udevice *dev;
  29. struct ram_info ram;
  30. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  31. if (ret) {
  32. debug("cannot get DRAM driver\n");
  33. return ret;
  34. }
  35. ret = ram_get_info(dev, &ram);
  36. if (ret) {
  37. debug("cannot get DRAM information\n");
  38. return ret;
  39. }
  40. gd->ram_size = ram.size;
  41. return 0;
  42. }
  43. int board_init(void)
  44. {
  45. int i = 0, rc;
  46. struct udevice *dev;
  47. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  48. while (1) {
  49. rc = uclass_get_device(UCLASS_MISC, i++, &dev);
  50. if (rc)
  51. break;
  52. }
  53. return 0;
  54. }
  55. void board_add_ram_info(int use_default)
  56. {
  57. int rc;
  58. uint32_t conf;
  59. uint32_t ecc, act_size, vga_rsvd;
  60. struct udevice *scu_dev;
  61. struct ast2600_scu *scu;
  62. rc = uclass_get_device_by_driver(UCLASS_CLK,
  63. DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
  64. if (rc) {
  65. debug("%s: cannot find SCU device, rc=%d\n", __func__, rc);
  66. return;
  67. }
  68. scu = devfdt_get_addr_ptr(scu_dev);
  69. if (IS_ERR_OR_NULL(scu)) {
  70. debug("%s: cannot get SCU address pointer\n", __func__);
  71. return;
  72. }
  73. conf = readl(MCR_CONF);
  74. ecc = conf & MCR_CONF_ECC_EN;
  75. act_size = 0x100 << ((conf & MCR_CONF_MEMSZ_MASK) >> MCR_CONF_MEMSZ_SHIFT);
  76. vga_rsvd = 0x8 << ((conf & MCR_CONF_VGA_MEMSZ_MASK) >> MCR_CONF_VGA_MEMSZ_SHIFT);
  77. /* no VGA reservation if efuse VGA disable bit is set */
  78. if (readl(scu->efuse) & SCU_EFUSE_DIS_VGA)
  79. vga_rsvd = 0;
  80. printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size,
  81. vga_rsvd, (ecc) ? "on" : "off");
  82. }
  83. void enable_caches(void)
  84. {
  85. /* get rid of the warning message */
  86. }