tqm8xx.c 17 KB

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  1. /*
  2. * (C) Copyright 2000-2008
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <hwconfig.h>
  9. #include <mpc8xx.h>
  10. #ifdef CONFIG_PS2MULT
  11. #include <ps2mult.h>
  12. #endif
  13. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  14. #include <libfdt.h>
  15. #endif
  16. extern flash_info_t flash_info[]; /* FLASH chips info */
  17. DECLARE_GLOBAL_DATA_PTR;
  18. static long int dram_size (long int, long int *, long int);
  19. #define _NOT_USED_ 0xFFFFFFFF
  20. /* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
  21. const uint sdram_table[] =
  22. {
  23. /*
  24. * Single Read. (Offset 0 in UPMA RAM)
  25. */
  26. 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
  27. 0x1FF5FC47, /* last */
  28. /*
  29. * SDRAM Initialization (offset 5 in UPMA RAM)
  30. *
  31. * This is no UPM entry point. The following definition uses
  32. * the remaining space to establish an initialization
  33. * sequence, which is executed by a RUN command.
  34. *
  35. */
  36. 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
  37. /*
  38. * Burst Read. (Offset 8 in UPMA RAM)
  39. */
  40. 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
  41. 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
  42. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  43. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  44. /*
  45. * Single Write. (Offset 18 in UPMA RAM)
  46. */
  47. 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
  48. 0x1FF5FC47, /* last */
  49. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  50. /*
  51. * Burst Write. (Offset 20 in UPMA RAM)
  52. */
  53. 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
  54. 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
  55. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  56. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57. /*
  58. * Refresh (Offset 30 in UPMA RAM)
  59. */
  60. 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  61. 0xFFFFFC84, 0xFFFFFC07, /* last */
  62. _NOT_USED_, _NOT_USED_,
  63. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  64. /*
  65. * Exception. (Offset 3c in UPMA RAM)
  66. */
  67. 0xFFFFFC07, /* last */
  68. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  69. };
  70. /* ------------------------------------------------------------------------- */
  71. /*
  72. * Check Board Identity:
  73. *
  74. * Test TQ ID string (TQM8xx...)
  75. * If present, check for "L" type (no second DRAM bank),
  76. * otherwise "L" type is assumed as default.
  77. *
  78. * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
  79. */
  80. int checkboard (void)
  81. {
  82. char buf[64];
  83. int i;
  84. int l = getenv_f("serial#", buf, sizeof(buf));
  85. puts ("Board: ");
  86. if (l < 0 || strncmp(buf, "TQM8", 4)) {
  87. puts ("### No HW ID - assuming TQM8xxL\n");
  88. return (0);
  89. }
  90. if ((buf[6] == 'L')) { /* a TQM8xxL type */
  91. gd->board_type = 'L';
  92. }
  93. if ((buf[6] == 'M')) { /* a TQM8xxM type */
  94. gd->board_type = 'M';
  95. }
  96. if ((buf[6] == 'D')) { /* a TQM885D type */
  97. gd->board_type = 'D';
  98. }
  99. for (i = 0; i < l; ++i) {
  100. if (buf[i] == ' ')
  101. break;
  102. putc (buf[i]);
  103. }
  104. putc ('\n');
  105. return (0);
  106. }
  107. /* ------------------------------------------------------------------------- */
  108. int dram_init(void)
  109. {
  110. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  111. volatile memctl8xx_t *memctl = &immap->im_memctl;
  112. long int size8, size9, size10;
  113. long int size_b0 = 0;
  114. long int size_b1 = 0;
  115. int board_type = gd->board_type;
  116. upmconfig (UPMA, (uint *) sdram_table,
  117. sizeof (sdram_table) / sizeof (uint));
  118. /*
  119. * Preliminary prescaler for refresh (depends on number of
  120. * banks): This value is selected for four cycles every 62.4 us
  121. * with two SDRAM banks or four cycles every 31.2 us with one
  122. * bank. It will be adjusted after memory sizing.
  123. */
  124. memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
  125. /*
  126. * The following value is used as an address (i.e. opcode) for
  127. * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
  128. * the port size is 32bit the SDRAM does NOT "see" the lower two
  129. * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
  130. * MICRON SDRAMs:
  131. * -> 0 00 010 0 010
  132. * | | | | +- Burst Length = 4
  133. * | | | +----- Burst Type = Sequential
  134. * | | +------- CAS Latency = 2
  135. * | +----------- Operating Mode = Standard
  136. * +-------------- Write Burst Mode = Programmed Burst Length
  137. */
  138. memctl->memc_mar = 0x00000088;
  139. /*
  140. * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
  141. * preliminary addresses - these have to be modified after the
  142. * SDRAM size has been determined.
  143. */
  144. memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
  145. memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
  146. #ifndef CONFIG_CAN_DRIVER
  147. if ((board_type != 'L') &&
  148. (board_type != 'M') &&
  149. (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
  150. memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
  151. memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
  152. }
  153. #endif /* CONFIG_CAN_DRIVER */
  154. memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
  155. udelay (200);
  156. /* perform SDRAM initializsation sequence */
  157. memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
  158. udelay (1);
  159. memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
  160. udelay (1);
  161. #ifndef CONFIG_CAN_DRIVER
  162. if ((board_type != 'L') &&
  163. (board_type != 'M') &&
  164. (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
  165. memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
  166. udelay (1);
  167. memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
  168. udelay (1);
  169. }
  170. #endif /* CONFIG_CAN_DRIVER */
  171. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  172. udelay (1000);
  173. /*
  174. * Check Bank 0 Memory Size for re-configuration
  175. *
  176. * try 8 column mode
  177. */
  178. size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
  179. debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
  180. udelay (1000);
  181. /*
  182. * try 9 column mode
  183. */
  184. size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
  185. debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
  186. udelay(1000);
  187. #if defined(CONFIG_SYS_MAMR_10COL)
  188. /*
  189. * try 10 column mode
  190. */
  191. size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
  192. debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
  193. #else
  194. size10 = 0;
  195. #endif /* CONFIG_SYS_MAMR_10COL */
  196. if ((size8 < size10) && (size9 < size10)) {
  197. size_b0 = size10;
  198. } else if ((size8 < size9) && (size10 < size9)) {
  199. size_b0 = size9;
  200. memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
  201. udelay (500);
  202. } else {
  203. size_b0 = size8;
  204. memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
  205. udelay (500);
  206. }
  207. debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
  208. #ifndef CONFIG_CAN_DRIVER
  209. if ((board_type != 'L') &&
  210. (board_type != 'M') &&
  211. (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
  212. /*
  213. * Check Bank 1 Memory Size
  214. * use current column settings
  215. * [9 column SDRAM may also be used in 8 column mode,
  216. * but then only half the real size will be used.]
  217. */
  218. size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
  219. SDRAM_MAX_SIZE);
  220. debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
  221. } else {
  222. size_b1 = 0;
  223. }
  224. #endif /* CONFIG_CAN_DRIVER */
  225. udelay (1000);
  226. /*
  227. * Adjust refresh rate depending on SDRAM type, both banks
  228. * For types > 128 MBit leave it at the current (fast) rate
  229. */
  230. if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
  231. /* reduce to 15.6 us (62.4 us / quad) */
  232. memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
  233. udelay (1000);
  234. }
  235. /*
  236. * Final mapping: map bigger bank first
  237. */
  238. if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
  239. memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  240. memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
  241. if (size_b0 > 0) {
  242. /*
  243. * Position Bank 0 immediately above Bank 1
  244. */
  245. memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  246. memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
  247. + size_b1;
  248. } else {
  249. unsigned long reg;
  250. /*
  251. * No bank 0
  252. *
  253. * invalidate bank
  254. */
  255. memctl->memc_br2 = 0;
  256. /* adjust refresh rate depending on SDRAM type, one bank */
  257. reg = memctl->memc_mptpr;
  258. reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
  259. memctl->memc_mptpr = reg;
  260. }
  261. } else { /* SDRAM Bank 0 is bigger - map first */
  262. memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  263. memctl->memc_br2 =
  264. (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
  265. if (size_b1 > 0) {
  266. /*
  267. * Position Bank 1 immediately above Bank 0
  268. */
  269. memctl->memc_or3 =
  270. ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  271. memctl->memc_br3 =
  272. ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
  273. + size_b0;
  274. } else {
  275. unsigned long reg;
  276. #ifndef CONFIG_CAN_DRIVER
  277. /*
  278. * No bank 1
  279. *
  280. * invalidate bank
  281. */
  282. memctl->memc_br3 = 0;
  283. #endif /* CONFIG_CAN_DRIVER */
  284. /* adjust refresh rate depending on SDRAM type, one bank */
  285. reg = memctl->memc_mptpr;
  286. reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
  287. memctl->memc_mptpr = reg;
  288. }
  289. }
  290. udelay (10000);
  291. #ifdef CONFIG_CAN_DRIVER
  292. /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
  293. /* Initialize OR3 / BR3 */
  294. memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
  295. memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
  296. /* Initialize MBMR */
  297. memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
  298. /* Initialize UPMB for CAN: single read */
  299. memctl->memc_mdr = 0xFFFFCC04;
  300. memctl->memc_mcr = 0x0100 | UPMB;
  301. memctl->memc_mdr = 0x0FFFD004;
  302. memctl->memc_mcr = 0x0101 | UPMB;
  303. memctl->memc_mdr = 0x0FFFC000;
  304. memctl->memc_mcr = 0x0102 | UPMB;
  305. memctl->memc_mdr = 0x3FFFC004;
  306. memctl->memc_mcr = 0x0103 | UPMB;
  307. memctl->memc_mdr = 0xFFFFDC07;
  308. memctl->memc_mcr = 0x0104 | UPMB;
  309. /* Initialize UPMB for CAN: single write */
  310. memctl->memc_mdr = 0xFFFCCC04;
  311. memctl->memc_mcr = 0x0118 | UPMB;
  312. memctl->memc_mdr = 0xCFFCDC04;
  313. memctl->memc_mcr = 0x0119 | UPMB;
  314. memctl->memc_mdr = 0x3FFCC000;
  315. memctl->memc_mcr = 0x011A | UPMB;
  316. memctl->memc_mdr = 0xFFFCC004;
  317. memctl->memc_mcr = 0x011B | UPMB;
  318. memctl->memc_mdr = 0xFFFDC405;
  319. memctl->memc_mcr = 0x011C | UPMB;
  320. #endif /* CONFIG_CAN_DRIVER */
  321. #ifdef CONFIG_ISP1362_USB
  322. /* Initialize OR5 / BR5 */
  323. memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
  324. memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
  325. #endif /* CONFIG_ISP1362_USB */
  326. gd->ram_size = size_b0 + size_b1;
  327. return 0;
  328. }
  329. /* ------------------------------------------------------------------------- */
  330. /*
  331. * Check memory range for valid RAM. A simple memory test determines
  332. * the actually available RAM size between addresses `base' and
  333. * `base + maxsize'. Some (not all) hardware errors are detected:
  334. * - short between address lines
  335. * - short between data lines
  336. */
  337. static long int dram_size (long int mamr_value, long int *base, long int maxsize)
  338. {
  339. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  340. volatile memctl8xx_t *memctl = &immap->im_memctl;
  341. memctl->memc_mamr = mamr_value;
  342. return (get_ram_size(base, maxsize));
  343. }
  344. /* ------------------------------------------------------------------------- */
  345. #ifdef CONFIG_MISC_INIT_R
  346. extern void load_sernum_ethaddr(void);
  347. int misc_init_r (void)
  348. {
  349. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  350. volatile memctl8xx_t *memctl = &immap->im_memctl;
  351. load_sernum_ethaddr();
  352. #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
  353. int scy, trlx, flash_or_timing, clk_diff;
  354. scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
  355. if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
  356. trlx = OR_TRLX;
  357. scy *= 2;
  358. } else {
  359. trlx = 0;
  360. }
  361. /*
  362. * We assume that each 10MHz of bus clock require 1-clk SCY
  363. * adjustment.
  364. */
  365. clk_diff = (gd->bus_clk / 1000000) - 50;
  366. /*
  367. * We need proper rounding here. This is what the "+5" and "-5"
  368. * are here for.
  369. */
  370. if (clk_diff >= 0)
  371. scy += (clk_diff + 5) / 10;
  372. else
  373. scy += (clk_diff - 5) / 10;
  374. /*
  375. * For bus frequencies above 50MHz, we want to use relaxed timing
  376. * (OR_TRLX).
  377. */
  378. if (gd->bus_clk >= 50000000)
  379. trlx = OR_TRLX;
  380. else
  381. trlx = 0;
  382. if (trlx)
  383. scy /= 2;
  384. if (scy > 0xf)
  385. scy = 0xf;
  386. if (scy < 1)
  387. scy = 1;
  388. flash_or_timing = (scy << 4) | trlx |
  389. (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
  390. memctl->memc_or0 =
  391. flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
  392. #else
  393. memctl->memc_or0 =
  394. CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
  395. #endif
  396. memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
  397. debug ("## BR0: 0x%08x OR0: 0x%08x\n",
  398. memctl->memc_br0, memctl->memc_or0);
  399. if (flash_info[1].size) {
  400. #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
  401. memctl->memc_or1 = flash_or_timing |
  402. (-flash_info[1].size & 0xFFFF8000);
  403. #else
  404. memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
  405. (-flash_info[1].size & 0xFFFF8000);
  406. #endif
  407. memctl->memc_br1 =
  408. ((CONFIG_SYS_FLASH_BASE +
  409. flash_info[0].
  410. size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
  411. debug ("## BR1: 0x%08x OR1: 0x%08x\n",
  412. memctl->memc_br1, memctl->memc_or1);
  413. } else {
  414. memctl->memc_br1 = 0; /* invalidate bank */
  415. debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
  416. memctl->memc_br1, memctl->memc_or1);
  417. }
  418. # ifdef CONFIG_IDE_LED
  419. /* Configure PA15 as output port */
  420. immap->im_ioport.iop_padir |= 0x0001;
  421. immap->im_ioport.iop_paodr |= 0x0001;
  422. immap->im_ioport.iop_papar &= ~0x0001;
  423. immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
  424. # endif
  425. return (0);
  426. }
  427. #endif /* CONFIG_MISC_INIT_R */
  428. # ifdef CONFIG_IDE_LED
  429. void ide_led (uchar led, uchar status)
  430. {
  431. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  432. /* We have one led for both pcmcia slots */
  433. if (status) { /* led on */
  434. immap->im_ioport.iop_padat |= 0x0001;
  435. } else {
  436. immap->im_ioport.iop_padat &= ~0x0001;
  437. }
  438. }
  439. # endif
  440. #ifdef CONFIG_LCD_INFO
  441. #include <lcd.h>
  442. #include <version.h>
  443. #include <timestamp.h>
  444. void lcd_show_board_info(void)
  445. {
  446. char temp[32];
  447. lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
  448. lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
  449. lcd_printf (" Wolfgang DENK, wd@denx.de\n");
  450. #ifdef CONFIG_LCD_INFO_BELOW_LOGO
  451. lcd_printf ("MPC823 CPU at %s MHz\n",
  452. strmhz(temp, gd->cpu_clk));
  453. lcd_printf (" %ld MB RAM, %ld MB Flash\n",
  454. gd->ram_size >> 20,
  455. gd->bd->bi_flashsize >> 20 );
  456. #else
  457. /* leave one blank line */
  458. lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
  459. strmhz(temp, gd->cpu_clk),
  460. gd->ram_size >> 20,
  461. gd->bd->bi_flashsize >> 20 );
  462. #endif /* CONFIG_LCD_INFO_BELOW_LOGO */
  463. }
  464. #endif /* CONFIG_LCD_INFO */
  465. /*
  466. * Device Tree Support
  467. */
  468. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  469. int fdt_set_node_and_value (void *blob,
  470. char *nodename,
  471. char *regname,
  472. void *var,
  473. int size)
  474. {
  475. int ret = 0;
  476. int nodeoffset = 0;
  477. nodeoffset = fdt_path_offset (blob, nodename);
  478. if (nodeoffset >= 0) {
  479. ret = fdt_setprop (blob, nodeoffset, regname, var,
  480. size);
  481. if (ret < 0) {
  482. printf("ft_blob_update(): "
  483. "cannot set %s/%s property; err: %s\n",
  484. nodename, regname, fdt_strerror (ret));
  485. }
  486. } else {
  487. printf("ft_blob_update(): "
  488. "cannot find %s node err:%s\n",
  489. nodename, fdt_strerror (nodeoffset));
  490. }
  491. return ret;
  492. }
  493. int fdt_del_node_name (void *blob, char *nodename)
  494. {
  495. int ret = 0;
  496. int nodeoffset = 0;
  497. nodeoffset = fdt_path_offset (blob, nodename);
  498. if (nodeoffset >= 0) {
  499. ret = fdt_del_node (blob, nodeoffset);
  500. if (ret < 0) {
  501. printf("%s: cannot delete %s; err: %s\n",
  502. __func__, nodename, fdt_strerror (ret));
  503. }
  504. } else {
  505. printf("%s: cannot find %s node err:%s\n",
  506. __func__, nodename, fdt_strerror (nodeoffset));
  507. }
  508. return ret;
  509. }
  510. int fdt_del_prop_name (void *blob, char *nodename, char *propname)
  511. {
  512. int ret = 0;
  513. int nodeoffset = 0;
  514. nodeoffset = fdt_path_offset (blob, nodename);
  515. if (nodeoffset >= 0) {
  516. ret = fdt_delprop (blob, nodeoffset, propname);
  517. if (ret < 0) {
  518. printf("%s: cannot delete %s %s; err: %s\n",
  519. __func__, nodename, propname,
  520. fdt_strerror (ret));
  521. }
  522. } else {
  523. printf("%s: cannot find %s node err:%s\n",
  524. __func__, nodename, fdt_strerror (nodeoffset));
  525. }
  526. return ret;
  527. }
  528. /*
  529. * update "brg" property in the blob
  530. */
  531. void ft_blob_update (void *blob, bd_t *bd)
  532. {
  533. uchar enetaddr[6];
  534. ulong brg_data = 0;
  535. /* BRG */
  536. brg_data = cpu_to_be32(bd->bi_busfreq);
  537. fdt_set_node_and_value(blob,
  538. "/soc/cpm", "brg-frequency",
  539. &brg_data, sizeof(brg_data));
  540. /* MAC addr */
  541. if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
  542. fdt_set_node_and_value(blob,
  543. "ethernet0", "local-mac-address",
  544. enetaddr, sizeof(u8) * 6);
  545. }
  546. if (hwconfig_arg_cmp("fec", "off")) {
  547. /* no FEC on this plattform, delete DTS nodes */
  548. fdt_del_node_name (blob, "ethernet1");
  549. fdt_del_node_name (blob, "mdio1");
  550. /* also the aliases entries */
  551. fdt_del_prop_name (blob, "/aliases", "ethernet1");
  552. fdt_del_prop_name (blob, "/aliases", "mdio1");
  553. } else {
  554. /* adjust local-mac-address for FEC ethernet */
  555. if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
  556. fdt_set_node_and_value(blob,
  557. "ethernet1", "local-mac-address",
  558. enetaddr, sizeof(u8) * 6);
  559. }
  560. }
  561. }
  562. int ft_board_setup(void *blob, bd_t *bd)
  563. {
  564. ft_cpu_setup(blob, bd);
  565. ft_blob_update(blob, bd);
  566. return 0;
  567. }
  568. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */