evm.c 27 KB

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  1. /*
  2. * (C) Copyright 2013
  3. * Texas Instruments Incorporated, <www.ti.com>
  4. *
  5. * Lokesh Vutla <lokeshvutla@ti.com>
  6. *
  7. * Based on previous work by:
  8. * Aneesh V <aneesh@ti.com>
  9. * Steve Sakoman <steve@sakoman.com>
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <common.h>
  14. #include <palmas.h>
  15. #include <sata.h>
  16. #include <linux/string.h>
  17. #include <asm/gpio.h>
  18. #include <usb.h>
  19. #include <linux/usb/gadget.h>
  20. #include <asm/omap_common.h>
  21. #include <asm/omap_sec_common.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/dra7xx_iodelay.h>
  24. #include <asm/emif.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <asm/arch/mmc_host_def.h>
  27. #include <asm/arch/sata.h>
  28. #include <environment.h>
  29. #include <dwc3-uboot.h>
  30. #include <dwc3-omap-uboot.h>
  31. #include <ti-usb-phy-uboot.h>
  32. #include <miiphy.h>
  33. #include "mux_data.h"
  34. #include "../common/board_detect.h"
  35. #define board_is_dra74x_evm() board_ti_is("5777xCPU")
  36. #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
  37. #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
  38. #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
  39. (strncmp("H", board_ti_get_rev(), 1) <= 0))
  40. #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
  41. (strncmp("C", board_ti_get_rev(), 1) <= 0))
  42. #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
  43. board_ti_get_emif2_size()
  44. #ifdef CONFIG_DRIVER_TI_CPSW
  45. #include <cpsw.h>
  46. #endif
  47. DECLARE_GLOBAL_DATA_PTR;
  48. /* GPIO 7_11 */
  49. #define GPIO_DDR_VTT_EN 203
  50. #define SYSINFO_BOARD_NAME_MAX_LEN 37
  51. const struct omap_sysinfo sysinfo = {
  52. "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  53. };
  54. static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  55. .sdram_config_init = 0x61851ab2,
  56. .sdram_config = 0x61851ab2,
  57. .sdram_config2 = 0x08000000,
  58. .ref_ctrl = 0x000040F1,
  59. .ref_ctrl_final = 0x00001035,
  60. .sdram_tim1 = 0xCCCF36B3,
  61. .sdram_tim2 = 0x308F7FDA,
  62. .sdram_tim3 = 0x427F88A8,
  63. .read_idle_ctrl = 0x00050000,
  64. .zq_config = 0x0007190B,
  65. .temp_alert_config = 0x00000000,
  66. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  67. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  68. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  69. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  70. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  71. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  72. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  73. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  74. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  75. .emif_rd_wr_lvl_ctl = 0x00000000,
  76. .emif_rd_wr_exec_thresh = 0x00000305
  77. };
  78. static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  79. .sdram_config_init = 0x61851B32,
  80. .sdram_config = 0x61851B32,
  81. .sdram_config2 = 0x08000000,
  82. .ref_ctrl = 0x000040F1,
  83. .ref_ctrl_final = 0x00001035,
  84. .sdram_tim1 = 0xCCCF36B3,
  85. .sdram_tim2 = 0x308F7FDA,
  86. .sdram_tim3 = 0x427F88A8,
  87. .read_idle_ctrl = 0x00050000,
  88. .zq_config = 0x0007190B,
  89. .temp_alert_config = 0x00000000,
  90. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  91. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  92. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  93. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  94. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  95. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  96. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  97. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  98. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  99. .emif_rd_wr_lvl_ctl = 0x00000000,
  100. .emif_rd_wr_exec_thresh = 0x00000305
  101. };
  102. static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
  103. .sdram_config_init = 0x61862B32,
  104. .sdram_config = 0x61862B32,
  105. .sdram_config2 = 0x08000000,
  106. .ref_ctrl = 0x0000514C,
  107. .ref_ctrl_final = 0x0000144A,
  108. .sdram_tim1 = 0xD113781C,
  109. .sdram_tim2 = 0x30717FE3,
  110. .sdram_tim3 = 0x409F86A8,
  111. .read_idle_ctrl = 0x00050000,
  112. .zq_config = 0x5007190B,
  113. .temp_alert_config = 0x00000000,
  114. .emif_ddr_phy_ctlr_1_init = 0x0024400D,
  115. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  116. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  117. .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
  118. .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
  119. .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
  120. .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
  121. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  122. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  123. .emif_rd_wr_lvl_ctl = 0x00000000,
  124. .emif_rd_wr_exec_thresh = 0x00000305
  125. };
  126. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
  127. .sdram_config_init = 0x61862BB2,
  128. .sdram_config = 0x61862BB2,
  129. .sdram_config2 = 0x00000000,
  130. .ref_ctrl = 0x0000514D,
  131. .ref_ctrl_final = 0x0000144A,
  132. .sdram_tim1 = 0xD1137824,
  133. .sdram_tim2 = 0x30B37FE3,
  134. .sdram_tim3 = 0x409F8AD8,
  135. .read_idle_ctrl = 0x00050000,
  136. .zq_config = 0x5007190B,
  137. .temp_alert_config = 0x00000000,
  138. .emif_ddr_phy_ctlr_1_init = 0x0824400E,
  139. .emif_ddr_phy_ctlr_1 = 0x0E24400E,
  140. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  141. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  142. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  143. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  144. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  145. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  146. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  147. .emif_rd_wr_lvl_ctl = 0x00000000,
  148. .emif_rd_wr_exec_thresh = 0x00000305
  149. };
  150. const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
  151. .sdram_config_init = 0x61851ab2,
  152. .sdram_config = 0x61851ab2,
  153. .sdram_config2 = 0x08000000,
  154. .ref_ctrl = 0x000040F1,
  155. .ref_ctrl_final = 0x00001035,
  156. .sdram_tim1 = 0xCCCF36B3,
  157. .sdram_tim2 = 0x30BF7FDA,
  158. .sdram_tim3 = 0x427F8BA8,
  159. .read_idle_ctrl = 0x00050000,
  160. .zq_config = 0x0007190B,
  161. .temp_alert_config = 0x00000000,
  162. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  163. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  164. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  165. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  166. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  167. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  168. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  169. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  170. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  171. .emif_rd_wr_lvl_ctl = 0x00000000,
  172. .emif_rd_wr_exec_thresh = 0x00000305
  173. };
  174. const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
  175. .sdram_config_init = 0x61851B32,
  176. .sdram_config = 0x61851B32,
  177. .sdram_config2 = 0x08000000,
  178. .ref_ctrl = 0x000040F1,
  179. .ref_ctrl_final = 0x00001035,
  180. .sdram_tim1 = 0xCCCF36B3,
  181. .sdram_tim2 = 0x308F7FDA,
  182. .sdram_tim3 = 0x427F88A8,
  183. .read_idle_ctrl = 0x00050000,
  184. .zq_config = 0x0007190B,
  185. .temp_alert_config = 0x00000000,
  186. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  187. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  188. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  189. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  190. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  191. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  192. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  193. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  194. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  195. .emif_rd_wr_lvl_ctl = 0x00000000,
  196. .emif_rd_wr_exec_thresh = 0x00000305
  197. };
  198. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  199. {
  200. u64 ram_size;
  201. ram_size = board_ti_get_emif_size();
  202. switch (omap_revision()) {
  203. case DRA752_ES1_0:
  204. case DRA752_ES1_1:
  205. case DRA752_ES2_0:
  206. switch (emif_nr) {
  207. case 1:
  208. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  209. *regs = &emif1_ddr3_532_mhz_1cs_2G;
  210. else
  211. *regs = &emif1_ddr3_532_mhz_1cs;
  212. break;
  213. case 2:
  214. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  215. *regs = &emif2_ddr3_532_mhz_1cs_2G;
  216. else
  217. *regs = &emif2_ddr3_532_mhz_1cs;
  218. break;
  219. }
  220. break;
  221. case DRA722_ES1_0:
  222. case DRA722_ES2_0:
  223. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  224. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
  225. else
  226. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
  227. break;
  228. default:
  229. *regs = &emif1_ddr3_532_mhz_1cs;
  230. }
  231. }
  232. static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
  233. .dmm_lisa_map_0 = 0x0,
  234. .dmm_lisa_map_1 = 0x80640300,
  235. .dmm_lisa_map_2 = 0xC0500220,
  236. .dmm_lisa_map_3 = 0xFF020100,
  237. .is_ma_present = 0x1
  238. };
  239. static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
  240. .dmm_lisa_map_0 = 0x0,
  241. .dmm_lisa_map_1 = 0x0,
  242. .dmm_lisa_map_2 = 0x80600100,
  243. .dmm_lisa_map_3 = 0xFF020100,
  244. .is_ma_present = 0x1
  245. };
  246. const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
  247. .dmm_lisa_map_0 = 0x0,
  248. .dmm_lisa_map_1 = 0x0,
  249. .dmm_lisa_map_2 = 0x80740300,
  250. .dmm_lisa_map_3 = 0xFF020100,
  251. .is_ma_present = 0x1
  252. };
  253. /*
  254. * DRA722 EVM EMIF1 2GB CONFIGURATION
  255. * EMIF1 4 devices of 512Mb x 8 Micron
  256. */
  257. const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
  258. .dmm_lisa_map_0 = 0x0,
  259. .dmm_lisa_map_1 = 0x0,
  260. .dmm_lisa_map_2 = 0x80700100,
  261. .dmm_lisa_map_3 = 0xFF020100,
  262. .is_ma_present = 0x1
  263. };
  264. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  265. {
  266. u64 ram_size;
  267. ram_size = board_ti_get_emif_size();
  268. switch (omap_revision()) {
  269. case DRA752_ES1_0:
  270. case DRA752_ES1_1:
  271. case DRA752_ES2_0:
  272. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  273. *dmm_lisa_regs = &lisa_map_dra7_2GB;
  274. else
  275. *dmm_lisa_regs = &lisa_map_dra7_1536MB;
  276. break;
  277. case DRA722_ES1_0:
  278. case DRA722_ES2_0:
  279. default:
  280. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  281. *dmm_lisa_regs = &lisa_map_2G_x_2;
  282. else
  283. *dmm_lisa_regs = &lisa_map_2G_x_4;
  284. break;
  285. }
  286. }
  287. struct vcores_data dra752_volts = {
  288. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  289. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  290. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  291. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  292. .mpu.pmic = &tps659038,
  293. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  294. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  295. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  296. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  297. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  298. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  299. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  300. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  301. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  302. .eve.pmic = &tps659038,
  303. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  304. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  305. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  306. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  307. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  308. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  309. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  310. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  311. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  312. .gpu.pmic = &tps659038,
  313. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  314. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  315. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  316. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  317. .core.addr = TPS659038_REG_ADDR_SMPS7,
  318. .core.pmic = &tps659038,
  319. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  320. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  321. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  322. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  323. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  324. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  325. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  326. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  327. .iva.pmic = &tps659038,
  328. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  329. };
  330. struct vcores_data dra722_volts = {
  331. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  332. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  333. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  334. .mpu.addr = TPS65917_REG_ADDR_SMPS1,
  335. .mpu.pmic = &tps659038,
  336. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  337. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  338. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  339. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  340. .core.addr = TPS65917_REG_ADDR_SMPS2,
  341. .core.pmic = &tps659038,
  342. /*
  343. * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
  344. * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
  345. */
  346. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  347. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  348. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  349. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  350. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  351. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  352. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  353. .gpu.addr = TPS65917_REG_ADDR_SMPS3,
  354. .gpu.pmic = &tps659038,
  355. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  356. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  357. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  358. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  359. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  360. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  361. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  362. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  363. .eve.addr = TPS65917_REG_ADDR_SMPS3,
  364. .eve.pmic = &tps659038,
  365. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  366. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  367. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  368. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  369. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  370. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  371. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  372. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  373. .iva.addr = TPS65917_REG_ADDR_SMPS3,
  374. .iva.pmic = &tps659038,
  375. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  376. };
  377. struct vcores_data dra718_volts = {
  378. /*
  379. * In the case of dra71x GPU MPU and CORE
  380. * are all powered up by BUCK0 of LP873X PMIC
  381. */
  382. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  383. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  384. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  385. .mpu.addr = LP873X_REG_ADDR_BUCK0,
  386. .mpu.pmic = &lp8733,
  387. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  388. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  389. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  390. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  391. .core.addr = LP873X_REG_ADDR_BUCK0,
  392. .core.pmic = &lp8733,
  393. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  394. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  395. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  396. .gpu.addr = LP873X_REG_ADDR_BUCK0,
  397. .gpu.pmic = &lp8733,
  398. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  399. /*
  400. * The DSPEVE and IVA rails are grouped on DRA71x-evm
  401. * and are powered by BUCK1 of LP873X PMIC
  402. */
  403. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  404. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  405. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  406. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  407. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  408. .eve.addr = LP873X_REG_ADDR_BUCK1,
  409. .eve.pmic = &lp8733,
  410. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  411. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  412. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  413. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  414. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  415. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  416. .iva.addr = LP873X_REG_ADDR_BUCK1,
  417. .iva.pmic = &lp8733,
  418. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  419. };
  420. int get_voltrail_opp(int rail_offset)
  421. {
  422. int opp;
  423. switch (rail_offset) {
  424. case VOLT_MPU:
  425. opp = DRA7_MPU_OPP;
  426. /* DRA71x supports only OPP_NOM for MPU */
  427. if (board_is_dra71x_evm())
  428. opp = OPP_NOM;
  429. break;
  430. case VOLT_CORE:
  431. opp = DRA7_CORE_OPP;
  432. /* DRA71x supports only OPP_NOM for CORE */
  433. if (board_is_dra71x_evm())
  434. opp = OPP_NOM;
  435. break;
  436. case VOLT_GPU:
  437. opp = DRA7_GPU_OPP;
  438. /* DRA71x supports only OPP_NOM for GPU */
  439. if (board_is_dra71x_evm())
  440. opp = OPP_NOM;
  441. break;
  442. case VOLT_EVE:
  443. opp = DRA7_DSPEVE_OPP;
  444. /*
  445. * DRA71x does not support OPP_OD for EVE.
  446. * If OPP_OD is selected by menuconfig, fallback
  447. * to OPP_NOM.
  448. */
  449. if (board_is_dra71x_evm() && opp == OPP_OD)
  450. opp = OPP_NOM;
  451. break;
  452. case VOLT_IVA:
  453. opp = DRA7_IVA_OPP;
  454. /*
  455. * DRA71x does not support OPP_OD for IVA.
  456. * If OPP_OD is selected by menuconfig, fallback
  457. * to OPP_NOM.
  458. */
  459. if (board_is_dra71x_evm() && opp == OPP_OD)
  460. opp = OPP_NOM;
  461. break;
  462. default:
  463. opp = OPP_NOM;
  464. }
  465. return opp;
  466. }
  467. /**
  468. * @brief board_init
  469. *
  470. * @return 0
  471. */
  472. int board_init(void)
  473. {
  474. gpmc_init();
  475. gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  476. return 0;
  477. }
  478. int dram_init_banksize(void)
  479. {
  480. u64 ram_size;
  481. ram_size = board_ti_get_emif_size();
  482. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  483. gd->bd->bi_dram[0].size = get_effective_memsize();
  484. if (ram_size > CONFIG_MAX_MEM_MAPPED) {
  485. gd->bd->bi_dram[1].start = 0x200000000;
  486. gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
  487. }
  488. return 0;
  489. }
  490. int board_late_init(void)
  491. {
  492. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  493. char *name = "unknown";
  494. if (is_dra72x()) {
  495. if (board_is_dra72x_revc_or_later())
  496. name = "dra72x-revc";
  497. else if (board_is_dra71x_evm())
  498. name = "dra71x";
  499. else
  500. name = "dra72x";
  501. } else {
  502. name = "dra7xx";
  503. }
  504. set_board_info_env(name);
  505. /*
  506. * Default FIT boot on HS devices. Non FIT images are not allowed
  507. * on HS devices.
  508. */
  509. if (get_device_type() == HS_DEVICE)
  510. setenv("boot_fit", "1");
  511. omap_die_id_serial();
  512. omap_set_fastboot_vars();
  513. #endif
  514. return 0;
  515. }
  516. #ifdef CONFIG_SPL_BUILD
  517. void do_board_detect(void)
  518. {
  519. int rc;
  520. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  521. CONFIG_EEPROM_CHIP_ADDRESS);
  522. if (rc)
  523. printf("ti_i2c_eeprom_init failed %d\n", rc);
  524. }
  525. #else
  526. void do_board_detect(void)
  527. {
  528. char *bname = NULL;
  529. int rc;
  530. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  531. CONFIG_EEPROM_CHIP_ADDRESS);
  532. if (rc)
  533. printf("ti_i2c_eeprom_init failed %d\n", rc);
  534. if (board_is_dra74x_evm()) {
  535. bname = "DRA74x EVM";
  536. } else if (board_is_dra72x_evm()) {
  537. bname = "DRA72x EVM";
  538. } else if (board_is_dra71x_evm()) {
  539. bname = "DRA71x EVM";
  540. } else {
  541. /* If EEPROM is not populated */
  542. if (is_dra72x())
  543. bname = "DRA72x EVM";
  544. else
  545. bname = "DRA74x EVM";
  546. }
  547. if (bname)
  548. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  549. "Board: %s REV %s\n", bname, board_ti_get_rev());
  550. }
  551. #endif /* CONFIG_SPL_BUILD */
  552. void vcores_init(void)
  553. {
  554. if (board_is_dra74x_evm()) {
  555. *omap_vcores = &dra752_volts;
  556. } else if (board_is_dra72x_evm()) {
  557. *omap_vcores = &dra722_volts;
  558. } else if (board_is_dra71x_evm()) {
  559. *omap_vcores = &dra718_volts;
  560. } else {
  561. /* If EEPROM is not populated */
  562. if (is_dra72x())
  563. *omap_vcores = &dra722_volts;
  564. else
  565. *omap_vcores = &dra752_volts;
  566. }
  567. }
  568. void set_muxconf_regs(void)
  569. {
  570. do_set_mux32((*ctrl)->control_padconf_core_base,
  571. early_padconf, ARRAY_SIZE(early_padconf));
  572. }
  573. #ifdef CONFIG_IODELAY_RECALIBRATION
  574. void recalibrate_iodelay(void)
  575. {
  576. struct pad_conf_entry const *pads, *delta_pads = NULL;
  577. struct iodelay_cfg_entry const *iodelay;
  578. int npads, niodelays, delta_npads = 0;
  579. int ret;
  580. switch (omap_revision()) {
  581. case DRA722_ES1_0:
  582. case DRA722_ES2_0:
  583. pads = dra72x_core_padconf_array_common;
  584. npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
  585. if (board_is_dra71x_evm()) {
  586. pads = dra71x_core_padconf_array;
  587. npads = ARRAY_SIZE(dra71x_core_padconf_array);
  588. iodelay = dra71_iodelay_cfg_array;
  589. niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
  590. } else if (board_is_dra72x_revc_or_later()) {
  591. delta_pads = dra72x_rgmii_padconf_array_revc;
  592. delta_npads =
  593. ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
  594. iodelay = dra72_iodelay_cfg_array_revc;
  595. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
  596. } else {
  597. delta_pads = dra72x_rgmii_padconf_array_revb;
  598. delta_npads =
  599. ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
  600. iodelay = dra72_iodelay_cfg_array_revb;
  601. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
  602. }
  603. break;
  604. case DRA752_ES1_0:
  605. case DRA752_ES1_1:
  606. pads = dra74x_core_padconf_array;
  607. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  608. iodelay = dra742_es1_1_iodelay_cfg_array;
  609. niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
  610. break;
  611. default:
  612. case DRA752_ES2_0:
  613. pads = dra74x_core_padconf_array;
  614. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  615. iodelay = dra742_es2_0_iodelay_cfg_array;
  616. niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
  617. /* Setup port1 and port2 for rgmii with 'no-id' mode */
  618. clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
  619. RGMII1_ID_MODE_N_MASK);
  620. break;
  621. }
  622. /* Setup I/O isolation */
  623. ret = __recalibrate_iodelay_start();
  624. if (ret)
  625. goto err;
  626. /* Do the muxing here */
  627. do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
  628. /* Now do the weird minor deltas that should be safe */
  629. if (delta_npads)
  630. do_set_mux32((*ctrl)->control_padconf_core_base,
  631. delta_pads, delta_npads);
  632. /* Setup IOdelay configuration */
  633. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
  634. err:
  635. /* Closeup.. remove isolation */
  636. __recalibrate_iodelay_end(ret);
  637. }
  638. #endif
  639. #if defined(CONFIG_MMC)
  640. int board_mmc_init(bd_t *bis)
  641. {
  642. omap_mmc_init(0, 0, 0, -1, -1);
  643. omap_mmc_init(1, 0, 0, -1, -1);
  644. return 0;
  645. }
  646. #endif
  647. #ifdef CONFIG_USB_DWC3
  648. static struct dwc3_device usb_otg_ss1 = {
  649. .maximum_speed = USB_SPEED_SUPER,
  650. .base = DRA7_USB_OTG_SS1_BASE,
  651. .tx_fifo_resize = false,
  652. .index = 0,
  653. };
  654. static struct dwc3_omap_device usb_otg_ss1_glue = {
  655. .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
  656. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  657. .index = 0,
  658. };
  659. static struct ti_usb_phy_device usb_phy1_device = {
  660. .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
  661. .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
  662. .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
  663. .index = 0,
  664. };
  665. static struct dwc3_device usb_otg_ss2 = {
  666. .maximum_speed = USB_SPEED_SUPER,
  667. .base = DRA7_USB_OTG_SS2_BASE,
  668. .tx_fifo_resize = false,
  669. .index = 1,
  670. };
  671. static struct dwc3_omap_device usb_otg_ss2_glue = {
  672. .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
  673. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  674. .index = 1,
  675. };
  676. static struct ti_usb_phy_device usb_phy2_device = {
  677. .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
  678. .index = 1,
  679. };
  680. int omap_xhci_board_usb_init(int index, enum usb_init_type init)
  681. {
  682. enable_usb_clocks(index);
  683. switch (index) {
  684. case 0:
  685. if (init == USB_INIT_DEVICE) {
  686. usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
  687. usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  688. } else {
  689. usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
  690. usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
  691. }
  692. ti_usb_phy_uboot_init(&usb_phy1_device);
  693. dwc3_omap_uboot_init(&usb_otg_ss1_glue);
  694. dwc3_uboot_init(&usb_otg_ss1);
  695. break;
  696. case 1:
  697. if (init == USB_INIT_DEVICE) {
  698. usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
  699. usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  700. } else {
  701. usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
  702. usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
  703. }
  704. ti_usb_phy_uboot_init(&usb_phy2_device);
  705. dwc3_omap_uboot_init(&usb_otg_ss2_glue);
  706. dwc3_uboot_init(&usb_otg_ss2);
  707. break;
  708. default:
  709. printf("Invalid Controller Index\n");
  710. }
  711. return 0;
  712. }
  713. int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
  714. {
  715. switch (index) {
  716. case 0:
  717. case 1:
  718. ti_usb_phy_uboot_exit(index);
  719. dwc3_uboot_exit(index);
  720. dwc3_omap_uboot_exit(index);
  721. break;
  722. default:
  723. printf("Invalid Controller Index\n");
  724. }
  725. disable_usb_clocks(index);
  726. return 0;
  727. }
  728. int usb_gadget_handle_interrupts(int index)
  729. {
  730. u32 status;
  731. status = dwc3_omap_uboot_interrupt_status(index);
  732. if (status)
  733. dwc3_uboot_handle_interrupt(index);
  734. return 0;
  735. }
  736. #endif
  737. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  738. int spl_start_uboot(void)
  739. {
  740. /* break into full u-boot on 'c' */
  741. if (serial_tstc() && serial_getc() == 'c')
  742. return 1;
  743. #ifdef CONFIG_SPL_ENV_SUPPORT
  744. env_init();
  745. env_relocate_spec();
  746. if (getenv_yesno("boot_os") != 1)
  747. return 1;
  748. #endif
  749. return 0;
  750. }
  751. #endif
  752. #ifdef CONFIG_DRIVER_TI_CPSW
  753. extern u32 *const omap_si_rev;
  754. static void cpsw_control(int enabled)
  755. {
  756. /* VTP can be added here */
  757. return;
  758. }
  759. static struct cpsw_slave_data cpsw_slaves[] = {
  760. {
  761. .slave_reg_ofs = 0x208,
  762. .sliver_reg_ofs = 0xd80,
  763. .phy_addr = 2,
  764. },
  765. {
  766. .slave_reg_ofs = 0x308,
  767. .sliver_reg_ofs = 0xdc0,
  768. .phy_addr = 3,
  769. },
  770. };
  771. static struct cpsw_platform_data cpsw_data = {
  772. .mdio_base = CPSW_MDIO_BASE,
  773. .cpsw_base = CPSW_BASE,
  774. .mdio_div = 0xff,
  775. .channels = 8,
  776. .cpdma_reg_ofs = 0x800,
  777. .slaves = 2,
  778. .slave_data = cpsw_slaves,
  779. .ale_reg_ofs = 0xd00,
  780. .ale_entries = 1024,
  781. .host_port_reg_ofs = 0x108,
  782. .hw_stats_reg_ofs = 0x900,
  783. .bd_ram_ofs = 0x2000,
  784. .mac_control = (1 << 5),
  785. .control = cpsw_control,
  786. .host_port_num = 0,
  787. .version = CPSW_CTRL_VERSION_2,
  788. };
  789. int board_eth_init(bd_t *bis)
  790. {
  791. int ret;
  792. uint8_t mac_addr[6];
  793. uint32_t mac_hi, mac_lo;
  794. uint32_t ctrl_val;
  795. /* try reading mac address from efuse */
  796. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  797. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  798. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  799. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  800. mac_addr[2] = mac_hi & 0xFF;
  801. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  802. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  803. mac_addr[5] = mac_lo & 0xFF;
  804. if (!getenv("ethaddr")) {
  805. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  806. if (is_valid_ethaddr(mac_addr))
  807. eth_setenv_enetaddr("ethaddr", mac_addr);
  808. }
  809. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  810. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  811. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  812. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  813. mac_addr[2] = mac_hi & 0xFF;
  814. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  815. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  816. mac_addr[5] = mac_lo & 0xFF;
  817. if (!getenv("eth1addr")) {
  818. if (is_valid_ethaddr(mac_addr))
  819. eth_setenv_enetaddr("eth1addr", mac_addr);
  820. }
  821. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  822. ctrl_val |= 0x22;
  823. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  824. if (*omap_si_rev == DRA722_ES1_0)
  825. cpsw_data.active_slave = 1;
  826. if (board_is_dra72x_revc_or_later()) {
  827. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  828. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  829. }
  830. ret = cpsw_register(&cpsw_data);
  831. if (ret < 0)
  832. printf("Error %d registering CPSW switch\n", ret);
  833. return ret;
  834. }
  835. #endif
  836. #ifdef CONFIG_BOARD_EARLY_INIT_F
  837. /* VTT regulator enable */
  838. static inline void vtt_regulator_enable(void)
  839. {
  840. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  841. return;
  842. /* Do not enable VTT for DRA722 */
  843. if (is_dra72x())
  844. return;
  845. /*
  846. * EVM Rev G and later use gpio7_11 for DDR3 termination.
  847. * This is safe enough to do on older revs.
  848. */
  849. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  850. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  851. }
  852. int board_early_init_f(void)
  853. {
  854. vtt_regulator_enable();
  855. return 0;
  856. }
  857. #endif
  858. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  859. int ft_board_setup(void *blob, bd_t *bd)
  860. {
  861. ft_cpu_setup(blob, bd);
  862. return 0;
  863. }
  864. #endif
  865. #ifdef CONFIG_SPL_LOAD_FIT
  866. int board_fit_config_name_match(const char *name)
  867. {
  868. if (is_dra72x()) {
  869. if (board_is_dra71x_evm()) {
  870. if (!strcmp(name, "dra71-evm"))
  871. return 0;
  872. }else if(board_is_dra72x_revc_or_later()) {
  873. if (!strcmp(name, "dra72-evm-revc"))
  874. return 0;
  875. } else if (!strcmp(name, "dra72-evm")) {
  876. return 0;
  877. }
  878. } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
  879. return 0;
  880. }
  881. return -1;
  882. }
  883. #endif
  884. #ifdef CONFIG_TI_SECURE_DEVICE
  885. void board_fit_image_post_process(void **p_image, size_t *p_size)
  886. {
  887. secure_boot_verify_image(p_image, p_size);
  888. }
  889. void board_tee_image_process(ulong tee_image, size_t tee_size)
  890. {
  891. secure_tee_install((u32)tee_image);
  892. }
  893. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  894. #endif