8xx_immap.h 11 KB

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  1. /*
  2. * MPC8xx Internal Memory Map
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * The I/O on the MPC860 is comprised of blocks of special registers
  6. * and the dual port ram for the Communication Processor Module.
  7. * Within this space are functional units such as the SIU, memory
  8. * controller, system timers, and other control functions. It is
  9. * a combination that I found difficult to separate into logical
  10. * functional files.....but anyone else is welcome to try. -- Dan
  11. */
  12. #ifndef __IMMAP_8XX__
  13. #define __IMMAP_8XX__
  14. /* System configuration registers.
  15. */
  16. typedef struct sys_conf {
  17. uint sc_siumcr;
  18. uint sc_sypcr;
  19. uint sc_swt;
  20. char res1[2];
  21. ushort sc_swsr;
  22. uint sc_sipend;
  23. uint sc_simask;
  24. uint sc_siel;
  25. uint sc_sivec;
  26. uint sc_tesr;
  27. char res2[0xc];
  28. uint sc_sdcr;
  29. char res3[0x4c];
  30. } sysconf8xx_t;
  31. /* PCMCIA configuration registers.
  32. */
  33. typedef struct pcmcia_conf {
  34. uint pcmc_pbr0;
  35. uint pcmc_por0;
  36. uint pcmc_pbr1;
  37. uint pcmc_por1;
  38. uint pcmc_pbr2;
  39. uint pcmc_por2;
  40. uint pcmc_pbr3;
  41. uint pcmc_por3;
  42. uint pcmc_pbr4;
  43. uint pcmc_por4;
  44. uint pcmc_pbr5;
  45. uint pcmc_por5;
  46. uint pcmc_pbr6;
  47. uint pcmc_por6;
  48. uint pcmc_pbr7;
  49. uint pcmc_por7;
  50. char res1[0x20];
  51. uint pcmc_pgcra;
  52. uint pcmc_pgcrb;
  53. uint pcmc_pscr;
  54. char res2[4];
  55. uint pcmc_pipr;
  56. char res3[4];
  57. uint pcmc_per;
  58. char res4[4];
  59. } pcmconf8xx_t;
  60. /* Memory controller registers.
  61. */
  62. typedef struct mem_ctlr {
  63. uint memc_br0;
  64. uint memc_or0;
  65. uint memc_br1;
  66. uint memc_or1;
  67. uint memc_br2;
  68. uint memc_or2;
  69. uint memc_br3;
  70. uint memc_or3;
  71. uint memc_br4;
  72. uint memc_or4;
  73. uint memc_br5;
  74. uint memc_or5;
  75. uint memc_br6;
  76. uint memc_or6;
  77. uint memc_br7;
  78. uint memc_or7;
  79. char res1[0x24];
  80. uint memc_mar;
  81. uint memc_mcr;
  82. char res2[4];
  83. uint memc_mamr;
  84. uint memc_mbmr;
  85. ushort memc_mstat;
  86. ushort memc_mptpr;
  87. uint memc_mdr;
  88. char res3[0x80];
  89. } memctl8xx_t;
  90. /* System Integration Timers.
  91. */
  92. typedef struct sys_int_timers {
  93. ushort sit_tbscr;
  94. char res0[0x02];
  95. uint sit_tbreff0;
  96. uint sit_tbreff1;
  97. char res1[0x14];
  98. ushort sit_rtcsc;
  99. char res2[0x02];
  100. uint sit_rtc;
  101. uint sit_rtsec;
  102. uint sit_rtcal;
  103. char res3[0x10];
  104. ushort sit_piscr;
  105. char res4[2];
  106. uint sit_pitc;
  107. uint sit_pitr;
  108. char res5[0x34];
  109. } sit8xx_t;
  110. #define TBSCR_TBIRQ_MASK ((ushort)0xff00)
  111. #define TBSCR_REFA ((ushort)0x0080)
  112. #define TBSCR_REFB ((ushort)0x0040)
  113. #define TBSCR_REFAE ((ushort)0x0008)
  114. #define TBSCR_REFBE ((ushort)0x0004)
  115. #define TBSCR_TBF ((ushort)0x0002)
  116. #define TBSCR_TBE ((ushort)0x0001)
  117. #define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
  118. #define RTCSC_SEC ((ushort)0x0080)
  119. #define RTCSC_ALR ((ushort)0x0040)
  120. #define RTCSC_38K ((ushort)0x0010)
  121. #define RTCSC_SIE ((ushort)0x0008)
  122. #define RTCSC_ALE ((ushort)0x0004)
  123. #define RTCSC_RTF ((ushort)0x0002)
  124. #define RTCSC_RTE ((ushort)0x0001)
  125. #define PISCR_PIRQ_MASK ((ushort)0xff00)
  126. #define PISCR_PS ((ushort)0x0080)
  127. #define PISCR_PIE ((ushort)0x0004)
  128. #define PISCR_PTF ((ushort)0x0002)
  129. #define PISCR_PTE ((ushort)0x0001)
  130. /* Clocks and Reset.
  131. */
  132. typedef struct clk_and_reset {
  133. uint car_sccr;
  134. uint car_plprcr;
  135. uint car_rsr;
  136. char res[0x74]; /* Reserved area */
  137. } car8xx_t;
  138. /* System Integration Timers keys.
  139. */
  140. typedef struct sitk {
  141. uint sitk_tbscrk;
  142. uint sitk_tbreff0k;
  143. uint sitk_tbreff1k;
  144. uint sitk_tbk;
  145. char res1[0x10];
  146. uint sitk_rtcsck;
  147. uint sitk_rtck;
  148. uint sitk_rtseck;
  149. uint sitk_rtcalk;
  150. char res2[0x10];
  151. uint sitk_piscrk;
  152. uint sitk_pitck;
  153. char res3[0x38];
  154. } sitk8xx_t;
  155. /* Clocks and reset keys.
  156. */
  157. typedef struct cark {
  158. uint cark_sccrk;
  159. uint cark_plprcrk;
  160. uint cark_rsrk;
  161. char res[0x474];
  162. } cark8xx_t;
  163. /* The key to unlock registers maintained by keep-alive power.
  164. */
  165. #define KAPWR_KEY ((unsigned int)0x55ccaa33)
  166. /* Video interface. MPC823 Only.
  167. */
  168. typedef struct vid823 {
  169. ushort vid_vccr;
  170. ushort res1;
  171. u_char vid_vsr;
  172. u_char res2;
  173. u_char vid_vcmr;
  174. u_char res3;
  175. uint vid_vbcb;
  176. uint res4;
  177. uint vid_vfcr0;
  178. uint vid_vfaa0;
  179. uint vid_vfba0;
  180. uint vid_vfcr1;
  181. uint vid_vfaa1;
  182. uint vid_vfba1;
  183. u_char res5[0x18];
  184. } vid823_t;
  185. /* LCD interface. 823 Only.
  186. */
  187. typedef struct lcd {
  188. uint lcd_lccr;
  189. uint lcd_lchcr;
  190. uint lcd_lcvcr;
  191. char res1[4];
  192. uint lcd_lcfaa;
  193. uint lcd_lcfba;
  194. char lcd_lcsr;
  195. char res2[0x7];
  196. } lcd823_t;
  197. /* I2C
  198. */
  199. typedef struct i2c {
  200. u_char i2c_i2mod;
  201. char res1[3];
  202. u_char i2c_i2add;
  203. char res2[3];
  204. u_char i2c_i2brg;
  205. char res3[3];
  206. u_char i2c_i2com;
  207. char res4[3];
  208. u_char i2c_i2cer;
  209. char res5[3];
  210. u_char i2c_i2cmr;
  211. char res6[0x8b];
  212. } i2c8xx_t;
  213. /* DMA control/status registers.
  214. */
  215. typedef struct sdma_csr {
  216. char res1[4];
  217. uint sdma_sdar;
  218. u_char sdma_sdsr;
  219. char res3[3];
  220. u_char sdma_sdmr;
  221. char res4[3];
  222. u_char sdma_idsr1;
  223. char res5[3];
  224. u_char sdma_idmr1;
  225. char res6[3];
  226. u_char sdma_idsr2;
  227. char res7[3];
  228. u_char sdma_idmr2;
  229. char res8[0x13];
  230. } sdma8xx_t;
  231. /* Communication Processor Module Interrupt Controller.
  232. */
  233. typedef struct cpm_ic {
  234. ushort cpic_civr;
  235. char res[0xe];
  236. uint cpic_cicr;
  237. uint cpic_cipr;
  238. uint cpic_cimr;
  239. uint cpic_cisr;
  240. } cpic8xx_t;
  241. /* Input/Output Port control/status registers.
  242. */
  243. typedef struct io_port {
  244. ushort iop_padir;
  245. ushort iop_papar;
  246. ushort iop_paodr;
  247. ushort iop_padat;
  248. char res1[8];
  249. ushort iop_pcdir;
  250. ushort iop_pcpar;
  251. ushort iop_pcso;
  252. ushort iop_pcdat;
  253. ushort iop_pcint;
  254. char res2[6];
  255. ushort iop_pddir;
  256. ushort iop_pdpar;
  257. char res3[2];
  258. ushort iop_pddat;
  259. uint utmode;
  260. char res4[4];
  261. } iop8xx_t;
  262. /* Communication Processor Module Timers
  263. */
  264. typedef struct cpm_timers {
  265. ushort cpmt_tgcr;
  266. char res1[0xe];
  267. ushort cpmt_tmr1;
  268. ushort cpmt_tmr2;
  269. ushort cpmt_trr1;
  270. ushort cpmt_trr2;
  271. ushort cpmt_tcr1;
  272. ushort cpmt_tcr2;
  273. ushort cpmt_tcn1;
  274. ushort cpmt_tcn2;
  275. ushort cpmt_tmr3;
  276. ushort cpmt_tmr4;
  277. ushort cpmt_trr3;
  278. ushort cpmt_trr4;
  279. ushort cpmt_tcr3;
  280. ushort cpmt_tcr4;
  281. ushort cpmt_tcn3;
  282. ushort cpmt_tcn4;
  283. ushort cpmt_ter1;
  284. ushort cpmt_ter2;
  285. ushort cpmt_ter3;
  286. ushort cpmt_ter4;
  287. char res2[8];
  288. } cpmtimer8xx_t;
  289. /* Finally, the Communication Processor stuff.....
  290. */
  291. typedef struct scc { /* Serial communication channels */
  292. uint scc_gsmrl;
  293. uint scc_gsmrh;
  294. ushort scc_psmr;
  295. char res1[2];
  296. ushort scc_todr;
  297. ushort scc_dsr;
  298. ushort scc_scce;
  299. char res2[2];
  300. ushort scc_sccm;
  301. char res3;
  302. u_char scc_sccs;
  303. char res4[8];
  304. } scc_t;
  305. typedef struct smc { /* Serial management channels */
  306. char res1[2];
  307. ushort smc_smcmr;
  308. char res2[2];
  309. u_char smc_smce;
  310. char res3[3];
  311. u_char smc_smcm;
  312. char res4[5];
  313. } smc_t;
  314. /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
  315. * it fits within the address space.
  316. */
  317. typedef struct fec {
  318. uint fec_addr_low; /* lower 32 bits of station address */
  319. ushort fec_addr_high; /* upper 16 bits of station address */
  320. ushort res1; /* reserved */
  321. uint fec_hash_table_high; /* upper 32-bits of hash table */
  322. uint fec_hash_table_low; /* lower 32-bits of hash table */
  323. uint fec_r_des_start; /* beginning of Rx descriptor ring */
  324. uint fec_x_des_start; /* beginning of Tx descriptor ring */
  325. uint fec_r_buff_size; /* Rx buffer size */
  326. uint res2[9]; /* reserved */
  327. uint fec_ecntrl; /* ethernet control register */
  328. uint fec_ievent; /* interrupt event register */
  329. uint fec_imask; /* interrupt mask register */
  330. uint fec_ivec; /* interrupt level and vector status */
  331. uint fec_r_des_active; /* Rx ring updated flag */
  332. uint fec_x_des_active; /* Tx ring updated flag */
  333. uint res3[10]; /* reserved */
  334. uint fec_mii_data; /* MII data register */
  335. uint fec_mii_speed; /* MII speed control register */
  336. uint res4[17]; /* reserved */
  337. uint fec_r_bound; /* end of RAM (read-only) */
  338. uint fec_r_fstart; /* Rx FIFO start address */
  339. uint res5[6]; /* reserved */
  340. uint fec_x_fstart; /* Tx FIFO start address */
  341. uint res6[17]; /* reserved */
  342. uint fec_fun_code; /* fec SDMA function code */
  343. uint res7[3]; /* reserved */
  344. uint fec_r_cntrl; /* Rx control register */
  345. uint fec_r_hash; /* Rx hash register */
  346. uint res8[14]; /* reserved */
  347. uint fec_x_cntrl; /* Tx control register */
  348. uint res9[0x1e]; /* reserved */
  349. } fec_t;
  350. /* The FEC and LCD color map share the same address space....
  351. * I guess we will never see an 823T :-).
  352. */
  353. union fec_lcd {
  354. fec_t fl_un_fec;
  355. u_char fl_un_cmap[0x200];
  356. };
  357. typedef struct comm_proc {
  358. /* General control and status registers.
  359. */
  360. ushort cp_cpcr;
  361. u_char res1[2];
  362. ushort cp_rccr;
  363. u_char res2;
  364. u_char cp_rmds;
  365. u_char res3[4];
  366. ushort cp_cpmcr1;
  367. ushort cp_cpmcr2;
  368. ushort cp_cpmcr3;
  369. ushort cp_cpmcr4;
  370. u_char res4[2];
  371. ushort cp_rter;
  372. u_char res5[2];
  373. ushort cp_rtmr;
  374. u_char res6[0x14];
  375. /* Baud rate generators.
  376. */
  377. uint cp_brgc1;
  378. uint cp_brgc2;
  379. uint cp_brgc3;
  380. uint cp_brgc4;
  381. /* Serial Communication Channels.
  382. */
  383. scc_t cp_scc[4];
  384. /* Serial Management Channels.
  385. */
  386. smc_t cp_smc[2];
  387. /* Serial Peripheral Interface.
  388. */
  389. ushort cp_spmode;
  390. u_char res7[4];
  391. u_char cp_spie;
  392. u_char res8[3];
  393. u_char cp_spim;
  394. u_char res9[2];
  395. u_char cp_spcom;
  396. u_char res10[2];
  397. /* Parallel Interface Port.
  398. */
  399. u_char res11[2];
  400. ushort cp_pipc;
  401. u_char res12[2];
  402. ushort cp_ptpr;
  403. uint cp_pbdir;
  404. uint cp_pbpar;
  405. u_char res13[2];
  406. ushort cp_pbodr;
  407. uint cp_pbdat;
  408. /* Port E - MPC87x/88x only.
  409. */
  410. uint cp_pedir;
  411. uint cp_pepar;
  412. uint cp_peso;
  413. uint cp_peodr;
  414. uint cp_pedat;
  415. /* Communications Processor Timing Register -
  416. Contains RMII Timing for the FECs on MPC87x/88x only.
  417. */
  418. uint cp_cptr;
  419. /* Serial Interface and Time Slot Assignment.
  420. */
  421. uint cp_simode;
  422. u_char cp_sigmr;
  423. u_char res15;
  424. u_char cp_sistr;
  425. u_char cp_sicmr;
  426. u_char res16[4];
  427. uint cp_sicr;
  428. uint cp_sirp;
  429. u_char res17[0xc];
  430. /* 256 bytes of MPC823 video controller RAM array.
  431. */
  432. u_char cp_vcram[0x100];
  433. u_char cp_siram[0x200];
  434. /* The fast ethernet controller is not really part of the CPM,
  435. * but it resides in the address space.
  436. * The LCD color map is also here.
  437. */
  438. union fec_lcd fl_un;
  439. #define cp_fec fl_un.fl_un_fec
  440. #define lcd_cmap fl_un.fl_un_cmap
  441. char res18[0xE00];
  442. /* The MPC885 family has a second FEC here */
  443. fec_t cp_fec2;
  444. #define cp_fec1 cp_fec /* consistency macro */
  445. /* Dual Ported RAM follows.
  446. * There are many different formats for this memory area
  447. * depending upon the devices used and options chosen.
  448. * Some processors don't have all of it populated.
  449. */
  450. u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
  451. /* Parameter RAM */
  452. union {
  453. u_char cp_dparam[0x400];
  454. u16 cp_dparam16[0x200];
  455. };
  456. } cpm8xx_t;
  457. /* Internal memory map.
  458. */
  459. typedef struct immap {
  460. sysconf8xx_t im_siu_conf; /* SIU Configuration */
  461. pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
  462. memctl8xx_t im_memctl; /* Memory Controller */
  463. sit8xx_t im_sit; /* System integration timers */
  464. car8xx_t im_clkrst; /* Clocks and reset */
  465. sitk8xx_t im_sitk; /* Sys int timer keys */
  466. cark8xx_t im_clkrstk; /* Clocks and reset keys */
  467. vid823_t im_vid; /* Video (823 only) */
  468. lcd823_t im_lcd; /* LCD (823 only) */
  469. i2c8xx_t im_i2c; /* I2C control/status */
  470. sdma8xx_t im_sdma; /* SDMA control/status */
  471. cpic8xx_t im_cpic; /* CPM Interrupt Controller */
  472. iop8xx_t im_ioport; /* IO Port control/status */
  473. cpmtimer8xx_t im_cpmtimer; /* CPM timers */
  474. cpm8xx_t im_cpm; /* Communication processor */
  475. } immap_t;
  476. #endif /* __IMMAP_8XX__ */