spi.c 14 KB

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  1. /*
  2. * Copyright (c) 2001 Navin Boppuri / Prashant Patel
  3. * <nboppuri@trinetcommunication.com>,
  4. * <pmpatel@trinetcommunication.com>
  5. * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
  6. * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /*
  11. * MPC8xx CPM SPI interface.
  12. *
  13. * Parts of this code are probably not portable and/or specific to
  14. * the board which I used for the tests. Please send fixes/complaints
  15. * to wd@denx.de
  16. *
  17. */
  18. #include <common.h>
  19. #include <mpc8xx.h>
  20. #include <commproc.h>
  21. #include <linux/ctype.h>
  22. #include <malloc.h>
  23. #include <post.h>
  24. #include <serial.h>
  25. #if (defined(CONFIG_SPI)) || (CONFIG_POST & CONFIG_SYS_POST_SPI)
  26. /* Warning:
  27. * You cannot enable DEBUG for early system initalization, i. e. when
  28. * this driver is used to read environment parameters like "baudrate"
  29. * from EEPROM which are used to initialize the serial port which is
  30. * needed to print the debug messages...
  31. */
  32. #undef DEBUG
  33. #define SPI_EEPROM_WREN 0x06
  34. #define SPI_EEPROM_RDSR 0x05
  35. #define SPI_EEPROM_READ 0x03
  36. #define SPI_EEPROM_WRITE 0x02
  37. /* ---------------------------------------------------------------
  38. * Offset for initial SPI buffers in DPRAM:
  39. * We need a 520 byte scratch DPRAM area to use at an early stage.
  40. * It is used between the two initialization calls (spi_init_f()
  41. * and spi_init_r()).
  42. * The value 0xb00 makes it far enough from the start of the data
  43. * area (as well as from the stack pointer).
  44. * --------------------------------------------------------------- */
  45. #ifndef CONFIG_SYS_SPI_INIT_OFFSET
  46. #define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
  47. #endif
  48. #ifdef DEBUG
  49. #define DPRINT(a) printf a;
  50. /* -----------------------------------------------
  51. * Helper functions to peek into tx and rx buffers
  52. * ----------------------------------------------- */
  53. static const char * const hex_digit = "0123456789ABCDEF";
  54. static char quickhex (int i)
  55. {
  56. return hex_digit[i];
  57. }
  58. static void memdump (void *pv, int num)
  59. {
  60. int i;
  61. unsigned char *pc = (unsigned char *) pv;
  62. for (i = 0; i < num; i++)
  63. printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
  64. printf ("\t");
  65. for (i = 0; i < num; i++)
  66. printf ("%c", isprint (pc[i]) ? pc[i] : '.');
  67. printf ("\n");
  68. }
  69. #else /* !DEBUG */
  70. #define DPRINT(a)
  71. #endif /* DEBUG */
  72. /* -------------------
  73. * Function prototypes
  74. * ------------------- */
  75. void spi_init (void);
  76. ssize_t spi_read (uchar *, int, uchar *, int);
  77. ssize_t spi_write (uchar *, int, uchar *, int);
  78. ssize_t spi_xfer (size_t);
  79. /* -------------------
  80. * Variables
  81. * ------------------- */
  82. #define MAX_BUFFER 0x104
  83. /* ----------------------------------------------------------------------
  84. * Initially we place the RX and TX buffers at a fixed location in DPRAM!
  85. * ---------------------------------------------------------------------- */
  86. static uchar *rxbuf =
  87. (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
  88. [CONFIG_SYS_SPI_INIT_OFFSET];
  89. static uchar *txbuf =
  90. (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
  91. [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
  92. /* **************************************************************************
  93. *
  94. * Function: spi_init_f
  95. *
  96. * Description: Init SPI-Controller (ROM part)
  97. *
  98. * return: ---
  99. *
  100. * *********************************************************************** */
  101. void spi_init_f (void)
  102. {
  103. unsigned int dpaddr;
  104. volatile spi_t *spi;
  105. volatile immap_t *immr;
  106. volatile cpm8xx_t *cp;
  107. volatile cbd_t *tbdf, *rbdf;
  108. immr = (immap_t *) CONFIG_SYS_IMMR;
  109. cp = (cpm8xx_t *) &immr->im_cpm;
  110. #ifdef CONFIG_SYS_SPI_UCODE_PATCH
  111. spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
  112. #else
  113. spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
  114. /* Disable relocation */
  115. spi->spi_rpbase = 0;
  116. #endif
  117. /* 1 */
  118. /* ------------------------------------------------
  119. * Initialize Port B SPI pins -> page 34-8 MPC860UM
  120. * (we are only in Master Mode !)
  121. * ------------------------------------------------ */
  122. /* --------------------------------------------
  123. * GPIO or per. Function
  124. * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
  125. * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
  126. * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
  127. * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
  128. * -------------------------------------------- */
  129. cp->cp_pbpar |= 0x0000000E; /* set bits */
  130. cp->cp_pbpar &= ~0x00000001; /* reset bit */
  131. /* ----------------------------------------------
  132. * In/Out or per. Function 0/1
  133. * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
  134. * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
  135. * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
  136. * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
  137. * ---------------------------------------------- */
  138. cp->cp_pbdir |= 0x0000000F;
  139. /* ----------------------------------------------
  140. * open drain or active output
  141. * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
  142. * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
  143. * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
  144. * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
  145. * ---------------------------------------------- */
  146. cp->cp_pbodr |= 0x00000008;
  147. cp->cp_pbodr &= ~0x00000007;
  148. /* Initialize the parameter ram.
  149. * We need to make sure many things are initialized to zero
  150. */
  151. spi->spi_rstate = 0;
  152. spi->spi_rdp = 0;
  153. spi->spi_rbptr = 0;
  154. spi->spi_rbc = 0;
  155. spi->spi_rxtmp = 0;
  156. spi->spi_tstate = 0;
  157. spi->spi_tdp = 0;
  158. spi->spi_tbptr = 0;
  159. spi->spi_tbc = 0;
  160. spi->spi_txtmp = 0;
  161. dpaddr = CPM_SPI_BASE;
  162. /* 3 */
  163. /* Set up the SPI parameters in the parameter ram */
  164. spi->spi_rbase = dpaddr;
  165. spi->spi_tbase = dpaddr + sizeof (cbd_t);
  166. /***********IMPORTANT******************/
  167. /*
  168. * Setting transmit and receive buffer descriptor pointers
  169. * initially to rbase and tbase. Only the microcode patches
  170. * documentation talks about initializing this pointer. This
  171. * is missing from the sample I2C driver. If you dont
  172. * initialize these pointers, the kernel hangs.
  173. */
  174. spi->spi_rbptr = spi->spi_rbase;
  175. spi->spi_tbptr = spi->spi_tbase;
  176. /* 4 */
  177. #ifdef CONFIG_SYS_SPI_UCODE_PATCH
  178. /*
  179. * Initialize required parameters if using microcode patch.
  180. */
  181. spi->spi_rstate = 0;
  182. spi->spi_tstate = 0;
  183. #else
  184. /* Init SPI Tx + Rx Parameters */
  185. while (cp->cp_cpcr & CPM_CR_FLG)
  186. ;
  187. cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
  188. while (cp->cp_cpcr & CPM_CR_FLG)
  189. ;
  190. #endif /* CONFIG_SYS_SPI_UCODE_PATCH */
  191. /* 5 */
  192. /* Set SDMA configuration register */
  193. immr->im_siu_conf.sc_sdcr = 0x0001;
  194. /* 6 */
  195. /* Set to big endian. */
  196. spi->spi_tfcr = SMC_EB;
  197. spi->spi_rfcr = SMC_EB;
  198. /* 7 */
  199. /* Set maximum receive size. */
  200. spi->spi_mrblr = MAX_BUFFER;
  201. /* 8 + 9 */
  202. /* tx and rx buffer descriptors */
  203. tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
  204. rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
  205. tbdf->cbd_sc &= ~BD_SC_READY;
  206. rbdf->cbd_sc &= ~BD_SC_EMPTY;
  207. /* Set the bd's rx and tx buffer address pointers */
  208. rbdf->cbd_bufaddr = (ulong) rxbuf;
  209. tbdf->cbd_bufaddr = (ulong) txbuf;
  210. /* 10 + 11 */
  211. cp->cp_spim = 0; /* Mask all SPI events */
  212. cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
  213. return;
  214. }
  215. /* **************************************************************************
  216. *
  217. * Function: spi_init_r
  218. *
  219. * Description: Init SPI-Controller (RAM part) -
  220. * The malloc engine is ready and we can move our buffers to
  221. * normal RAM
  222. *
  223. * return: ---
  224. *
  225. * *********************************************************************** */
  226. void spi_init_r (void)
  227. {
  228. volatile cpm8xx_t *cp;
  229. volatile spi_t *spi;
  230. volatile immap_t *immr;
  231. volatile cbd_t *tbdf, *rbdf;
  232. immr = (immap_t *) CONFIG_SYS_IMMR;
  233. cp = (cpm8xx_t *) &immr->im_cpm;
  234. #ifdef CONFIG_SYS_SPI_UCODE_PATCH
  235. spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
  236. #else
  237. spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
  238. /* Disable relocation */
  239. spi->spi_rpbase = 0;
  240. #endif
  241. /* tx and rx buffer descriptors */
  242. tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
  243. rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
  244. /* Allocate memory for RX and TX buffers */
  245. rxbuf = (uchar *) malloc (MAX_BUFFER);
  246. txbuf = (uchar *) malloc (MAX_BUFFER);
  247. rbdf->cbd_bufaddr = (ulong) rxbuf;
  248. tbdf->cbd_bufaddr = (ulong) txbuf;
  249. return;
  250. }
  251. /****************************************************************************
  252. * Function: spi_write
  253. **************************************************************************** */
  254. ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
  255. {
  256. int i;
  257. memset(rxbuf, 0, MAX_BUFFER);
  258. memset(txbuf, 0, MAX_BUFFER);
  259. *txbuf = SPI_EEPROM_WREN; /* write enable */
  260. spi_xfer(1);
  261. memcpy(txbuf, addr, alen);
  262. *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */
  263. memcpy(alen + txbuf, buffer, len);
  264. spi_xfer(alen + len);
  265. /* ignore received data */
  266. for (i = 0; i < 1000; i++) {
  267. *txbuf = SPI_EEPROM_RDSR; /* read status */
  268. txbuf[1] = 0;
  269. spi_xfer(2);
  270. if (!(rxbuf[1] & 1)) {
  271. break;
  272. }
  273. udelay(1000);
  274. }
  275. if (i >= 1000) {
  276. printf ("*** spi_write: Time out while writing!\n");
  277. }
  278. return len;
  279. }
  280. /****************************************************************************
  281. * Function: spi_read
  282. **************************************************************************** */
  283. ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
  284. {
  285. memset(rxbuf, 0, MAX_BUFFER);
  286. memset(txbuf, 0, MAX_BUFFER);
  287. memcpy(txbuf, addr, alen);
  288. *txbuf = SPI_EEPROM_READ; /* READ memory array */
  289. /*
  290. * There is a bug in 860T (?) that cuts the last byte of input
  291. * if we're reading into DPRAM. The solution we choose here is
  292. * to always read len+1 bytes (we have one extra byte at the
  293. * end of the buffer).
  294. */
  295. spi_xfer(alen + len + 1);
  296. memcpy(buffer, alen + rxbuf, len);
  297. return len;
  298. }
  299. /****************************************************************************
  300. * Function: spi_xfer
  301. **************************************************************************** */
  302. ssize_t spi_xfer (size_t count)
  303. {
  304. volatile immap_t *immr;
  305. volatile cpm8xx_t *cp;
  306. volatile spi_t *spi;
  307. cbd_t *tbdf, *rbdf;
  308. ushort loop;
  309. int tm;
  310. DPRINT (("*** spi_xfer entered ***\n"));
  311. immr = (immap_t *) CONFIG_SYS_IMMR;
  312. cp = (cpm8xx_t *) &immr->im_cpm;
  313. #ifdef CONFIG_SYS_SPI_UCODE_PATCH
  314. spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
  315. #else
  316. spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
  317. /* Disable relocation */
  318. spi->spi_rpbase = 0;
  319. #endif
  320. tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
  321. rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
  322. /* Set CS for device */
  323. cp->cp_pbdat &= ~0x0001;
  324. /* Setting tx bd status and data length */
  325. tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
  326. tbdf->cbd_datlen = count;
  327. DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n",
  328. tbdf->cbd_datlen));
  329. /* Setting rx bd status and data length */
  330. rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
  331. rbdf->cbd_datlen = 0; /* rx length has no significance */
  332. loop = cp->cp_spmode & SPMODE_LOOP;
  333. cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */
  334. loop |
  335. SPMODE_REV |
  336. SPMODE_MSTR |
  337. SPMODE_EN |
  338. SPMODE_LEN(8) | /* 8 Bits per char */
  339. SPMODE_PM(0x8) ; /* medium speed */
  340. cp->cp_spim = 0; /* Mask all SPI events */
  341. cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
  342. /* start spi transfer */
  343. DPRINT (("*** spi_xfer: Performing transfer ...\n"));
  344. cp->cp_spcom |= SPI_STR; /* Start transmit */
  345. /* --------------------------------
  346. * Wait for SPI transmit to get out
  347. * or time out (1 second = 1000 ms)
  348. * -------------------------------- */
  349. for (tm=0; tm<1000; ++tm) {
  350. if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */
  351. DPRINT (("*** spi_xfer: Tx buffer empty\n"));
  352. break;
  353. }
  354. if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
  355. DPRINT (("*** spi_xfer: Tx BD done\n"));
  356. break;
  357. }
  358. udelay (1000);
  359. }
  360. if (tm >= 1000) {
  361. printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
  362. }
  363. DPRINT (("*** spi_xfer: ... transfer ended\n"));
  364. #ifdef DEBUG
  365. printf ("\nspi_xfer: txbuf after xfer\n");
  366. memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */
  367. printf ("spi_xfer: rxbuf after xfer\n");
  368. memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */
  369. printf ("\n");
  370. #endif
  371. /* Clear CS for device */
  372. cp->cp_pbdat |= 0x0001;
  373. return count;
  374. }
  375. #endif /* CONFIG_SPI || (CONFIG_POST & CONFIG_SYS_POST_SPI) */
  376. /*
  377. * SPI test
  378. *
  379. * The Serial Peripheral Interface (SPI) is tested in the local loopback mode.
  380. * The interface is configured accordingly and several packets
  381. * are transferred. The configurable test parameters are:
  382. * TEST_MIN_LENGTH - minimum size of packet to transfer
  383. * TEST_MAX_LENGTH - maximum size of packet to transfer
  384. * TEST_NUM - number of tests
  385. */
  386. #if CONFIG_POST & CONFIG_SYS_POST_SPI
  387. #define TEST_MIN_LENGTH 1
  388. #define TEST_MAX_LENGTH MAX_BUFFER
  389. #define TEST_NUM 1
  390. static void packet_fill (char * packet, int length)
  391. {
  392. char c = (char) length;
  393. int i;
  394. for (i = 0; i < length; i++)
  395. {
  396. packet[i] = c++;
  397. }
  398. }
  399. static int packet_check (char * packet, int length)
  400. {
  401. char c = (char) length;
  402. int i;
  403. for (i = 0; i < length; i++) {
  404. if (packet[i] != c++) return -1;
  405. }
  406. return 0;
  407. }
  408. int spi_post_test (int flags)
  409. {
  410. int res = -1;
  411. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  412. volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm;
  413. int i;
  414. int l;
  415. spi_init_f ();
  416. spi_init_r ();
  417. cp->cp_spmode |= SPMODE_LOOP;
  418. for (i = 0; i < TEST_NUM; i++) {
  419. for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) {
  420. packet_fill ((char *)txbuf, l);
  421. spi_xfer (l);
  422. if (packet_check ((char *)rxbuf, l) < 0) {
  423. goto Done;
  424. }
  425. }
  426. }
  427. res = 0;
  428. Done:
  429. cp->cp_spmode &= ~SPMODE_LOOP;
  430. /*
  431. * SCC2 parameter RAM space overlaps
  432. * the SPI parameter RAM space. So we need to restore
  433. * the SCC2 configuration if it is used by UART.
  434. */
  435. #if !defined(CONFIG_8xx_CONS_NONE)
  436. serial_reinit_all ();
  437. #endif
  438. if (res != 0) {
  439. post_log ("SPI test failed\n");
  440. }
  441. return res;
  442. }
  443. #endif /* CONFIG_POST & CONFIG_SYS_POST_SPI */