serial.c 15 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <commproc.h>
  9. #include <command.h>
  10. #include <serial.h>
  11. #include <watchdog.h>
  12. #include <linux/compiler.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
  15. #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
  16. #define SMC_INDEX 0
  17. #define PROFF_SMC PROFF_SMC1
  18. #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
  19. #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
  20. #define SMC_INDEX 1
  21. #define PROFF_SMC PROFF_SMC2
  22. #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
  23. #endif /* CONFIG_8xx_CONS_SMCx */
  24. #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
  25. #define SCC_INDEX 0
  26. #define PROFF_SCC PROFF_SCC1
  27. #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
  28. #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
  29. #define SCC_INDEX 1
  30. #define PROFF_SCC PROFF_SCC2
  31. #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
  32. #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
  33. #define SCC_INDEX 2
  34. #define PROFF_SCC PROFF_SCC3
  35. #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
  36. #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
  37. #define SCC_INDEX 3
  38. #define PROFF_SCC PROFF_SCC4
  39. #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
  40. #endif /* CONFIG_8xx_CONS_SCCx */
  41. #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
  42. #define CONFIG_SYS_SMC_RXBUFLEN 1
  43. #define CONFIG_SYS_MAXIDLE 0
  44. #else
  45. #if !defined(CONFIG_SYS_MAXIDLE)
  46. #error "you must define CONFIG_SYS_MAXIDLE"
  47. #endif
  48. #endif
  49. typedef volatile struct serialbuffer {
  50. cbd_t rxbd; /* Rx BD */
  51. cbd_t txbd; /* Tx BD */
  52. uint rxindex; /* index for next character to read */
  53. volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
  54. volatile uchar txbuf; /* tx buffers */
  55. } serialbuffer_t;
  56. static void serial_setdivisor(volatile cpm8xx_t *cp)
  57. {
  58. int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
  59. if(divisor/16>0x1000) {
  60. /* bad divisor, assume 50MHz clock and 9600 baud */
  61. divisor=(50*1000*1000 + 8*9600)/16/9600;
  62. }
  63. #ifdef CONFIG_SYS_BRGCLK_PRESCALE
  64. divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
  65. #endif
  66. if(divisor<=0x1000) {
  67. cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
  68. } else {
  69. cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
  70. }
  71. }
  72. #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
  73. /*
  74. * Minimal serial functions needed to use one of the SMC ports
  75. * as serial console interface.
  76. */
  77. static void smc_setbrg (void)
  78. {
  79. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  80. volatile cpm8xx_t *cp = &(im->im_cpm);
  81. /* Set up the baud rate generator.
  82. * See 8xx_io/commproc.c for details.
  83. *
  84. * Wire BRG1 to SMCx
  85. */
  86. cp->cp_simode = 0x00000000;
  87. serial_setdivisor(cp);
  88. }
  89. static int smc_init (void)
  90. {
  91. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  92. volatile smc_t *sp;
  93. volatile smc_uart_t *up;
  94. volatile cpm8xx_t *cp = &(im->im_cpm);
  95. #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
  96. volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
  97. #endif
  98. uint dpaddr;
  99. volatile serialbuffer_t *rtx;
  100. /* initialize pointers to SMC */
  101. sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
  102. up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
  103. #ifdef CONFIG_SYS_SMC_UCODE_PATCH
  104. up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
  105. #else
  106. /* Disable relocation */
  107. up->smc_rpbase = 0;
  108. #endif
  109. /* Disable transmitter/receiver. */
  110. sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  111. /* Enable SDMA. */
  112. im->im_siu_conf.sc_sdcr = 1;
  113. /* clear error conditions */
  114. #ifdef CONFIG_SYS_SDSR
  115. im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
  116. #else
  117. im->im_sdma.sdma_sdsr = 0x83;
  118. #endif
  119. /* clear SDMA interrupt mask */
  120. #ifdef CONFIG_SYS_SDMR
  121. im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
  122. #else
  123. im->im_sdma.sdma_sdmr = 0x00;
  124. #endif
  125. #if defined(CONFIG_8xx_CONS_SMC1)
  126. /* Use Port B for SMC1 instead of other functions. */
  127. cp->cp_pbpar |= 0x000000c0;
  128. cp->cp_pbdir &= ~0x000000c0;
  129. cp->cp_pbodr &= ~0x000000c0;
  130. #else /* CONFIG_8xx_CONS_SMC2 */
  131. # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
  132. /* Use Port A for SMC2 instead of other functions. */
  133. ip->iop_papar |= 0x00c0;
  134. ip->iop_padir &= ~0x00c0;
  135. ip->iop_paodr &= ~0x00c0;
  136. # else /* must be a 860 then */
  137. /* Use Port B for SMC2 instead of other functions.
  138. */
  139. cp->cp_pbpar |= 0x00000c00;
  140. cp->cp_pbdir &= ~0x00000c00;
  141. cp->cp_pbodr &= ~0x00000c00;
  142. # endif
  143. #endif
  144. /* Set the physical address of the host memory buffers in
  145. * the buffer descriptors.
  146. */
  147. dpaddr = CPM_SERIAL_BASE;
  148. rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
  149. /* Allocate space for two buffer descriptors in the DP ram.
  150. * For now, this address seems OK, but it may have to
  151. * change with newer versions of the firmware.
  152. * damm: allocating space after the two buffers for rx/tx data
  153. */
  154. rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
  155. rtx->rxbd.cbd_sc = 0;
  156. rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
  157. rtx->txbd.cbd_sc = 0;
  158. /* Set up the uart parameters in the parameter ram. */
  159. up->smc_rbase = dpaddr;
  160. up->smc_tbase = dpaddr+sizeof(cbd_t);
  161. up->smc_rfcr = SMC_EB;
  162. up->smc_tfcr = SMC_EB;
  163. #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
  164. up->smc_rbptr = up->smc_rbase;
  165. up->smc_tbptr = up->smc_tbase;
  166. up->smc_rstate = 0;
  167. up->smc_tstate = 0;
  168. #endif
  169. /* Set UART mode, 8 bit, no parity, one stop.
  170. * Enable receive and transmit.
  171. */
  172. sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
  173. /* Mask all interrupts and remove anything pending.
  174. */
  175. sp->smc_smcm = 0;
  176. sp->smc_smce = 0xff;
  177. #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
  178. /* clock source is PLD */
  179. /* set freq to 19200 Baud */
  180. *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
  181. /* configure clk4 as input */
  182. im->im_ioport.iop_pdpar |= 0x800;
  183. im->im_ioport.iop_pddir &= ~0x800;
  184. cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
  185. #else
  186. /* Set up the baud rate generator */
  187. smc_setbrg ();
  188. #endif
  189. /* Make the first buffer the only buffer. */
  190. rtx->txbd.cbd_sc |= BD_SC_WRAP;
  191. rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
  192. /* single/multi character receive. */
  193. up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
  194. up->smc_maxidl = CONFIG_SYS_MAXIDLE;
  195. rtx->rxindex = 0;
  196. /* Initialize Tx/Rx parameters. */
  197. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  198. ;
  199. cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
  200. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  201. ;
  202. /* Enable transmitter/receiver. */
  203. sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
  204. return (0);
  205. }
  206. static void
  207. smc_putc(const char c)
  208. {
  209. volatile smc_uart_t *up;
  210. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  211. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  212. volatile serialbuffer_t *rtx;
  213. if (c == '\n')
  214. smc_putc ('\r');
  215. up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
  216. #ifdef CONFIG_SYS_SMC_UCODE_PATCH
  217. up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
  218. #endif
  219. rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
  220. /* Wait for last character to go. */
  221. rtx->txbuf = c;
  222. rtx->txbd.cbd_datlen = 1;
  223. rtx->txbd.cbd_sc |= BD_SC_READY;
  224. __asm__("eieio");
  225. while (rtx->txbd.cbd_sc & BD_SC_READY) {
  226. WATCHDOG_RESET ();
  227. __asm__("eieio");
  228. }
  229. }
  230. static void
  231. smc_puts (const char *s)
  232. {
  233. while (*s) {
  234. smc_putc (*s++);
  235. }
  236. }
  237. static int
  238. smc_getc(void)
  239. {
  240. volatile smc_uart_t *up;
  241. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  242. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  243. volatile serialbuffer_t *rtx;
  244. unsigned char c;
  245. up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
  246. #ifdef CONFIG_SYS_SMC_UCODE_PATCH
  247. up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
  248. #endif
  249. rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
  250. /* Wait for character to show up. */
  251. while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
  252. WATCHDOG_RESET ();
  253. /* the characters are read one by one,
  254. * use the rxindex to know the next char to deliver
  255. */
  256. c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
  257. rtx->rxindex++;
  258. /* check if all char are readout, then make prepare for next receive */
  259. if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
  260. rtx->rxindex = 0;
  261. rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
  262. }
  263. return(c);
  264. }
  265. static int
  266. smc_tstc(void)
  267. {
  268. volatile smc_uart_t *up;
  269. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  270. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  271. volatile serialbuffer_t *rtx;
  272. up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
  273. #ifdef CONFIG_SYS_SMC_UCODE_PATCH
  274. up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
  275. #endif
  276. rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
  277. return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
  278. }
  279. struct serial_device serial_smc_device =
  280. {
  281. .name = "serial_smc",
  282. .start = smc_init,
  283. .stop = NULL,
  284. .setbrg = smc_setbrg,
  285. .getc = smc_getc,
  286. .tstc = smc_tstc,
  287. .putc = smc_putc,
  288. .puts = smc_puts,
  289. };
  290. #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
  291. #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
  292. defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
  293. static void
  294. scc_setbrg (void)
  295. {
  296. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  297. volatile cpm8xx_t *cp = &(im->im_cpm);
  298. /* Set up the baud rate generator.
  299. * See 8xx_io/commproc.c for details.
  300. *
  301. * Wire BRG1 to SCCx
  302. */
  303. cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
  304. serial_setdivisor(cp);
  305. }
  306. static int scc_init (void)
  307. {
  308. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  309. volatile scc_t *sp;
  310. volatile scc_uart_t *up;
  311. volatile cbd_t *tbdf, *rbdf;
  312. volatile cpm8xx_t *cp = &(im->im_cpm);
  313. uint dpaddr;
  314. #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
  315. volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
  316. #endif
  317. /* initialize pointers to SCC */
  318. sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
  319. up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
  320. /* Disable transmitter/receiver. */
  321. sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  322. #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
  323. /*
  324. * The MPC850 has SCC3 on Port B
  325. */
  326. cp->cp_pbpar |= 0x06;
  327. cp->cp_pbdir &= ~0x06;
  328. cp->cp_pbodr &= ~0x06;
  329. #elif (SCC_INDEX < 2)
  330. /*
  331. * Standard configuration for SCC's is on Part A
  332. */
  333. ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
  334. ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
  335. ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
  336. #endif
  337. /* Allocate space for two buffer descriptors in the DP ram. */
  338. dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8);
  339. /* Enable SDMA. */
  340. im->im_siu_conf.sc_sdcr = 0x0001;
  341. /* Set the physical address of the host memory buffers in
  342. * the buffer descriptors.
  343. */
  344. rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
  345. rbdf->cbd_bufaddr = (uint) (rbdf+2);
  346. rbdf->cbd_sc = 0;
  347. tbdf = rbdf + 1;
  348. tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
  349. tbdf->cbd_sc = 0;
  350. /* Set up the baud rate generator. */
  351. scc_setbrg ();
  352. /* Set up the uart parameters in the parameter ram. */
  353. up->scc_genscc.scc_rbase = dpaddr;
  354. up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
  355. /* Initialize Tx/Rx parameters. */
  356. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  357. ;
  358. cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
  359. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  360. ;
  361. up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
  362. up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
  363. up->scc_genscc.scc_mrblr = 1; /* Single character receive */
  364. up->scc_maxidl = 0; /* disable max idle */
  365. up->scc_brkcr = 1; /* send one break character on stop TX */
  366. up->scc_parec = 0;
  367. up->scc_frmec = 0;
  368. up->scc_nosec = 0;
  369. up->scc_brkec = 0;
  370. up->scc_uaddr1 = 0;
  371. up->scc_uaddr2 = 0;
  372. up->scc_toseq = 0;
  373. up->scc_char1 = 0x8000;
  374. up->scc_char2 = 0x8000;
  375. up->scc_char3 = 0x8000;
  376. up->scc_char4 = 0x8000;
  377. up->scc_char5 = 0x8000;
  378. up->scc_char6 = 0x8000;
  379. up->scc_char7 = 0x8000;
  380. up->scc_char8 = 0x8000;
  381. up->scc_rccm = 0xc0ff;
  382. /* Set low latency / small fifo. */
  383. sp->scc_gsmrh = SCC_GSMRH_RFW;
  384. /* Set SCC(x) clock mode to 16x
  385. * See 8xx_io/commproc.c for details.
  386. *
  387. * Wire BRG1 to SCCn
  388. */
  389. /* Set UART mode, clock divider 16 on Tx and Rx */
  390. sp->scc_gsmrl &= ~0xF;
  391. sp->scc_gsmrl |=
  392. (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
  393. sp->scc_psmr = 0;
  394. sp->scc_psmr |= SCU_PSMR_CL;
  395. /* Mask all interrupts and remove anything pending. */
  396. sp->scc_sccm = 0;
  397. sp->scc_scce = 0xffff;
  398. sp->scc_dsr = 0x7e7e;
  399. sp->scc_psmr = 0x3000;
  400. /* Make the first buffer the only buffer. */
  401. tbdf->cbd_sc |= BD_SC_WRAP;
  402. rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
  403. /* Enable transmitter/receiver. */
  404. sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  405. return (0);
  406. }
  407. static void
  408. scc_putc(const char c)
  409. {
  410. volatile cbd_t *tbdf;
  411. volatile char *buf;
  412. volatile scc_uart_t *up;
  413. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  414. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  415. if (c == '\n')
  416. scc_putc ('\r');
  417. up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
  418. tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
  419. /* Wait for last character to go. */
  420. buf = (char *)tbdf->cbd_bufaddr;
  421. *buf = c;
  422. tbdf->cbd_datlen = 1;
  423. tbdf->cbd_sc |= BD_SC_READY;
  424. __asm__("eieio");
  425. while (tbdf->cbd_sc & BD_SC_READY) {
  426. __asm__("eieio");
  427. WATCHDOG_RESET ();
  428. }
  429. }
  430. static void
  431. scc_puts (const char *s)
  432. {
  433. while (*s) {
  434. scc_putc (*s++);
  435. }
  436. }
  437. static int
  438. scc_getc(void)
  439. {
  440. volatile cbd_t *rbdf;
  441. volatile unsigned char *buf;
  442. volatile scc_uart_t *up;
  443. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  444. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  445. unsigned char c;
  446. up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
  447. rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
  448. /* Wait for character to show up. */
  449. buf = (unsigned char *)rbdf->cbd_bufaddr;
  450. while (rbdf->cbd_sc & BD_SC_EMPTY)
  451. WATCHDOG_RESET ();
  452. c = *buf;
  453. rbdf->cbd_sc |= BD_SC_EMPTY;
  454. return(c);
  455. }
  456. static int
  457. scc_tstc(void)
  458. {
  459. volatile cbd_t *rbdf;
  460. volatile scc_uart_t *up;
  461. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  462. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  463. up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
  464. rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
  465. return(!(rbdf->cbd_sc & BD_SC_EMPTY));
  466. }
  467. struct serial_device serial_scc_device =
  468. {
  469. .name = "serial_scc",
  470. .start = scc_init,
  471. .stop = NULL,
  472. .setbrg = scc_setbrg,
  473. .getc = scc_getc,
  474. .tstc = scc_tstc,
  475. .putc = scc_putc,
  476. .puts = scc_puts,
  477. };
  478. #endif /* CONFIG_8xx_CONS_SCCx */
  479. __weak struct serial_device *default_serial_console(void)
  480. {
  481. #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
  482. return &serial_smc_device;
  483. #else
  484. return &serial_scc_device;
  485. #endif
  486. }
  487. void mpc8xx_serial_initialize(void)
  488. {
  489. #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
  490. serial_register(&serial_smc_device);
  491. #endif
  492. #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
  493. defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
  494. serial_register(&serial_scc_device);
  495. #endif
  496. }
  497. #if defined(CONFIG_CMD_KGDB)
  498. void
  499. kgdb_serial_init(void)
  500. {
  501. int i = -1;
  502. if (strcmp(default_serial_console()->name, "serial_smc") == 0)
  503. {
  504. #if defined(CONFIG_8xx_CONS_SMC1)
  505. i = 1;
  506. #elif defined(CONFIG_8xx_CONS_SMC2)
  507. i = 2;
  508. #endif
  509. }
  510. else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
  511. {
  512. #if defined(CONFIG_8xx_CONS_SCC1)
  513. i = 1;
  514. #elif defined(CONFIG_8xx_CONS_SCC2)
  515. i = 2;
  516. #elif defined(CONFIG_8xx_CONS_SCC3)
  517. i = 3;
  518. #elif defined(CONFIG_8xx_CONS_SCC4)
  519. i = 4;
  520. #endif
  521. }
  522. if (i >= 0)
  523. {
  524. serial_printf("[on %s%d] ", default_serial_console()->name, i);
  525. }
  526. }
  527. void
  528. putDebugChar (int c)
  529. {
  530. serial_putc (c);
  531. }
  532. void
  533. putDebugStr (const char *str)
  534. {
  535. serial_puts (str);
  536. }
  537. int
  538. getDebugChar (void)
  539. {
  540. return serial_getc();
  541. }
  542. void
  543. kgdb_interruptible (int yes)
  544. {
  545. return;
  546. }
  547. #endif
  548. #endif /* CONFIG_8xx_CONS_NONE */