scc.c 13 KB

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  1. /*
  2. * File: scc.c
  3. * Description:
  4. * Basic ET HW initialization and packet RX/TX routines
  5. *
  6. * NOTE <<<IMPORTANT: PLEASE READ>>>:
  7. * Do not cache Rx/Tx buffers!
  8. */
  9. /*
  10. * MPC823 <-> MC68160 Connections:
  11. *
  12. * Setup MPC823 to work with MC68160 Enhanced Ethernet
  13. * Serial Tranceiver as follows:
  14. *
  15. * MPC823 Signal MC68160 Comments
  16. * ------ ------ ------- --------
  17. * PA-12 ETHTX --------> TX Eth. Port Transmit Data
  18. * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
  19. * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
  20. * PA-13 ETHRX <-------- RX Eth. Port Receive Data
  21. * PC-8 E_RENA <-------- RENA Eth. Receive Enable
  22. * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
  23. * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
  24. *
  25. * FADS Board Signal MC68160 Comments
  26. * ----------------- ------- --------
  27. * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
  28. * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
  29. * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
  30. * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
  31. *
  32. */
  33. #include <common.h>
  34. #include <malloc.h>
  35. #include <commproc.h>
  36. #include <net.h>
  37. #include <command.h>
  38. #if defined(CONFIG_CMD_NET) && defined(SCC_ENET)
  39. /* Ethernet Transmit and Receive Buffers */
  40. #define DBUF_LENGTH 1520
  41. #define TX_BUF_CNT 2
  42. #define TOUT_LOOP 10000 /* 10 ms to have a packet sent */
  43. static char txbuf[DBUF_LENGTH];
  44. static uint rxIdx; /* index of the current RX buffer */
  45. static uint txIdx; /* index of the current TX buffer */
  46. /*
  47. * SCC Ethernet Tx and Rx buffer descriptors allocated at the
  48. * immr->udata_bd address on Dual-Port RAM
  49. * Provide for Double Buffering
  50. */
  51. typedef volatile struct CommonBufferDescriptor {
  52. cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
  53. cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  54. } RTXBD;
  55. static RTXBD *rtx;
  56. static int scc_send(struct eth_device *dev, void *packet, int length);
  57. static int scc_recv(struct eth_device* dev);
  58. static int scc_init (struct eth_device* dev, bd_t * bd);
  59. static void scc_halt(struct eth_device* dev);
  60. int scc_initialize(bd_t *bis)
  61. {
  62. struct eth_device* dev;
  63. dev = (struct eth_device*) malloc(sizeof *dev);
  64. memset(dev, 0, sizeof *dev);
  65. strcpy(dev->name, "SCC");
  66. dev->iobase = 0;
  67. dev->priv = 0;
  68. dev->init = scc_init;
  69. dev->halt = scc_halt;
  70. dev->send = scc_send;
  71. dev->recv = scc_recv;
  72. eth_register(dev);
  73. return 1;
  74. }
  75. static int scc_send(struct eth_device *dev, void *packet, int length)
  76. {
  77. int i, j=0;
  78. #if 0
  79. volatile char *in, *out;
  80. #endif
  81. /* section 16.9.23.3
  82. * Wait for ready
  83. */
  84. #if 0
  85. while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
  86. out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
  87. in = packet;
  88. for(i = 0; i < length; i++) {
  89. *out++ = *in++;
  90. }
  91. rtx->txbd[txIdx].cbd_datlen = length;
  92. rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
  93. while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
  94. #ifdef ET_DEBUG
  95. printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
  96. #endif
  97. i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
  98. /* wrap around buffer index when necessary */
  99. if (txIdx >= TX_BUF_CNT) txIdx = 0;
  100. #endif
  101. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
  102. udelay (1); /* will also trigger Wd if needed */
  103. j++;
  104. }
  105. if (j>=TOUT_LOOP) printf("TX not ready\n");
  106. rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
  107. rtx->txbd[txIdx].cbd_datlen = length;
  108. rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
  109. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
  110. udelay (1); /* will also trigger Wd if needed */
  111. j++;
  112. }
  113. if (j>=TOUT_LOOP) printf("TX timeout\n");
  114. #ifdef ET_DEBUG
  115. printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
  116. #endif
  117. i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
  118. return i;
  119. }
  120. static int scc_recv (struct eth_device *dev)
  121. {
  122. int length;
  123. for (;;) {
  124. /* section 16.9.23.2 */
  125. if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  126. length = -1;
  127. break; /* nothing received - leave for() loop */
  128. }
  129. length = rtx->rxbd[rxIdx].cbd_datlen;
  130. if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
  131. #ifdef ET_DEBUG
  132. printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
  133. #endif
  134. } else {
  135. /* Pass the packet up to the protocol layers. */
  136. net_process_received_packet(net_rx_packets[rxIdx],
  137. length - 4);
  138. }
  139. /* Give the buffer back to the SCC. */
  140. rtx->rxbd[rxIdx].cbd_datlen = 0;
  141. /* wrap around buffer index when necessary */
  142. if ((rxIdx + 1) >= PKTBUFSRX) {
  143. rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
  144. (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  145. rxIdx = 0;
  146. } else {
  147. rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  148. rxIdx++;
  149. }
  150. }
  151. return length;
  152. }
  153. /**************************************************************
  154. *
  155. * SCC Ethernet Initialization Routine
  156. *
  157. *************************************************************/
  158. static int scc_init (struct eth_device *dev, bd_t * bis)
  159. {
  160. int i;
  161. scc_enet_t *pram_ptr;
  162. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  163. pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
  164. rxIdx = 0;
  165. txIdx = 0;
  166. if (!rtx)
  167. rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
  168. #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
  169. /* Configure port A pins for Txd and Rxd.
  170. */
  171. immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
  172. immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
  173. immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
  174. #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
  175. /* Configure port B pins for Txd and Rxd.
  176. */
  177. immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
  178. immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
  179. immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
  180. #else
  181. #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
  182. #endif
  183. #if defined(PC_ENET_LBK)
  184. /* Configure port C pins to disable External Loopback
  185. */
  186. immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
  187. immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
  188. immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
  189. immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
  190. #endif /* PC_ENET_LBK */
  191. /* Configure port C pins to enable CLSN and RENA.
  192. */
  193. immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  194. immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  195. immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
  196. /* Configure port A for TCLK and RCLK.
  197. */
  198. immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
  199. immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
  200. /*
  201. * Configure Serial Interface clock routing -- see section 16.7.5.3
  202. * First, clear all SCC bits to zero, then set the ones we want.
  203. */
  204. immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
  205. immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
  206. /*
  207. * Initialize SDCR -- see section 16.9.23.7
  208. * SDMA configuration register
  209. */
  210. immr->im_siu_conf.sc_sdcr = 0x01;
  211. /*
  212. * Setup SCC Ethernet Parameter RAM
  213. */
  214. pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
  215. pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
  216. pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
  217. pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
  218. pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
  219. /*
  220. * Setup Receiver Buffer Descriptors (13.14.24.18)
  221. * Settings:
  222. * Empty, Wrap
  223. */
  224. for (i = 0; i < PKTBUFSRX; i++) {
  225. rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  226. rtx->rxbd[i].cbd_datlen = 0; /* Reset */
  227. rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
  228. }
  229. rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  230. /*
  231. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  232. * Settings:
  233. * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
  234. */
  235. for (i = 0; i < TX_BUF_CNT; i++) {
  236. rtx->txbd[i].cbd_sc =
  237. (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  238. rtx->txbd[i].cbd_datlen = 0; /* Reset */
  239. rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
  240. }
  241. rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  242. /*
  243. * Enter Command: Initialize Rx Params for SCC
  244. */
  245. do { /* Spin until ready to issue command */
  246. __asm__ ("eieio");
  247. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  248. /* Issue command */
  249. immr->im_cpm.cp_cpcr =
  250. ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
  251. do { /* Spin until command processed */
  252. __asm__ ("eieio");
  253. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  254. /*
  255. * Ethernet Specific Parameter RAM
  256. * see table 13-16, pg. 660,
  257. * pg. 681 (example with suggested settings)
  258. */
  259. pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
  260. pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
  261. pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
  262. pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
  263. pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
  264. pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
  265. pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
  266. pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
  267. pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
  268. pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
  269. pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
  270. pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
  271. pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
  272. pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
  273. pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
  274. #define ea eth_get_ethaddr()
  275. pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
  276. pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
  277. pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
  278. #undef ea
  279. pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
  280. pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
  281. pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
  282. pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
  283. pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
  284. pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
  285. pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
  286. pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
  287. /*
  288. * Enter Command: Initialize Tx Params for SCC
  289. */
  290. do { /* Spin until ready to issue command */
  291. __asm__ ("eieio");
  292. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  293. /* Issue command */
  294. immr->im_cpm.cp_cpcr =
  295. ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
  296. do { /* Spin until command processed */
  297. __asm__ ("eieio");
  298. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  299. /*
  300. * Mask all Events in SCCM - we use polling mode
  301. */
  302. immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
  303. /*
  304. * Clear Events in SCCE -- Clear bits by writing 1's
  305. */
  306. immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
  307. /*
  308. * Initialize GSMR High 32-Bits
  309. * Settings: Normal Mode
  310. */
  311. immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
  312. /*
  313. * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
  314. * Settings:
  315. * TCI = Invert
  316. * TPL = 48 bits
  317. * TPP = Repeating 10's
  318. * MODE = Ethernet
  319. */
  320. immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
  321. SCC_GSMRL_TPL_48 |
  322. SCC_GSMRL_TPP_10 |
  323. SCC_GSMRL_MODE_ENET);
  324. /*
  325. * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
  326. */
  327. immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
  328. /*
  329. * Initialize the PSMR
  330. * Settings:
  331. * CRC = 32-Bit CCITT
  332. * NIB = Begin searching for SFD 22 bits after RENA
  333. * FDE = Full Duplex Enable
  334. * LPB = Loopback Enable (Needed when FDE is set)
  335. * BRO = Reject broadcast packets
  336. * PROMISCOUS = Catch all packets regardless of dest. MAC adress
  337. */
  338. immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
  339. SCC_PSMR_NIB22 |
  340. #if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
  341. SCC_PSMR_FDE | SCC_PSMR_LPB |
  342. #endif
  343. #if defined(CONFIG_SCC_ENET_NO_BROADCAST)
  344. SCC_PSMR_BRO |
  345. #endif
  346. #if defined(CONFIG_SCC_ENET_PROMISCOUS)
  347. SCC_PSMR_PRO |
  348. #endif
  349. 0;
  350. /*
  351. * Configure Ethernet TENA Signal
  352. */
  353. #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
  354. immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
  355. immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
  356. #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
  357. immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
  358. immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
  359. #else
  360. #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
  361. #endif
  362. /*
  363. * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
  364. */
  365. immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
  366. (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  367. return 1;
  368. }
  369. static void scc_halt (struct eth_device *dev)
  370. {
  371. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  372. immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
  373. ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  374. immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  375. }
  376. #if 0
  377. void restart (void)
  378. {
  379. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  380. immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
  381. (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  382. }
  383. #endif
  384. #endif