fec.c 23 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <commproc.h>
  10. #include <malloc.h>
  11. #include <net.h>
  12. #include <phy.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #undef ET_DEBUG
  15. #if defined(CONFIG_CMD_NET) && \
  16. (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
  17. /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
  18. #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
  19. #define CONFIG_ETHER_ON_FEC1 1
  20. #endif
  21. /* define WANT_MII when MII support is required */
  22. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
  23. #define WANT_MII
  24. #else
  25. #undef WANT_MII
  26. #endif
  27. #if defined(WANT_MII)
  28. #include <miiphy.h>
  29. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  30. #error "CONFIG_MII has to be defined!"
  31. #endif
  32. #endif
  33. #if defined(CONFIG_RMII) && !defined(WANT_MII)
  34. #error RMII support is unusable without a working PHY.
  35. #endif
  36. #ifdef CONFIG_SYS_DISCOVER_PHY
  37. static int mii_discover_phy(struct eth_device *dev);
  38. #endif
  39. int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
  40. int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  41. u16 value);
  42. static struct ether_fcc_info_s
  43. {
  44. int ether_index;
  45. int fecp_offset;
  46. int phy_addr;
  47. int actual_phy_addr;
  48. int initialized;
  49. }
  50. ether_fcc_info[] = {
  51. #if defined(CONFIG_ETHER_ON_FEC1)
  52. {
  53. 0,
  54. offsetof(immap_t, im_cpm.cp_fec1),
  55. #if defined(CONFIG_FEC1_PHY)
  56. CONFIG_FEC1_PHY,
  57. #else
  58. -1, /* discover */
  59. #endif
  60. -1,
  61. 0,
  62. },
  63. #endif
  64. #if defined(CONFIG_ETHER_ON_FEC2)
  65. {
  66. 1,
  67. offsetof(immap_t, im_cpm.cp_fec2),
  68. #if defined(CONFIG_FEC2_PHY)
  69. CONFIG_FEC2_PHY,
  70. #else
  71. -1,
  72. #endif
  73. -1,
  74. 0,
  75. },
  76. #endif
  77. };
  78. /* Ethernet Transmit and Receive Buffers */
  79. #define DBUF_LENGTH 1520
  80. #define TX_BUF_CNT 2
  81. #define TOUT_LOOP 100
  82. #define PKT_MAXBUF_SIZE 1518
  83. #define PKT_MINBUF_SIZE 64
  84. #define PKT_MAXBLR_SIZE 1520
  85. #ifdef __GNUC__
  86. static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
  87. #else
  88. #error txbuf must be aligned.
  89. #endif
  90. static uint rxIdx; /* index of the current RX buffer */
  91. static uint txIdx; /* index of the current TX buffer */
  92. /*
  93. * FEC Ethernet Tx and Rx buffer descriptors allocated at the
  94. * immr->udata_bd address on Dual-Port RAM
  95. * Provide for Double Buffering
  96. */
  97. typedef volatile struct CommonBufferDescriptor {
  98. cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
  99. cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  100. } RTXBD;
  101. static RTXBD *rtx = NULL;
  102. static int fec_send(struct eth_device *dev, void *packet, int length);
  103. static int fec_recv(struct eth_device* dev);
  104. static int fec_init(struct eth_device* dev, bd_t * bd);
  105. static void fec_halt(struct eth_device* dev);
  106. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  107. static void __mii_init(void);
  108. #endif
  109. int fec_initialize(bd_t *bis)
  110. {
  111. struct eth_device* dev;
  112. struct ether_fcc_info_s *efis;
  113. int i;
  114. for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
  115. dev = malloc(sizeof(*dev));
  116. if (dev == NULL)
  117. hang();
  118. memset(dev, 0, sizeof(*dev));
  119. /* for FEC1 make sure that the name of the interface is the same
  120. as the old one for compatibility reasons */
  121. if (i == 0) {
  122. strcpy(dev->name, "FEC");
  123. } else {
  124. sprintf (dev->name, "FEC%d",
  125. ether_fcc_info[i].ether_index + 1);
  126. }
  127. efis = &ether_fcc_info[i];
  128. /*
  129. * reset actual phy addr
  130. */
  131. efis->actual_phy_addr = -1;
  132. dev->priv = efis;
  133. dev->init = fec_init;
  134. dev->halt = fec_halt;
  135. dev->send = fec_send;
  136. dev->recv = fec_recv;
  137. eth_register(dev);
  138. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  139. int retval;
  140. struct mii_dev *mdiodev = mdio_alloc();
  141. if (!mdiodev)
  142. return -ENOMEM;
  143. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  144. mdiodev->read = fec8xx_miiphy_read;
  145. mdiodev->write = fec8xx_miiphy_write;
  146. retval = mdio_register(mdiodev);
  147. if (retval < 0)
  148. return retval;
  149. #endif
  150. }
  151. return 1;
  152. }
  153. static int fec_send(struct eth_device *dev, void *packet, int length)
  154. {
  155. int j, rc;
  156. struct ether_fcc_info_s *efis = dev->priv;
  157. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  158. /* section 16.9.23.3
  159. * Wait for ready
  160. */
  161. j = 0;
  162. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
  163. udelay(1);
  164. j++;
  165. }
  166. if (j>=TOUT_LOOP) {
  167. printf("TX not ready\n");
  168. }
  169. rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
  170. rtx->txbd[txIdx].cbd_datlen = length;
  171. rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
  172. __asm__ ("eieio");
  173. /* Activate transmit Buffer Descriptor polling */
  174. fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
  175. j = 0;
  176. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
  177. udelay(1);
  178. j++;
  179. }
  180. if (j>=TOUT_LOOP) {
  181. printf("TX timeout\n");
  182. }
  183. #ifdef ET_DEBUG
  184. printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
  185. __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
  186. (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
  187. #endif
  188. /* return only status bits */;
  189. rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
  190. txIdx = (txIdx + 1) % TX_BUF_CNT;
  191. return rc;
  192. }
  193. static int fec_recv (struct eth_device *dev)
  194. {
  195. struct ether_fcc_info_s *efis = dev->priv;
  196. volatile fec_t *fecp =
  197. (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
  198. int length;
  199. for (;;) {
  200. /* section 16.9.23.2 */
  201. if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  202. length = -1;
  203. break; /* nothing received - leave for() loop */
  204. }
  205. length = rtx->rxbd[rxIdx].cbd_datlen;
  206. if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
  207. #ifdef ET_DEBUG
  208. printf ("%s[%d] err: %x\n",
  209. __FUNCTION__, __LINE__,
  210. rtx->rxbd[rxIdx].cbd_sc);
  211. #endif
  212. } else {
  213. uchar *rx = net_rx_packets[rxIdx];
  214. length -= 4;
  215. #if defined(CONFIG_CMD_CDP)
  216. if ((rx[0] & 1) != 0 &&
  217. memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
  218. !is_cdp_packet((uchar *)rx))
  219. rx = NULL;
  220. #endif
  221. /*
  222. * Pass the packet up to the protocol layers.
  223. */
  224. if (rx != NULL)
  225. net_process_received_packet(rx, length);
  226. }
  227. /* Give the buffer back to the FEC. */
  228. rtx->rxbd[rxIdx].cbd_datlen = 0;
  229. /* wrap around buffer index when necessary */
  230. if ((rxIdx + 1) >= PKTBUFSRX) {
  231. rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
  232. (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  233. rxIdx = 0;
  234. } else {
  235. rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  236. rxIdx++;
  237. }
  238. __asm__ ("eieio");
  239. /* Try to fill Buffer Descriptors */
  240. fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
  241. }
  242. return length;
  243. }
  244. /**************************************************************
  245. *
  246. * FEC Ethernet Initialization Routine
  247. *
  248. *************************************************************/
  249. #define FEC_ECNTRL_PINMUX 0x00000004
  250. #define FEC_ECNTRL_ETHER_EN 0x00000002
  251. #define FEC_ECNTRL_RESET 0x00000001
  252. #define FEC_RCNTRL_BC_REJ 0x00000010
  253. #define FEC_RCNTRL_PROM 0x00000008
  254. #define FEC_RCNTRL_MII_MODE 0x00000004
  255. #define FEC_RCNTRL_DRT 0x00000002
  256. #define FEC_RCNTRL_LOOP 0x00000001
  257. #define FEC_TCNTRL_FDEN 0x00000004
  258. #define FEC_TCNTRL_HBC 0x00000002
  259. #define FEC_TCNTRL_GTS 0x00000001
  260. #define FEC_RESET_DELAY 50
  261. #if defined(CONFIG_RMII)
  262. static inline void fec_10Mbps(struct eth_device *dev)
  263. {
  264. struct ether_fcc_info_s *efis = dev->priv;
  265. int fecidx = efis->ether_index;
  266. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  267. if ((unsigned int)fecidx >= 2)
  268. hang();
  269. ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
  270. }
  271. static inline void fec_100Mbps(struct eth_device *dev)
  272. {
  273. struct ether_fcc_info_s *efis = dev->priv;
  274. int fecidx = efis->ether_index;
  275. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  276. if ((unsigned int)fecidx >= 2)
  277. hang();
  278. ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
  279. }
  280. #endif
  281. static inline void fec_full_duplex(struct eth_device *dev)
  282. {
  283. struct ether_fcc_info_s *efis = dev->priv;
  284. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  285. fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
  286. fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
  287. }
  288. static inline void fec_half_duplex(struct eth_device *dev)
  289. {
  290. struct ether_fcc_info_s *efis = dev->priv;
  291. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  292. fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
  293. fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
  294. }
  295. static void fec_pin_init(int fecidx)
  296. {
  297. bd_t *bd = gd->bd;
  298. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  299. /*
  300. * Set MII speed to 2.5 MHz or slightly below.
  301. *
  302. * According to the MPC860T (Rev. D) Fast ethernet controller user
  303. * manual (6.2.14),
  304. * the MII management interface clock must be less than or equal
  305. * to 2.5 MHz.
  306. * This MDC frequency is equal to system clock / (2 * MII_SPEED).
  307. * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
  308. *
  309. * All MII configuration is done via FEC1 registers:
  310. */
  311. immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
  312. #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
  313. /* use MDC for MII */
  314. immr->im_ioport.iop_pdpar |= 0x0080;
  315. immr->im_ioport.iop_pddir &= ~0x0080;
  316. #endif
  317. if (fecidx == 0) {
  318. #if defined(CONFIG_ETHER_ON_FEC1)
  319. #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
  320. #if !defined(CONFIG_RMII)
  321. immr->im_ioport.iop_papar |= 0xf830;
  322. immr->im_ioport.iop_padir |= 0x0830;
  323. immr->im_ioport.iop_padir &= ~0xf000;
  324. immr->im_cpm.cp_pbpar |= 0x00001001;
  325. immr->im_cpm.cp_pbdir &= ~0x00001001;
  326. immr->im_ioport.iop_pcpar |= 0x000c;
  327. immr->im_ioport.iop_pcdir &= ~0x000c;
  328. immr->im_cpm.cp_pepar |= 0x00000003;
  329. immr->im_cpm.cp_pedir |= 0x00000003;
  330. immr->im_cpm.cp_peso &= ~0x00000003;
  331. immr->im_cpm.cp_cptr &= ~0x00000100;
  332. #else
  333. #if !defined(CONFIG_FEC1_PHY_NORXERR)
  334. immr->im_ioport.iop_papar |= 0x1000;
  335. immr->im_ioport.iop_padir &= ~0x1000;
  336. #endif
  337. immr->im_ioport.iop_papar |= 0xe810;
  338. immr->im_ioport.iop_padir |= 0x0810;
  339. immr->im_ioport.iop_padir &= ~0xe000;
  340. immr->im_cpm.cp_pbpar |= 0x00000001;
  341. immr->im_cpm.cp_pbdir &= ~0x00000001;
  342. immr->im_cpm.cp_cptr |= 0x00000100;
  343. immr->im_cpm.cp_cptr &= ~0x00000050;
  344. #endif /* !CONFIG_RMII */
  345. #else
  346. /*
  347. * Configure all of port D for MII.
  348. */
  349. immr->im_ioport.iop_pdpar = 0x1fff;
  350. /*
  351. * Bits moved from Rev. D onward
  352. */
  353. if ((get_immr(0) & 0xffff) < 0x0501)
  354. immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
  355. else
  356. immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
  357. #endif
  358. #endif /* CONFIG_ETHER_ON_FEC1 */
  359. } else if (fecidx == 1) {
  360. #if defined(CONFIG_ETHER_ON_FEC2)
  361. #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
  362. #if !defined(CONFIG_RMII)
  363. immr->im_cpm.cp_pepar |= 0x0003fffc;
  364. immr->im_cpm.cp_pedir |= 0x0003fffc;
  365. immr->im_cpm.cp_peso &= ~0x000087fc;
  366. immr->im_cpm.cp_peso |= 0x00037800;
  367. immr->im_cpm.cp_cptr &= ~0x00000080;
  368. #else
  369. #if !defined(CONFIG_FEC2_PHY_NORXERR)
  370. immr->im_cpm.cp_pepar |= 0x00000010;
  371. immr->im_cpm.cp_pedir |= 0x00000010;
  372. immr->im_cpm.cp_peso &= ~0x00000010;
  373. #endif
  374. immr->im_cpm.cp_pepar |= 0x00039620;
  375. immr->im_cpm.cp_pedir |= 0x00039620;
  376. immr->im_cpm.cp_peso |= 0x00031000;
  377. immr->im_cpm.cp_peso &= ~0x00008620;
  378. immr->im_cpm.cp_cptr |= 0x00000080;
  379. immr->im_cpm.cp_cptr &= ~0x00000028;
  380. #endif /* CONFIG_RMII */
  381. #endif /* CONFIG_MPC885_FAMILY */
  382. #endif /* CONFIG_ETHER_ON_FEC2 */
  383. }
  384. }
  385. static int fec_reset(volatile fec_t *fecp)
  386. {
  387. int i;
  388. /* Whack a reset.
  389. * A delay is required between a reset of the FEC block and
  390. * initialization of other FEC registers because the reset takes
  391. * some time to complete. If you don't delay, subsequent writes
  392. * to FEC registers might get killed by the reset routine which is
  393. * still in progress.
  394. */
  395. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
  396. for (i = 0;
  397. (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
  398. ++i) {
  399. udelay (1);
  400. }
  401. if (i == FEC_RESET_DELAY)
  402. return -1;
  403. return 0;
  404. }
  405. static int fec_init (struct eth_device *dev, bd_t * bd)
  406. {
  407. struct ether_fcc_info_s *efis = dev->priv;
  408. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  409. volatile fec_t *fecp =
  410. (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
  411. int i;
  412. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  413. /* the MII interface is connected to FEC1
  414. * so for the miiphy_xxx function to work we must
  415. * call mii_init since fec_halt messes the thing up
  416. */
  417. if (efis->ether_index != 0)
  418. __mii_init();
  419. #endif
  420. if (fec_reset(fecp) < 0)
  421. printf ("FEC_RESET_DELAY timeout\n");
  422. /* We use strictly polling mode only
  423. */
  424. fecp->fec_imask = 0;
  425. /* Clear any pending interrupt
  426. */
  427. fecp->fec_ievent = 0xffc0;
  428. /* No need to set the IVEC register */
  429. /* Set station address
  430. */
  431. #define ea dev->enetaddr
  432. fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
  433. fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
  434. #undef ea
  435. #if defined(CONFIG_CMD_CDP)
  436. /*
  437. * Turn on multicast address hash table
  438. */
  439. fecp->fec_hash_table_high = 0xffffffff;
  440. fecp->fec_hash_table_low = 0xffffffff;
  441. #else
  442. /* Clear multicast address hash table
  443. */
  444. fecp->fec_hash_table_high = 0;
  445. fecp->fec_hash_table_low = 0;
  446. #endif
  447. /* Set maximum receive buffer size.
  448. */
  449. fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
  450. /* Set maximum frame length
  451. */
  452. fecp->fec_r_hash = PKT_MAXBUF_SIZE;
  453. /*
  454. * Setup Buffers and Buffer Desriptors
  455. */
  456. rxIdx = 0;
  457. txIdx = 0;
  458. if (!rtx)
  459. rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
  460. /*
  461. * Setup Receiver Buffer Descriptors (13.14.24.18)
  462. * Settings:
  463. * Empty, Wrap
  464. */
  465. for (i = 0; i < PKTBUFSRX; i++) {
  466. rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  467. rtx->rxbd[i].cbd_datlen = 0; /* Reset */
  468. rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
  469. }
  470. rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  471. /*
  472. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  473. * Settings:
  474. * Last, Tx CRC
  475. */
  476. for (i = 0; i < TX_BUF_CNT; i++) {
  477. rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
  478. rtx->txbd[i].cbd_datlen = 0; /* Reset */
  479. rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
  480. }
  481. rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  482. /* Set receive and transmit descriptor base
  483. */
  484. fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
  485. fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
  486. /* Enable MII mode
  487. */
  488. #if 0 /* Full duplex mode */
  489. fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
  490. fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
  491. #else /* Half duplex mode */
  492. fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
  493. fecp->fec_x_cntrl = 0;
  494. #endif
  495. /* Enable big endian and don't care about SDMA FC.
  496. */
  497. fecp->fec_fun_code = 0x78000000;
  498. /*
  499. * Setup the pin configuration of the FEC
  500. */
  501. fec_pin_init (efis->ether_index);
  502. rxIdx = 0;
  503. txIdx = 0;
  504. /*
  505. * Now enable the transmit and receive processing
  506. */
  507. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
  508. if (efis->phy_addr == -1) {
  509. #ifdef CONFIG_SYS_DISCOVER_PHY
  510. /*
  511. * wait for the PHY to wake up after reset
  512. */
  513. efis->actual_phy_addr = mii_discover_phy (dev);
  514. if (efis->actual_phy_addr == -1) {
  515. printf ("Unable to discover phy!\n");
  516. return -1;
  517. }
  518. #else
  519. efis->actual_phy_addr = -1;
  520. #endif
  521. } else {
  522. efis->actual_phy_addr = efis->phy_addr;
  523. }
  524. #if defined(CONFIG_MII) && defined(CONFIG_RMII)
  525. /*
  526. * adapt the RMII speed to the speed of the phy
  527. */
  528. if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
  529. fec_100Mbps (dev);
  530. } else {
  531. fec_10Mbps (dev);
  532. }
  533. #endif
  534. #if defined(CONFIG_MII)
  535. /*
  536. * adapt to the half/full speed settings
  537. */
  538. if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
  539. fec_full_duplex (dev);
  540. } else {
  541. fec_half_duplex (dev);
  542. }
  543. #endif
  544. /* And last, try to fill Rx Buffer Descriptors */
  545. fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
  546. efis->initialized = 1;
  547. return 0;
  548. }
  549. static void fec_halt(struct eth_device* dev)
  550. {
  551. struct ether_fcc_info_s *efis = dev->priv;
  552. volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  553. int i;
  554. /* avoid halt if initialized; mii gets stuck otherwise */
  555. if (!efis->initialized)
  556. return;
  557. /* Whack a reset.
  558. * A delay is required between a reset of the FEC block and
  559. * initialization of other FEC registers because the reset takes
  560. * some time to complete. If you don't delay, subsequent writes
  561. * to FEC registers might get killed by the reset routine which is
  562. * still in progress.
  563. */
  564. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
  565. for (i = 0;
  566. (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
  567. ++i) {
  568. udelay (1);
  569. }
  570. if (i == FEC_RESET_DELAY) {
  571. printf ("FEC_RESET_DELAY timeout\n");
  572. return;
  573. }
  574. efis->initialized = 0;
  575. }
  576. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  577. /* Make MII read/write commands for the FEC.
  578. */
  579. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
  580. (REG & 0x1f) << 18))
  581. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
  582. (REG & 0x1f) << 18) | \
  583. (VAL & 0xffff))
  584. /* Interrupt events/masks.
  585. */
  586. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  587. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  588. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  589. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  590. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  591. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  592. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  593. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  594. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  595. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  596. /* PHY identification
  597. */
  598. #define PHY_ID_LXT970 0x78100000 /* LXT970 */
  599. #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
  600. #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
  601. #define PHY_ID_QS6612 0x01814400 /* QS6612 */
  602. #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
  603. #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
  604. #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
  605. #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
  606. #define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
  607. /* send command to phy using mii, wait for result */
  608. static uint
  609. mii_send(uint mii_cmd)
  610. {
  611. uint mii_reply;
  612. volatile fec_t *ep;
  613. int cnt;
  614. ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
  615. ep->fec_mii_data = mii_cmd; /* command to phy */
  616. /* wait for mii complete */
  617. cnt = 0;
  618. while (!(ep->fec_ievent & FEC_ENET_MII)) {
  619. if (++cnt > 1000) {
  620. printf("mii_send STUCK!\n");
  621. break;
  622. }
  623. }
  624. mii_reply = ep->fec_mii_data; /* result from phy */
  625. ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
  626. #if 0
  627. printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
  628. __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
  629. #endif
  630. return (mii_reply & 0xffff); /* data read from phy */
  631. }
  632. #endif
  633. #if defined(CONFIG_SYS_DISCOVER_PHY)
  634. static int mii_discover_phy(struct eth_device *dev)
  635. {
  636. #define MAX_PHY_PASSES 11
  637. uint phyno;
  638. int pass;
  639. uint phytype;
  640. int phyaddr;
  641. phyaddr = -1; /* didn't find a PHY yet */
  642. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  643. if (pass > 1) {
  644. /* PHY may need more time to recover from reset.
  645. * The LXT970 needs 50ms typical, no maximum is
  646. * specified, so wait 10ms before try again.
  647. * With 11 passes this gives it 100ms to wake up.
  648. */
  649. udelay(10000); /* wait 10ms */
  650. }
  651. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  652. phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
  653. #ifdef ET_DEBUG
  654. printf("PHY type 0x%x pass %d type ", phytype, pass);
  655. #endif
  656. if (phytype != 0xffff) {
  657. phyaddr = phyno;
  658. phytype |= mii_send(mk_mii_read(phyno,
  659. MII_PHYSID1)) << 16;
  660. #ifdef ET_DEBUG
  661. printf("PHY @ 0x%x pass %d type ",phyno,pass);
  662. switch (phytype & 0xfffffff0) {
  663. case PHY_ID_LXT970:
  664. printf("LXT970\n");
  665. break;
  666. case PHY_ID_LXT971:
  667. printf("LXT971\n");
  668. break;
  669. case PHY_ID_82555:
  670. printf("82555\n");
  671. break;
  672. case PHY_ID_QS6612:
  673. printf("QS6612\n");
  674. break;
  675. case PHY_ID_AMD79C784:
  676. printf("AMD79C784\n");
  677. break;
  678. case PHY_ID_LSI80225B:
  679. printf("LSI L80225/B\n");
  680. break;
  681. case PHY_ID_DM9161:
  682. printf("Davicom DM9161\n");
  683. break;
  684. case PHY_ID_KSM8995M:
  685. printf("MICREL KS8995M\n");
  686. break;
  687. default:
  688. printf("0x%08x\n", phytype);
  689. break;
  690. }
  691. #endif
  692. }
  693. }
  694. }
  695. if (phyaddr < 0) {
  696. printf("No PHY device found.\n");
  697. }
  698. return phyaddr;
  699. }
  700. #endif /* CONFIG_SYS_DISCOVER_PHY */
  701. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
  702. /****************************************************************************
  703. * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
  704. * This function is a subset of eth_init
  705. ****************************************************************************
  706. */
  707. static void __mii_init(void)
  708. {
  709. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  710. volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
  711. if (fec_reset(fecp) < 0)
  712. printf ("FEC_RESET_DELAY timeout\n");
  713. /* We use strictly polling mode only
  714. */
  715. fecp->fec_imask = 0;
  716. /* Clear any pending interrupt
  717. */
  718. fecp->fec_ievent = 0xffc0;
  719. /* Now enable the transmit and receive processing
  720. */
  721. fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
  722. }
  723. void mii_init (void)
  724. {
  725. int i;
  726. __mii_init();
  727. /* Setup the pin configuration of the FEC(s)
  728. */
  729. for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
  730. fec_pin_init(ether_fcc_info[i].ether_index);
  731. }
  732. /*****************************************************************************
  733. * Read and write a MII PHY register, routines used by MII Utilities
  734. *
  735. * FIXME: These routines are expected to return 0 on success, but mii_send
  736. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  737. * no PHY connected...
  738. * For now always return 0.
  739. * FIXME: These routines only work after calling eth_init() at least once!
  740. * Otherwise they hang in mii_send() !!! Sorry!
  741. *****************************************************************************/
  742. int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  743. {
  744. unsigned short value = 0;
  745. short rdreg; /* register working value */
  746. #ifdef MII_DEBUG
  747. printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
  748. #endif
  749. rdreg = mii_send(mk_mii_read(addr, reg));
  750. value = rdreg;
  751. #ifdef MII_DEBUG
  752. printf ("0x%04x\n", value);
  753. #endif
  754. return value;
  755. }
  756. int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  757. u16 value)
  758. {
  759. #ifdef MII_DEBUG
  760. printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
  761. #endif
  762. (void)mii_send(mk_mii_write(addr, reg, value));
  763. #ifdef MII_DEBUG
  764. printf ("0x%04x\n", value);
  765. #endif
  766. return 0;
  767. }
  768. #endif
  769. #endif