cpu.c 13 KB

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  1. /*
  2. * (C) Copyright 2000-2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * m8xx.c
  9. *
  10. * CPU specific code
  11. *
  12. * written or collected and sometimes rewritten by
  13. * Magnus Damm <damm@bitsmart.com>
  14. *
  15. * minor modifications by
  16. * Wolfgang Denk <wd@denx.de>
  17. */
  18. #include <common.h>
  19. #include <watchdog.h>
  20. #include <command.h>
  21. #include <mpc8xx.h>
  22. #include <commproc.h>
  23. #include <netdev.h>
  24. #include <asm/cache.h>
  25. #include <linux/compiler.h>
  26. #include <asm/io.h>
  27. #if defined(CONFIG_OF_LIBFDT)
  28. #include <libfdt.h>
  29. #include <fdt_support.h>
  30. #endif
  31. DECLARE_GLOBAL_DATA_PTR;
  32. static char *cpu_warning = "\n " \
  33. "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
  34. #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
  35. !defined(CONFIG_MPC862))
  36. static int check_CPU (long clock, uint pvr, uint immr)
  37. {
  38. char *id_str =
  39. # if defined(CONFIG_MPC855)
  40. "PC855";
  41. # elif defined(CONFIG_MPC860P)
  42. "PC860P";
  43. # else
  44. NULL;
  45. # endif
  46. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  47. uint k, m;
  48. char buf[32];
  49. char pre = 'X';
  50. char *mid = "xx";
  51. char *suf;
  52. /* the highest 16 bits should be 0x0050 for a 860 */
  53. if ((pvr >> 16) != 0x0050)
  54. return -1;
  55. k = (immr << 16) |
  56. immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
  57. m = 0;
  58. suf = "";
  59. /*
  60. * Some boards use sockets so different CPUs can be used.
  61. * We have to check chip version in run time.
  62. */
  63. switch (k) {
  64. case 0x00020001: pre = 'P'; break;
  65. case 0x00030001: break;
  66. case 0x00120003: suf = "A"; break;
  67. case 0x00130003: suf = "A3"; break;
  68. case 0x00200004: suf = "B"; break;
  69. case 0x00300004: suf = "C"; break;
  70. case 0x00310004: suf = "C1"; m = 1; break;
  71. case 0x00200064: mid = "SR"; suf = "B"; break;
  72. case 0x00300065: mid = "SR"; suf = "C"; break;
  73. case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
  74. case 0x05010000: suf = "D3"; m = 1; break;
  75. case 0x05020000: suf = "D4"; m = 1; break;
  76. /* this value is not documented anywhere */
  77. case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
  78. /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
  79. case 0x08010004: /* Rev. A.0 */
  80. suf = "A";
  81. /* fall through */
  82. case 0x08000003: /* Rev. 0.3 */
  83. pre = 'M'; m = 1;
  84. if (id_str == NULL)
  85. id_str =
  86. # if defined(CONFIG_MPC859T)
  87. "PC859T";
  88. # else
  89. "PC866x"; /* Unknown chip from MPC866 family */
  90. # endif
  91. break;
  92. case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
  93. if (id_str == NULL)
  94. id_str = "PC885"; /* 870/875/880/885 */
  95. break;
  96. default: suf = NULL; break;
  97. }
  98. if (id_str == NULL)
  99. id_str = "PC86x"; /* Unknown 86x chip */
  100. if (suf)
  101. printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
  102. else
  103. printf ("unknown M%s (0x%08x)", id_str, k);
  104. #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
  105. printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
  106. strmhz (buf, clock),
  107. CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
  108. ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
  109. CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
  110. ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
  111. );
  112. #else
  113. printf (" at %s MHz: ", strmhz (buf, clock));
  114. #endif
  115. print_size(checkicache(), " I-Cache ");
  116. print_size(checkdcache(), " D-Cache");
  117. /* do we have a FEC (860T/P or 852/859/866/885)? */
  118. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  119. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  120. printf (" FEC present");
  121. }
  122. if (!m) {
  123. puts (cpu_warning);
  124. }
  125. putc ('\n');
  126. #ifdef DEBUG
  127. if(clock != measure_gclk()) {
  128. printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
  129. }
  130. #endif
  131. return 0;
  132. }
  133. #elif defined(CONFIG_MPC862)
  134. static int check_CPU (long clock, uint pvr, uint immr)
  135. {
  136. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  137. uint k, m;
  138. char buf[32];
  139. char pre = 'X';
  140. __maybe_unused char *mid = "xx";
  141. char *suf;
  142. /* the highest 16 bits should be 0x0050 for a 8xx */
  143. if ((pvr >> 16) != 0x0050)
  144. return -1;
  145. k = (immr << 16) |
  146. immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
  147. m = 0;
  148. switch (k) {
  149. /* this value is not documented anywhere */
  150. case 0x06000000: mid = "P"; suf = "0"; break;
  151. case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
  152. case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
  153. default: suf = NULL; break;
  154. }
  155. #ifndef CONFIG_MPC857
  156. if (suf)
  157. printf ("%cPC862%sZPnn%s", pre, mid, suf);
  158. else
  159. printf ("unknown MPC862 (0x%08x)", k);
  160. #else
  161. if (suf)
  162. printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
  163. else
  164. printf ("unknown MPC857 (0x%08x)", k);
  165. #endif
  166. printf(" at %s MHz: ", strmhz(buf, clock));
  167. print_size(checkicache(), " I-Cache ");
  168. print_size(checkdcache(), " D-Cache");
  169. /* lets check and see if we're running on a 862T (or P?) */
  170. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  171. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  172. printf (" FEC present");
  173. }
  174. if (!m) {
  175. puts (cpu_warning);
  176. }
  177. putc ('\n');
  178. return 0;
  179. }
  180. #elif defined(CONFIG_MPC823)
  181. static int check_CPU (long clock, uint pvr, uint immr)
  182. {
  183. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  184. uint k, m;
  185. char buf[32];
  186. char *suf;
  187. /* the highest 16 bits should be 0x0050 for a 8xx */
  188. if ((pvr >> 16) != 0x0050)
  189. return -1;
  190. k = (immr << 16) |
  191. in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
  192. m = 0;
  193. switch (k) {
  194. /* MPC823 */
  195. case 0x20000000: suf = "0"; break;
  196. case 0x20010000: suf = "0.1"; break;
  197. case 0x20020000: suf = "Z2/3"; break;
  198. case 0x20020001: suf = "Z3"; break;
  199. case 0x21000000: suf = "A"; break;
  200. case 0x21010000: suf = "B"; m = 1; break;
  201. case 0x21010001: suf = "B2"; m = 1; break;
  202. /* MPC823E */
  203. case 0x24010000: suf = NULL;
  204. puts ("PPC823EZTnnB2");
  205. m = 1;
  206. break;
  207. default:
  208. suf = NULL;
  209. printf ("unknown MPC823 (0x%08x)", k);
  210. break;
  211. }
  212. if (suf)
  213. printf ("PPC823ZTnn%s", suf);
  214. printf(" at %s MHz: ", strmhz(buf, clock));
  215. print_size(checkicache(), " I-Cache ");
  216. print_size(checkdcache(), " D-Cache");
  217. /* lets check and see if we're running on a 860T (or P?) */
  218. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  219. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  220. puts (" FEC present");
  221. }
  222. if (!m) {
  223. puts (cpu_warning);
  224. }
  225. putc ('\n');
  226. return 0;
  227. }
  228. #elif defined(CONFIG_MPC850)
  229. static int check_CPU (long clock, uint pvr, uint immr)
  230. {
  231. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  232. uint k, m;
  233. char buf[32];
  234. /* the highest 16 bits should be 0x0050 for a 8xx */
  235. if ((pvr >> 16) != 0x0050)
  236. return -1;
  237. k = (immr << 16) |
  238. immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
  239. m = 0;
  240. switch (k) {
  241. case 0x20020001:
  242. printf ("XPC850xxZT");
  243. break;
  244. case 0x21000065:
  245. printf ("XPC850xxZTA");
  246. break;
  247. case 0x21010067:
  248. printf ("XPC850xxZTB");
  249. m = 1;
  250. break;
  251. case 0x21020068:
  252. printf ("XPC850xxZTC");
  253. m = 1;
  254. break;
  255. default:
  256. printf ("unknown MPC850 (0x%08x)", k);
  257. }
  258. printf(" at %s MHz: ", strmhz(buf, clock));
  259. print_size(checkicache(), " I-Cache ");
  260. print_size(checkdcache(), " D-Cache");
  261. /* lets check and see if we're running on a 850T (or P?) */
  262. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  263. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  264. printf (" FEC present");
  265. }
  266. if (!m) {
  267. puts (cpu_warning);
  268. }
  269. putc ('\n');
  270. return 0;
  271. }
  272. #else
  273. #error CPU undefined
  274. #endif
  275. /* ------------------------------------------------------------------------- */
  276. int checkcpu (void)
  277. {
  278. ulong clock = gd->cpu_clk;
  279. uint immr = get_immr (0); /* Return full IMMR contents */
  280. uint pvr = get_pvr ();
  281. puts ("CPU: ");
  282. /* 850 has PARTNUM 20 */
  283. /* 801 has PARTNUM 10 */
  284. return check_CPU (clock, pvr, immr);
  285. }
  286. /* ------------------------------------------------------------------------- */
  287. /* L1 i-cache */
  288. /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
  289. /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
  290. int checkicache (void)
  291. {
  292. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  293. volatile memctl8xx_t *memctl = &immap->im_memctl;
  294. u32 cacheon = rd_ic_cst () & IDC_ENABLED;
  295. #ifdef CONFIG_IP86x
  296. u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
  297. #else
  298. u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
  299. #endif
  300. u32 m;
  301. u32 lines = -1;
  302. wr_ic_cst (IDC_UNALL);
  303. wr_ic_cst (IDC_INVALL);
  304. wr_ic_cst (IDC_DISABLE);
  305. __asm__ volatile ("isync");
  306. while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
  307. wr_ic_adr (k);
  308. wr_ic_cst (IDC_LDLCK);
  309. __asm__ volatile ("isync");
  310. lines++;
  311. k += 0x10; /* the number of bytes in a cacheline */
  312. }
  313. wr_ic_cst (IDC_UNALL);
  314. wr_ic_cst (IDC_INVALL);
  315. if (cacheon)
  316. wr_ic_cst (IDC_ENABLE);
  317. else
  318. wr_ic_cst (IDC_DISABLE);
  319. __asm__ volatile ("isync");
  320. return lines << 4;
  321. };
  322. /* ------------------------------------------------------------------------- */
  323. /* L1 d-cache */
  324. /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
  325. /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
  326. /* call with cache disabled */
  327. int checkdcache (void)
  328. {
  329. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  330. volatile memctl8xx_t *memctl = &immap->im_memctl;
  331. u32 cacheon = rd_dc_cst () & IDC_ENABLED;
  332. #ifdef CONFIG_IP86x
  333. u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
  334. #else
  335. u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
  336. #endif
  337. u32 m;
  338. u32 lines = -1;
  339. wr_dc_cst (IDC_UNALL);
  340. wr_dc_cst (IDC_INVALL);
  341. wr_dc_cst (IDC_DISABLE);
  342. while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
  343. wr_dc_adr (k);
  344. wr_dc_cst (IDC_LDLCK);
  345. lines++;
  346. k += 0x10; /* the number of bytes in a cacheline */
  347. }
  348. wr_dc_cst (IDC_UNALL);
  349. wr_dc_cst (IDC_INVALL);
  350. if (cacheon)
  351. wr_dc_cst (IDC_ENABLE);
  352. else
  353. wr_dc_cst (IDC_DISABLE);
  354. return lines << 4;
  355. };
  356. /* ------------------------------------------------------------------------- */
  357. void upmconfig (uint upm, uint * table, uint size)
  358. {
  359. uint i;
  360. uint addr = 0;
  361. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  362. volatile memctl8xx_t *memctl = &immap->im_memctl;
  363. for (i = 0; i < size; i++) {
  364. memctl->memc_mdr = table[i]; /* (16-15) */
  365. memctl->memc_mcr = addr | upm; /* (16-16) */
  366. addr++;
  367. }
  368. }
  369. /* ------------------------------------------------------------------------- */
  370. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  371. {
  372. ulong msr, addr;
  373. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  374. immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
  375. /* Interrupts and MMU off */
  376. __asm__ volatile ("mtspr 81, 0");
  377. __asm__ volatile ("mfmsr %0":"=r" (msr));
  378. msr &= ~0x1030;
  379. __asm__ volatile ("mtmsr %0"::"r" (msr));
  380. /*
  381. * Trying to execute the next instruction at a non-existing address
  382. * should cause a machine check, resulting in reset
  383. */
  384. #ifdef CONFIG_SYS_RESET_ADDRESS
  385. addr = CONFIG_SYS_RESET_ADDRESS;
  386. #else
  387. /*
  388. * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
  389. * - sizeof (ulong) is usually a valid address. Better pick an address
  390. * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
  391. * "(ulong)-1" used to be a good choice for many systems...
  392. */
  393. addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
  394. #endif
  395. ((void (*)(void)) addr) ();
  396. return 1;
  397. }
  398. /* ------------------------------------------------------------------------- */
  399. /*
  400. * Get timebase clock frequency (like cpu_clk in Hz)
  401. *
  402. * See sections 14.2 and 14.6 of the User's Manual
  403. */
  404. unsigned long get_tbclk (void)
  405. {
  406. uint immr = get_immr (0); /* Return full IMMR contents */
  407. volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
  408. ulong oscclk, factor, pll;
  409. if (immap->im_clkrst.car_sccr & SCCR_TBS) {
  410. return (gd->cpu_clk / 16);
  411. }
  412. pll = immap->im_clkrst.car_plprcr;
  413. #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
  414. /*
  415. * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
  416. * factor is calculated as follows:
  417. *
  418. * MFN
  419. * MFI + -------
  420. * MFD + 1
  421. * factor = -----------------
  422. * (PDF + 1) * 2^S
  423. *
  424. * For older chips, it's just MF field of PLPRCR plus one.
  425. */
  426. if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
  427. factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
  428. (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
  429. } else {
  430. factor = PLPRCR_val(MF)+1;
  431. }
  432. oscclk = gd->cpu_clk / factor;
  433. if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
  434. return (oscclk / 4);
  435. }
  436. return (oscclk / 16);
  437. }
  438. /* ------------------------------------------------------------------------- */
  439. #if defined(CONFIG_WATCHDOG)
  440. void watchdog_reset (void)
  441. {
  442. int re_enable = disable_interrupts ();
  443. reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
  444. if (re_enable)
  445. enable_interrupts ();
  446. }
  447. #endif /* CONFIG_WATCHDOG */
  448. #if defined(CONFIG_WATCHDOG)
  449. void reset_8xx_watchdog (volatile immap_t * immr)
  450. {
  451. /*
  452. * All other boards use the MPC8xx Internal Watchdog
  453. */
  454. immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
  455. immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
  456. }
  457. #endif /* CONFIG_WATCHDOG */
  458. /*
  459. * Initializes on-chip ethernet controllers.
  460. * to override, implement board_eth_init()
  461. */
  462. int cpu_eth_init(bd_t *bis)
  463. {
  464. #if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
  465. scc_initialize(bis);
  466. #endif
  467. #if defined(FEC_ENET)
  468. fec_initialize(bis);
  469. #endif
  470. return 0;
  471. }