omap3_spi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
  4. * Christophe Ricard <christophe.ricard@gmail.com>
  5. *
  6. * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
  7. *
  8. * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
  9. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  10. *
  11. * Copyright (C) 2007 Atmel Corporation
  12. *
  13. * Parts taken from linux/drivers/spi/omap2_mcspi.c
  14. * Copyright (C) 2005, 2006 Nokia Corporation
  15. *
  16. * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <spi.h>
  21. #include <malloc.h>
  22. #include <asm/io.h>
  23. #include <linux/bitops.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define OMAP4_MCSPI_REG_OFFSET 0x100
  26. struct omap2_mcspi_platform_config {
  27. unsigned int regs_offset;
  28. };
  29. /* per-register bitmasks */
  30. #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
  31. #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
  32. #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
  33. #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
  34. #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
  35. #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
  36. #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
  37. #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
  38. #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
  39. #define OMAP3_MCSPI_CHCONF_POL BIT(1)
  40. #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
  41. #define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
  42. #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
  43. #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
  44. #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
  45. #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
  46. #define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
  47. #define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
  48. #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
  49. #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
  50. #define OMAP3_MCSPI_CHCONF_IS BIT(18)
  51. #define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
  52. #define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
  53. #define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
  54. #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
  55. #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
  56. #define OMAP3_MCSPI_CHCTRL_EN BIT(0)
  57. #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
  58. #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
  59. #define MCSPI_PINDIR_D0_IN_D1_OUT 0
  60. #define MCSPI_PINDIR_D0_OUT_D1_IN 1
  61. #define OMAP3_MCSPI_MAX_FREQ 48000000
  62. #define SPI_WAIT_TIMEOUT 10
  63. /* OMAP3 McSPI registers */
  64. struct mcspi_channel {
  65. unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
  66. unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
  67. unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
  68. unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
  69. unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
  70. };
  71. struct mcspi {
  72. unsigned char res1[0x10];
  73. unsigned int sysconfig; /* 0x10 */
  74. unsigned int sysstatus; /* 0x14 */
  75. unsigned int irqstatus; /* 0x18 */
  76. unsigned int irqenable; /* 0x1C */
  77. unsigned int wakeupenable; /* 0x20 */
  78. unsigned int syst; /* 0x24 */
  79. unsigned int modulctrl; /* 0x28 */
  80. struct mcspi_channel channel[4];
  81. /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
  82. /* channel1: 0x40 - 0x50, bus 0 & 1 */
  83. /* channel2: 0x54 - 0x64, bus 0 & 1 */
  84. /* channel3: 0x68 - 0x78, bus 0 */
  85. };
  86. struct omap3_spi_priv {
  87. struct mcspi *regs;
  88. unsigned int cs;
  89. unsigned int freq;
  90. unsigned int mode;
  91. unsigned int wordlen;
  92. unsigned int pin_dir:1;
  93. };
  94. static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
  95. {
  96. writel(val, &priv->regs->channel[priv->cs].chconf);
  97. /* Flash post writes to make immediate effect */
  98. readl(&priv->regs->channel[priv->cs].chconf);
  99. }
  100. static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
  101. {
  102. writel(enable, &priv->regs->channel[priv->cs].chctrl);
  103. /* Flash post writes to make immediate effect */
  104. readl(&priv->regs->channel[priv->cs].chctrl);
  105. }
  106. static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
  107. const void *txp, unsigned long flags)
  108. {
  109. ulong start;
  110. int i, chconf;
  111. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  112. /* Enable the channel */
  113. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  114. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  115. chconf |= (priv->wordlen - 1) << 7;
  116. chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
  117. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  118. omap3_spi_write_chconf(priv, chconf);
  119. for (i = 0; i < len; i++) {
  120. /* wait till TX register is empty (TXS == 1) */
  121. start = get_timer(0);
  122. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  123. OMAP3_MCSPI_CHSTAT_TXS)) {
  124. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  125. printf("SPI TXS timed out, status=0x%08x\n",
  126. readl(&priv->regs->channel[priv->cs].chstat));
  127. return -1;
  128. }
  129. }
  130. /* Write the data */
  131. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  132. if (priv->wordlen > 16)
  133. writel(((u32 *)txp)[i], tx);
  134. else if (priv->wordlen > 8)
  135. writel(((u16 *)txp)[i], tx);
  136. else
  137. writel(((u8 *)txp)[i], tx);
  138. }
  139. /* wait to finish of transfer */
  140. while ((readl(&priv->regs->channel[priv->cs].chstat) &
  141. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
  142. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
  143. ;
  144. /* Disable the channel otherwise the next immediate RX will get affected */
  145. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  146. if (flags & SPI_XFER_END) {
  147. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  148. omap3_spi_write_chconf(priv, chconf);
  149. }
  150. return 0;
  151. }
  152. static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
  153. void *rxp, unsigned long flags)
  154. {
  155. int i, chconf;
  156. ulong start;
  157. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  158. /* Enable the channel */
  159. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  160. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  161. chconf |= (priv->wordlen - 1) << 7;
  162. chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
  163. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  164. omap3_spi_write_chconf(priv, chconf);
  165. writel(0, &priv->regs->channel[priv->cs].tx);
  166. for (i = 0; i < len; i++) {
  167. start = get_timer(0);
  168. /* Wait till RX register contains data (RXS == 1) */
  169. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  170. OMAP3_MCSPI_CHSTAT_RXS)) {
  171. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  172. printf("SPI RXS timed out, status=0x%08x\n",
  173. readl(&priv->regs->channel[priv->cs].chstat));
  174. return -1;
  175. }
  176. }
  177. /* Disable the channel to prevent furher receiving */
  178. if (i == (len - 1))
  179. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  180. /* Read the data */
  181. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  182. if (priv->wordlen > 16)
  183. ((u32 *)rxp)[i] = readl(rx);
  184. else if (priv->wordlen > 8)
  185. ((u16 *)rxp)[i] = (u16)readl(rx);
  186. else
  187. ((u8 *)rxp)[i] = (u8)readl(rx);
  188. }
  189. if (flags & SPI_XFER_END) {
  190. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  191. omap3_spi_write_chconf(priv, chconf);
  192. }
  193. return 0;
  194. }
  195. /*McSPI Transmit Receive Mode*/
  196. static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
  197. const void *txp, void *rxp, unsigned long flags)
  198. {
  199. ulong start;
  200. int chconf, i = 0;
  201. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  202. /*Enable SPI channel*/
  203. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  204. /*set TRANSMIT-RECEIVE Mode*/
  205. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  206. chconf |= (priv->wordlen - 1) << 7;
  207. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  208. omap3_spi_write_chconf(priv, chconf);
  209. /*Shift in and out 1 byte at time*/
  210. for (i=0; i < len; i++){
  211. /* Write: wait for TX empty (TXS == 1)*/
  212. start = get_timer(0);
  213. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  214. OMAP3_MCSPI_CHSTAT_TXS)) {
  215. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  216. printf("SPI TXS timed out, status=0x%08x\n",
  217. readl(&priv->regs->channel[priv->cs].chstat));
  218. return -1;
  219. }
  220. }
  221. /* Write the data */
  222. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  223. if (priv->wordlen > 16)
  224. writel(((u32 *)txp)[i], tx);
  225. else if (priv->wordlen > 8)
  226. writel(((u16 *)txp)[i], tx);
  227. else
  228. writel(((u8 *)txp)[i], tx);
  229. /*Read: wait for RX containing data (RXS == 1)*/
  230. start = get_timer(0);
  231. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  232. OMAP3_MCSPI_CHSTAT_RXS)) {
  233. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  234. printf("SPI RXS timed out, status=0x%08x\n",
  235. readl(&priv->regs->channel[priv->cs].chstat));
  236. return -1;
  237. }
  238. }
  239. /* Read the data */
  240. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  241. if (priv->wordlen > 16)
  242. ((u32 *)rxp)[i] = readl(rx);
  243. else if (priv->wordlen > 8)
  244. ((u16 *)rxp)[i] = (u16)readl(rx);
  245. else
  246. ((u8 *)rxp)[i] = (u8)readl(rx);
  247. }
  248. /* Disable the channel */
  249. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  250. /*if transfer must be terminated disable the channel*/
  251. if (flags & SPI_XFER_END) {
  252. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  253. omap3_spi_write_chconf(priv, chconf);
  254. }
  255. return 0;
  256. }
  257. static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
  258. const void *dout, void *din, unsigned long flags)
  259. {
  260. unsigned int len;
  261. int ret = -1;
  262. if (priv->wordlen < 4 || priv->wordlen > 32) {
  263. printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
  264. return -1;
  265. }
  266. if (bitlen % priv->wordlen)
  267. return -1;
  268. len = bitlen / priv->wordlen;
  269. if (bitlen == 0) { /* only change CS */
  270. int chconf = readl(&priv->regs->channel[priv->cs].chconf);
  271. if (flags & SPI_XFER_BEGIN) {
  272. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  273. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  274. omap3_spi_write_chconf(priv, chconf);
  275. }
  276. if (flags & SPI_XFER_END) {
  277. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  278. omap3_spi_write_chconf(priv, chconf);
  279. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  280. }
  281. ret = 0;
  282. } else {
  283. if (dout != NULL && din != NULL)
  284. ret = omap3_spi_txrx(priv, len, dout, din, flags);
  285. else if (dout != NULL)
  286. ret = omap3_spi_write(priv, len, dout, flags);
  287. else if (din != NULL)
  288. ret = omap3_spi_read(priv, len, din, flags);
  289. }
  290. return ret;
  291. }
  292. static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
  293. {
  294. uint32_t confr, div = 0;
  295. confr = readl(&priv->regs->channel[priv->cs].chconf);
  296. /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
  297. if (priv->freq) {
  298. while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
  299. > priv->freq)
  300. div++;
  301. } else {
  302. div = 0xC;
  303. }
  304. /* set clock divisor */
  305. confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
  306. confr |= div << 2;
  307. omap3_spi_write_chconf(priv, confr);
  308. }
  309. static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
  310. {
  311. uint32_t confr;
  312. confr = readl(&priv->regs->channel[priv->cs].chconf);
  313. /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
  314. * REVISIT: this controller could support SPI_3WIRE mode.
  315. */
  316. if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
  317. confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
  318. confr |= OMAP3_MCSPI_CHCONF_DPE0;
  319. } else {
  320. confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
  321. confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
  322. }
  323. /* set SPI mode 0..3 */
  324. confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
  325. if (priv->mode & SPI_CPHA)
  326. confr |= OMAP3_MCSPI_CHCONF_PHA;
  327. if (priv->mode & SPI_CPOL)
  328. confr |= OMAP3_MCSPI_CHCONF_POL;
  329. /* set chipselect polarity; manage with FORCE */
  330. if (!(priv->mode & SPI_CS_HIGH))
  331. confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
  332. else
  333. confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
  334. /* Transmit & receive mode */
  335. confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
  336. omap3_spi_write_chconf(priv, confr);
  337. }
  338. static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
  339. {
  340. unsigned int confr;
  341. /* McSPI individual channel configuration */
  342. confr = readl(&priv->regs->channel[priv->cs].chconf);
  343. /* wordlength */
  344. confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
  345. confr |= (priv->wordlen - 1) << 7;
  346. omap3_spi_write_chconf(priv, confr);
  347. }
  348. static void spi_reset(struct mcspi *regs)
  349. {
  350. unsigned int tmp;
  351. writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
  352. do {
  353. tmp = readl(&regs->sysstatus);
  354. } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
  355. writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
  356. OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
  357. OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
  358. writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
  359. }
  360. static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
  361. {
  362. unsigned int conf;
  363. /*
  364. * setup when switching from (reset default) slave mode
  365. * to single-channel master mode
  366. */
  367. conf = readl(&priv->regs->modulctrl);
  368. conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
  369. conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
  370. writel(conf, &priv->regs->modulctrl);
  371. }
  372. static int omap3_spi_claim_bus(struct udevice *dev)
  373. {
  374. struct udevice *bus = dev->parent;
  375. struct omap3_spi_priv *priv = dev_get_priv(bus);
  376. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  377. priv->cs = slave_plat->cs;
  378. priv->freq = slave_plat->max_hz;
  379. _omap3_spi_claim_bus(priv);
  380. return 0;
  381. }
  382. static int omap3_spi_release_bus(struct udevice *dev)
  383. {
  384. struct udevice *bus = dev->parent;
  385. struct omap3_spi_priv *priv = dev_get_priv(bus);
  386. writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
  387. return 0;
  388. }
  389. static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
  390. {
  391. struct udevice *bus = dev->parent;
  392. struct omap3_spi_priv *priv = dev_get_priv(bus);
  393. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  394. priv->cs = slave_plat->cs;
  395. priv->wordlen = wordlen;
  396. _omap3_spi_set_wordlen(priv);
  397. return 0;
  398. }
  399. static int omap3_spi_probe(struct udevice *dev)
  400. {
  401. struct omap3_spi_priv *priv = dev_get_priv(dev);
  402. const void *blob = gd->fdt_blob;
  403. int node = dev_of_offset(dev);
  404. struct omap2_mcspi_platform_config* data =
  405. (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
  406. priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
  407. if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
  408. priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
  409. else
  410. priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
  411. priv->wordlen = SPI_DEFAULT_WORDLEN;
  412. spi_reset(priv->regs);
  413. return 0;
  414. }
  415. static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
  416. const void *dout, void *din, unsigned long flags)
  417. {
  418. struct udevice *bus = dev->parent;
  419. struct omap3_spi_priv *priv = dev_get_priv(bus);
  420. return _spi_xfer(priv, bitlen, dout, din, flags);
  421. }
  422. static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
  423. {
  424. struct omap3_spi_priv *priv = dev_get_priv(dev);
  425. priv->freq = speed;
  426. _omap3_spi_set_speed(priv);
  427. return 0;
  428. }
  429. static int omap3_spi_set_mode(struct udevice *dev, uint mode)
  430. {
  431. struct omap3_spi_priv *priv = dev_get_priv(dev);
  432. priv->mode = mode;
  433. _omap3_spi_set_mode(priv);
  434. return 0;
  435. }
  436. static const struct dm_spi_ops omap3_spi_ops = {
  437. .claim_bus = omap3_spi_claim_bus,
  438. .release_bus = omap3_spi_release_bus,
  439. .set_wordlen = omap3_spi_set_wordlen,
  440. .xfer = omap3_spi_xfer,
  441. .set_speed = omap3_spi_set_speed,
  442. .set_mode = omap3_spi_set_mode,
  443. /*
  444. * cs_info is not needed, since we require all chip selects to be
  445. * in the device tree explicitly
  446. */
  447. };
  448. static struct omap2_mcspi_platform_config omap2_pdata = {
  449. .regs_offset = 0,
  450. };
  451. static struct omap2_mcspi_platform_config omap4_pdata = {
  452. .regs_offset = OMAP4_MCSPI_REG_OFFSET,
  453. };
  454. static const struct udevice_id omap3_spi_ids[] = {
  455. { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
  456. { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
  457. { }
  458. };
  459. U_BOOT_DRIVER(omap3_spi) = {
  460. .name = "omap3_spi",
  461. .id = UCLASS_SPI,
  462. .of_match = omap3_spi_ids,
  463. .probe = omap3_spi_probe,
  464. .ops = &omap3_spi_ops,
  465. .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
  466. };