starfive_edp.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
  4. * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  5. * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  6. *
  7. * This edp panel driver is inspired from the Linux Kernel driver
  8. * drivers/gpu/drm/panel/panel-raydium-edp.c.
  9. */
  10. #include <common.h>
  11. #include <backlight.h>
  12. #include <dm.h>
  13. #include <mipi_dsi.h>
  14. #include <panel.h>
  15. #include <asm/gpio.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/delay.h>
  18. #include <power/regulator.h>
  19. #include <i2c.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/jh7110-regs.h>
  22. #include <asm/io.h>
  23. #define UART_DEBUG
  24. #define TEST_EDID // read eDP panel EDID
  25. #define EDP_2G7
  26. #define LINK_TRAIN_ENABLE
  27. #define LT8911EXB_RST_PIN GPIO41
  28. #define BOE_14INCH_MAX_LANES 4
  29. #define _1080P_eDP_Panel_
  30. #define _MIPI_Lane_ 4 // 3 /2 / 1
  31. #define _MIPI_data_PN_Swap_En 0xF0
  32. #define _MIPI_data_PN_Swap_Dis 0x00
  33. #define _MIPI_data_PN_ _MIPI_data_PN_Swap_Dis
  34. #define NO_SWAP 0x00 // 3210 default
  35. #define MIPI_DATA_3210 0 // default
  36. #define MIPI_DATA_0123 21
  37. #define MIPI_DATA_2103 20
  38. #define MIPI_DATA_SEQ NO_SWAP
  39. #define _Nvid 0 // 0: 0x0080,default
  40. static int Nvid_Val[] = { 0x0080, 0x0800 };
  41. #define usleep_range(a, b) udelay((b))
  42. #ifdef _1080P_eDP_Panel_
  43. #define eDP_lane 2
  44. #define PCR_PLL_PREDIV 0x40
  45. static int MIPI_Timing[] =
  46. { 88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 14850 }; // VESA
  47. //#define _6bit_ // eDP panel Color Depth,262K color
  48. #define _8bit_ // eDP panel Color Depth,16.7M color
  49. #endif
  50. enum {
  51. hfp = 0,
  52. hs,
  53. hbp,
  54. hact,
  55. htotal,
  56. vfp,
  57. vs,
  58. vbp,
  59. vact,
  60. vtotal,
  61. pclk_10khz
  62. };
  63. u8 Read_DPCD010A = 0x00;
  64. bool ScrambleMode = 0;
  65. bool flag_mipi_on = 0;
  66. #ifdef TEST_EDID // read eDP panel EDID
  67. u8 EDID_DATA[128] = { 0 };
  68. u16 EDID_Timing[11] = { 0 };
  69. bool EDID_Reply = 0;
  70. #endif
  71. static inline void sys_modl(void *addr, uint32_t mask, uint32_t val)
  72. {
  73. uint32_t tmp;
  74. tmp = readl(addr);
  75. tmp &= ~mask;
  76. tmp |= (val & mask);
  77. debug("tmp 0x%x\n", tmp);
  78. writel(tmp, addr);
  79. }
  80. struct edp_panel_priv {
  81. struct udevice *reg;
  82. struct udevice *backlight;
  83. struct gpio_desc *reset_gpio; //reset
  84. struct gpio_desc *pwm_gpio; //power
  85. struct gpio_desc *bl_gpio; //backlight
  86. };
  87. static const struct display_timing default_timing = {
  88. .pixelclock.typ = 148500000,
  89. .hactive.typ = 1920,
  90. .hfront_porch.typ = 88,
  91. .hback_porch.typ = 148,
  92. .hsync_len.typ = 44,
  93. .vactive.typ = 1080,
  94. .vfront_porch.typ = 34,
  95. .vback_porch.typ = 6,
  96. .vsync_len.typ = 5,
  97. };
  98. static int edp_panel_i2c_write(struct udevice *dev, uint addr, uint8_t data)
  99. {
  100. uint8_t valb;
  101. int err;
  102. valb = data;
  103. err = dm_i2c_write(dev, addr, &valb, 1);
  104. return err;
  105. }
  106. static int edp_panel_i2c_read(struct udevice *dev, uint8_t addr, uint8_t *data)
  107. {
  108. uint8_t valb;
  109. int err;
  110. err = dm_i2c_read(dev, addr, &valb, 1);
  111. if (err)
  112. return err;
  113. *data = (int)valb;
  114. return 0;
  115. }
  116. static u8 LT8911EXB_IIC_Read_byte(struct udevice *dev, u8 reg)
  117. {
  118. uint8_t valb;
  119. int err;
  120. err = dm_i2c_read(dev, reg, &valb, 1);
  121. if (err)
  122. return err;
  123. udelay(10);
  124. return (int)valb;
  125. }
  126. static void LT8911EXB_IIC_Write_byte(struct udevice *dev,u8 reg, u8 val)
  127. {
  128. dm_i2c_write(dev, reg, &val, 1);
  129. udelay(10);
  130. }
  131. u8 boe_i2c_read(struct udevice *dev,u8 reg){
  132. return LT8911EXB_IIC_Read_byte(dev,reg);
  133. }
  134. void boe_i2c_write(struct udevice *dev,u8 reg, u8 val){
  135. LT8911EXB_IIC_Write_byte(dev,reg,val);
  136. }
  137. void Reset_LT8911EXB(struct udevice *dev)
  138. {
  139. struct edp_panel_priv *priv = dev_get_priv(dev);
  140. dm_gpio_set_value(priv->pwm_gpio, 0);
  141. dm_gpio_set_value(priv->bl_gpio, 0);
  142. dm_gpio_set_value(priv->reset_gpio, 0);
  143. }
  144. void LT8911EX_ChipID(struct udevice *dev)
  145. {
  146. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  147. LT8911EXB_IIC_Write_byte(dev, 0x08, 0x7f );
  148. #ifdef UART_DEBUG
  149. debug( "\r\nLT8911EXB chip ID: 0x%x", LT8911EXB_IIC_Read_byte(dev, 0x00 ) );
  150. debug( ",0x%x", LT8911EXB_IIC_Read_byte(dev, 0x01 ) );
  151. debug( ",0x%x", LT8911EXB_IIC_Read_byte(dev, 0x02 ) );
  152. #endif
  153. }
  154. void LT8911EXB_read_edid(struct udevice *dev)
  155. {
  156. #ifdef TEST_EDID
  157. u8 reg, i, j;
  158. // bool aux_reply, aux_ack, aux_nack, aux_defer;
  159. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  160. LT8911EXB_IIC_Write_byte(dev, 0x00, 0x20 ); //Soft Link train
  161. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa6 );
  162. LT8911EXB_IIC_Write_byte(dev, 0x2a, 0x01 );
  163. /*set edid offset addr*/
  164. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x40 ); //CMD
  165. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x00 ); //addr[15:8]
  166. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x50 ); //addr[7:0]
  167. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x00 ); //data lenth
  168. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x00 ); //data lenth
  169. LT8911EXB_IIC_Write_byte(dev, 0x2c, 0x00 ); //start Aux read edid
  170. #ifdef UART_DEBUG
  171. debug( "\r\n" );
  172. debug( "\r\nRead eDP EDID......" );
  173. #endif
  174. mdelay( 20 ); //more than 10ms
  175. reg = LT8911EXB_IIC_Read_byte(dev, 0x25);
  176. debug( "\r\nRead eDP EDID.reg = %02x.....\n", reg);
  177. if( ( reg & 0x0f ) == 0x0c )
  178. {
  179. for( j = 0; j < 8; j++ )
  180. {
  181. if( j == 7 )
  182. {
  183. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x10 ); //MOT
  184. }else
  185. {
  186. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x50 );
  187. }
  188. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x00 );
  189. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x50 );
  190. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x0f );
  191. LT8911EXB_IIC_Write_byte(dev, 0x2c, 0x00 ); //start Aux read edid
  192. mdelay( 50 ); //more than 50ms
  193. if( LT8911EXB_IIC_Read_byte(dev, 0x39 ) == 0x31 )
  194. {
  195. LT8911EXB_IIC_Read_byte(dev, 0x2b );
  196. for( i = 0; i < 16; i++ )
  197. {
  198. EDID_DATA[j * 16 + i] = LT8911EXB_IIC_Read_byte(dev, 0x2b );
  199. }
  200. EDID_Reply = 1;
  201. }else
  202. {
  203. EDID_Reply = 0;
  204. #ifdef UART_DEBUG
  205. debug( "\r\nno_reply" );
  206. debug( "\r\n" );
  207. #endif
  208. debug("\r\n*************End***************");
  209. return;
  210. }
  211. }
  212. #ifdef UART_DEBUG
  213. for( i = 0; i < 128; i++ ) //print edid data
  214. {
  215. if( ( i % 16 ) == 0 )
  216. {
  217. debug( "\r\n" );
  218. }
  219. debug( "%d, ", EDID_DATA[i] );
  220. }
  221. EDID_Timing[hfp] = ( ( EDID_DATA[0x41] & 0xC0 ) * 4 + EDID_DATA[0x3e] );
  222. EDID_Timing[hs] = ( ( EDID_DATA[0x41] & 0x30 ) * 16 + EDID_DATA[0x3f] );
  223. EDID_Timing[hbp] = ( ( ( EDID_DATA[0x3a] & 0x0f ) * 0x100 + EDID_DATA[0x39] ) - ( ( EDID_DATA[0x41] & 0x30 ) * 16 + EDID_DATA[0x3f] ) - ( ( EDID_DATA[0x41] & 0xC0 ) * 4 + EDID_DATA[0x3e] ) );
  224. EDID_Timing[hact] = ( ( EDID_DATA[0x3a] & 0xf0 ) * 16 + EDID_DATA[0x38] );
  225. EDID_Timing[htotal] = ( ( EDID_DATA[0x3a] & 0xf0 ) * 16 + EDID_DATA[0x38] + ( ( EDID_DATA[0x3a] & 0x0f ) * 0x100 + EDID_DATA[0x39] ) );
  226. EDID_Timing[vfp] = ( ( EDID_DATA[0x41] & 0x0c ) * 4 + ( EDID_DATA[0x40] & 0xf0 ) / 16 );
  227. EDID_Timing[vs] = ( ( EDID_DATA[0x41] & 0x03 ) * 16 + (EDID_DATA[0x40] & 0x0f) );
  228. EDID_Timing[vbp] = ( ( ( EDID_DATA[0x3d] & 0x03 ) * 0x100 + EDID_DATA[0x3c] ) - ( ( EDID_DATA[0x41] & 0x03 ) * 16 + ( EDID_DATA[0x40] & 0x0f ) ) - ( ( EDID_DATA[0x41] & 0x0c ) * 4 + ( EDID_DATA[0x40] & 0xf0 ) / 16 ) );
  229. EDID_Timing[vact] = ( ( EDID_DATA[0x3d] & 0xf0 ) * 16 + EDID_DATA[0x3b] );
  230. EDID_Timing[vtotal] = ( ( EDID_DATA[0x3d] & 0xf0 ) * 16 + EDID_DATA[0x3b] + ( ( EDID_DATA[0x3d] & 0x03 ) * 0x100 + EDID_DATA[0x3c] ) );
  231. EDID_Timing[pclk_10khz] = ( EDID_DATA[0x37] * 0x100 + EDID_DATA[0x36] );
  232. #endif
  233. }
  234. return;
  235. #endif
  236. }
  237. void LT8911EXB_MIPI_Video_Timing(struct udevice *dev) // ( struct video_timing *video_format )
  238. {
  239. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xd0 );
  240. LT8911EXB_IIC_Write_byte(dev, 0x0d, (u8)( MIPI_Timing[vtotal] / 256 ) );
  241. LT8911EXB_IIC_Write_byte(dev, 0x0e, (u8)( MIPI_Timing[vtotal] % 256 ) ); //vtotal
  242. LT8911EXB_IIC_Write_byte(dev, 0x0f, (u8)( MIPI_Timing[vact] / 256 ) );
  243. LT8911EXB_IIC_Write_byte(dev, 0x10, (u8)( MIPI_Timing[vact] % 256 ) ); //vactive
  244. LT8911EXB_IIC_Write_byte(dev, 0x11, (u8)( MIPI_Timing[htotal] / 256 ) );
  245. LT8911EXB_IIC_Write_byte(dev, 0x12, (u8)( MIPI_Timing[htotal] % 256 ) ); //htotal
  246. LT8911EXB_IIC_Write_byte(dev, 0x13, (u8)( MIPI_Timing[hact] / 256 ) );
  247. LT8911EXB_IIC_Write_byte(dev, 0x14, (u8)( MIPI_Timing[hact] % 256 ) ); //hactive
  248. LT8911EXB_IIC_Write_byte(dev, 0x15, (u8)( MIPI_Timing[vs] % 256 ) ); //vsa
  249. LT8911EXB_IIC_Write_byte(dev, 0x16, (u8)( MIPI_Timing[hs] % 256 ) ); //hsa
  250. LT8911EXB_IIC_Write_byte(dev, 0x17, (u8)( MIPI_Timing[vfp] / 256 ) );
  251. LT8911EXB_IIC_Write_byte(dev, 0x18, (u8)( MIPI_Timing[vfp] % 256 ) ); //vfp
  252. LT8911EXB_IIC_Write_byte(dev, 0x19, (u8)( MIPI_Timing[hfp] / 256 ) );
  253. LT8911EXB_IIC_Write_byte(dev, 0x1a, (u8)( MIPI_Timing[hfp] % 256 ) ); //hfp
  254. }
  255. void LT8911EXB_eDP_Video_cfg(struct udevice *dev) // ( struct video_timing *video_format )
  256. {
  257. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa8 );
  258. LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x88 ); // MSA from register
  259. #ifdef _Msa_Active_Only_
  260. LT8911EXB_IIC_Write_byte(dev, 0x05, 0x00 );
  261. LT8911EXB_IIC_Write_byte(dev, 0x06, 0x00 ); //htotal
  262. LT8911EXB_IIC_Write_byte(dev, 0x07, 0x00 );
  263. LT8911EXB_IIC_Write_byte(dev, 0x08, 0x00 ); //h_start
  264. LT8911EXB_IIC_Write_byte(dev, 0x09, 0x00 );
  265. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0x00 ); //hsa
  266. LT8911EXB_IIC_Write_byte(dev, 0x0b, (u8)( MIPI_Timing[hact] / 256 ) );
  267. LT8911EXB_IIC_Write_byte(dev, 0x0c, (u8)( MIPI_Timing[hact] % 256 ) ); //hactive
  268. LT8911EXB_IIC_Write_byte(dev, 0x0d, 0x00 );
  269. LT8911EXB_IIC_Write_byte(dev, 0x0e, 0x00 ); //vtotal
  270. LT8911EXB_IIC_Write_byte(dev, 0x11, 0x00 );
  271. LT8911EXB_IIC_Write_byte(dev, 0x12, 0x00 );
  272. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x00 );
  273. LT8911EXB_IIC_Write_byte(dev, 0x15, (u8)( MIPI_Timing[vact] / 256 ) );
  274. LT8911EXB_IIC_Write_byte(dev, 0x16, (u8)( MIPI_Timing[vact] % 256 ) ); //vactive
  275. #else
  276. LT8911EXB_IIC_Write_byte(dev, 0x05, (u8)( MIPI_Timing[htotal] / 256 ) );
  277. LT8911EXB_IIC_Write_byte(dev, 0x06, (u8)( MIPI_Timing[htotal] % 256 ) );
  278. LT8911EXB_IIC_Write_byte(dev, 0x07, (u8)( ( MIPI_Timing[hs] + MIPI_Timing[hbp] ) / 256 ) );
  279. LT8911EXB_IIC_Write_byte(dev, 0x08, (u8)( ( MIPI_Timing[hs] + MIPI_Timing[hbp] ) % 256 ) );
  280. LT8911EXB_IIC_Write_byte(dev, 0x09, (u8)( MIPI_Timing[hs] / 256 ) );
  281. LT8911EXB_IIC_Write_byte(dev, 0x0a, (u8)( MIPI_Timing[hs] % 256 ) );
  282. LT8911EXB_IIC_Write_byte(dev, 0x0b, (u8)( MIPI_Timing[hact] / 256 ) );
  283. LT8911EXB_IIC_Write_byte(dev, 0x0c, (u8)( MIPI_Timing[hact] % 256 ) );
  284. LT8911EXB_IIC_Write_byte(dev, 0x0d, (u8)( MIPI_Timing[vtotal] / 256 ) );
  285. LT8911EXB_IIC_Write_byte(dev, 0x0e, (u8)( MIPI_Timing[vtotal] % 256 ) );
  286. LT8911EXB_IIC_Write_byte(dev, 0x11, (u8)( ( MIPI_Timing[vs] + MIPI_Timing[vbp] ) / 256 ) );
  287. LT8911EXB_IIC_Write_byte(dev, 0x12, (u8)( ( MIPI_Timing[vs] + MIPI_Timing[vbp] ) % 256 ) );
  288. LT8911EXB_IIC_Write_byte(dev, 0x14, (u8)( MIPI_Timing[vs] % 256 ) );
  289. LT8911EXB_IIC_Write_byte(dev, 0x15, (u8)( MIPI_Timing[vact] / 256 ) );
  290. LT8911EXB_IIC_Write_byte(dev, 0x16, (u8)( MIPI_Timing[vact] % 256 ) );
  291. #endif
  292. }
  293. void LT8911EXB_init(struct udevice *dev)
  294. {
  295. u8 i;
  296. u8 pcr_pll_postdiv;
  297. u8 pcr_m;
  298. u16 Temp16;
  299. /* init */
  300. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); // Change Reg bank
  301. LT8911EXB_IIC_Write_byte(dev, 0x08, 0x7f ); // i2c over aux issue
  302. LT8911EXB_IIC_Write_byte(dev, 0x49, 0xff ); // enable 0x87xx
  303. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 ); // Change Reg bank
  304. LT8911EXB_IIC_Write_byte(dev, 0x5a, 0x0e ); // GPIO test output
  305. //for power consumption//
  306. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  307. LT8911EXB_IIC_Write_byte(dev, 0x05, 0x06 );
  308. LT8911EXB_IIC_Write_byte(dev, 0x43, 0x00 );
  309. LT8911EXB_IIC_Write_byte(dev, 0x44, 0x1f );
  310. LT8911EXB_IIC_Write_byte(dev, 0x45, 0xf7 );
  311. LT8911EXB_IIC_Write_byte(dev, 0x46, 0xf6 );
  312. LT8911EXB_IIC_Write_byte(dev, 0x49, 0x7f );
  313. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 );
  314. #if ( eDP_lane == 2 )
  315. {
  316. LT8911EXB_IIC_Write_byte(dev, 0x12, 0x33 );
  317. }
  318. #elif ( eDP_lane == 1 )
  319. {
  320. LT8911EXB_IIC_Write_byte(dev, 0x12, 0x11 );
  321. }
  322. #endif
  323. /* mipi Rx analog */
  324. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 ); // Change Reg bank
  325. LT8911EXB_IIC_Write_byte(dev, 0x32, 0x51 );
  326. LT8911EXB_IIC_Write_byte(dev, 0x35, 0x22 ); //EQ current 0x22/0x42/0x62/0x82/0xA2/0xC2/0xe2
  327. LT8911EXB_IIC_Write_byte(dev, 0x3a, 0x77 ); //EQ 12.5db
  328. LT8911EXB_IIC_Write_byte(dev, 0x3b, 0x77 ); //EQ 12.5db
  329. LT8911EXB_IIC_Write_byte(dev, 0x4c, 0x0c );
  330. LT8911EXB_IIC_Write_byte(dev, 0x4d, 0x00 );
  331. /* dessc_pcr pll analog */
  332. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 ); // Change Reg bank
  333. LT8911EXB_IIC_Write_byte(dev, 0x6a, 0x40 );
  334. LT8911EXB_IIC_Write_byte(dev, 0x6b, PCR_PLL_PREDIV );
  335. Temp16 = MIPI_Timing[pclk_10khz];
  336. if( MIPI_Timing[pclk_10khz] < 8800 )
  337. {
  338. LT8911EXB_IIC_Write_byte(dev, 0x6e, 0x82 ); //0x44:pre-div = 2 ,pixel_clk=44~ 88MHz
  339. pcr_pll_postdiv = 0x08;
  340. }else
  341. if( MIPI_Timing[pclk_10khz] < 17600 )
  342. {
  343. LT8911EXB_IIC_Write_byte(dev, 0x6e, 0x81 ); //0x40:pre-div = 1, pixel_clk =88~176MHz
  344. pcr_pll_postdiv = 0x04;
  345. }else
  346. {
  347. LT8911EXB_IIC_Write_byte(dev, 0x6e, 0x80 ); //0x40:pre-div = 0, pixel_clk =176~200MHz
  348. pcr_pll_postdiv = 0x02;
  349. }
  350. pcr_m = (u8)( Temp16 * pcr_pll_postdiv / 25 / 100 );
  351. /* dessc pll digital */
  352. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 ); // Change Reg bank
  353. LT8911EXB_IIC_Write_byte(dev, 0xa9, 0x31 );
  354. LT8911EXB_IIC_Write_byte(dev, 0xaa, 0x17 );
  355. LT8911EXB_IIC_Write_byte(dev, 0xab, 0xba );
  356. LT8911EXB_IIC_Write_byte(dev, 0xac, 0xe1 );
  357. LT8911EXB_IIC_Write_byte(dev, 0xad, 0x47 );
  358. LT8911EXB_IIC_Write_byte(dev, 0xae, 0x01 );
  359. LT8911EXB_IIC_Write_byte(dev, 0xae, 0x11 );
  360. /* Digital Top */
  361. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 ); // Change Reg bank
  362. LT8911EXB_IIC_Write_byte(dev, 0xc0, 0x01 ); //select mipi Rx
  363. #ifdef _6bit_
  364. LT8911EXB_IIC_Write_byte(dev, 0xb0, 0xd0 ); //enable dither
  365. #else
  366. LT8911EXB_IIC_Write_byte(dev, 0xb0, 0x00 ); // disable dither
  367. #endif
  368. /* mipi Rx Digital */
  369. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xd0 ); // Change Reg bank
  370. LT8911EXB_IIC_Write_byte(dev, 0x00, _MIPI_data_PN_ + _MIPI_Lane_ % 4 ); // 0: 4 Lane / 1: 1 Lane / 2 : 2 Lane / 3: 3 Lane
  371. LT8911EXB_IIC_Write_byte(dev, 0x02, 0x08 ); //settle
  372. LT8911EXB_IIC_Write_byte(dev, 0x03, MIPI_DATA_SEQ ); // default is 0x00
  373. LT8911EXB_IIC_Write_byte(dev, 0x08, 0x00 );
  374. // LT8911EXB_IIC_Write_byte(dev, 0x0a, 0x12 ); //pcr mode
  375. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x80 ); //fifo position
  376. LT8911EXB_IIC_Write_byte(dev, 0x1c, 0x80 ); //fifo position
  377. // hs mode:MIPI行采样;vs mode:MIPI帧采样
  378. LT8911EXB_IIC_Write_byte(dev, 0x24, 0x70 ); // 0x30 [3:0] line limit //pcr mode( de hs vs)
  379. LT8911EXB_IIC_Write_byte(dev, 0x31, 0x0a );
  380. /*stage1 hs mode*/
  381. LT8911EXB_IIC_Write_byte(dev, 0x25, 0x90 ); // 0x80 // line limit
  382. LT8911EXB_IIC_Write_byte(dev, 0x2a, 0x3a ); // 0x04 // step in limit
  383. LT8911EXB_IIC_Write_byte(dev, 0x21, 0x4f ); // hs_step
  384. LT8911EXB_IIC_Write_byte(dev, 0x22, 0xff );
  385. /*stage2 de mode*/
  386. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0x02 ); //de adjust pre line
  387. LT8911EXB_IIC_Write_byte(dev, 0x38, 0x02 ); //de_threshold 1
  388. LT8911EXB_IIC_Write_byte(dev, 0x39, 0x04 ); //de_threshold 2
  389. LT8911EXB_IIC_Write_byte(dev, 0x3a, 0x08 ); //de_threshold 3
  390. LT8911EXB_IIC_Write_byte(dev, 0x3b, 0x10 ); //de_threshold 4
  391. LT8911EXB_IIC_Write_byte(dev, 0x3f, 0x04 ); //de_step 1
  392. LT8911EXB_IIC_Write_byte(dev, 0x40, 0x08 ); //de_step 2
  393. LT8911EXB_IIC_Write_byte(dev, 0x41, 0x10 ); //de_step 3
  394. LT8911EXB_IIC_Write_byte(dev, 0x42, 0x60 ); //de_step 4
  395. /*stage2 hs mode*/
  396. LT8911EXB_IIC_Write_byte(dev, 0x1e, 0x0A );//LT8911EXB_IIC_Write_byte(dev, 0x1e, 0x01 ); // 0x11
  397. LT8911EXB_IIC_Write_byte(dev, 0x23, 0xf0 ); // 0x80 //
  398. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x80 ); // 0xa0
  399. #ifdef _Test_Pattern_
  400. LT8911EXB_IIC_Write_byte(dev, 0x26, ( pcr_m | 0x80 ) );
  401. #else
  402. LT8911EXB_IIC_Write_byte(dev, 0x26, pcr_m );
  403. #endif
  404. LT8911EXB_MIPI_Video_Timing(dev); //defualt setting is 1080P
  405. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); // Change Reg bank
  406. LT8911EXB_IIC_Write_byte(dev, 0x03, 0x7b ); //PCR reset
  407. LT8911EXB_IIC_Write_byte(dev, 0x03, 0xff );
  408. #ifdef EDP_2G7
  409. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  410. LT8911EXB_IIC_Write_byte(dev, 0x19, 0x31 );
  411. LT8911EXB_IIC_Write_byte(dev, 0x1a, 0x36 ); // sync m
  412. LT8911EXB_IIC_Write_byte(dev, 0x1b, 0x00 ); // sync_k [7:0]
  413. LT8911EXB_IIC_Write_byte(dev, 0x1c, 0x00 ); // sync_k [13:8]
  414. // txpll Analog
  415. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 );
  416. LT8911EXB_IIC_Write_byte(dev, 0x09, 0x00 ); // div hardware mode, for ssc.
  417. // LT8911EXB_IIC_Write_byte(dev, 0x01, 0x18 );// default : 0x18
  418. LT8911EXB_IIC_Write_byte(dev, 0x02, 0x42 );
  419. LT8911EXB_IIC_Write_byte(dev, 0x03, 0x00 ); // txpll en = 0
  420. LT8911EXB_IIC_Write_byte(dev, 0x03, 0x01 ); // txpll en = 1
  421. // LT8911EXB_IIC_Write_byte(dev, 0x04, 0x3a );// default : 0x3A
  422. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  423. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x10 ); // cal en = 0
  424. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  425. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfc );
  426. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfd );
  427. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  428. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x11 ); // cal en = 1
  429. // ssc
  430. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  431. LT8911EXB_IIC_Write_byte(dev, 0x13, 0x83 );
  432. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x41 );
  433. LT8911EXB_IIC_Write_byte(dev, 0x16, 0x0a );
  434. LT8911EXB_IIC_Write_byte(dev, 0x18, 0x0a );
  435. LT8911EXB_IIC_Write_byte(dev, 0x19, 0x33 );
  436. #endif
  437. #ifdef _eDP_1G62_
  438. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  439. LT8911EXB_IIC_Write_byte(dev, 0x19, 0x31 );
  440. LT8911EXB_IIC_Write_byte(dev, 0x1a, 0x20 ); // sync m
  441. LT8911EXB_IIC_Write_byte(dev, 0x1b, 0x19 ); // sync_k [7:0]
  442. LT8911EXB_IIC_Write_byte(dev, 0x1c, 0x99 ); // sync_k [13:8]
  443. // txpll Analog
  444. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 );
  445. LT8911EXB_IIC_Write_byte(dev, 0x09, 0x00 ); // div hardware mode, for ssc.
  446. // LT8911EXB_IIC_Write_byte(dev, 0x01, 0x18 );// default : 0x18
  447. LT8911EXB_IIC_Write_byte(dev, 0x02, 0x42 );
  448. LT8911EXB_IIC_Write_byte(dev, 0x03, 0x00 ); // txpll en = 0
  449. LT8911EXB_IIC_Write_byte(dev, 0x03, 0x01 ); // txpll en = 1
  450. // LT8911EXB_IIC_Write_byte(dev, 0x04, 0x3a );// default : 0x3A
  451. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  452. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x10 ); // cal en = 0
  453. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  454. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfc );
  455. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfd );
  456. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  457. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x11 ); // cal en = 1
  458. //ssc
  459. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  460. LT8911EXB_IIC_Write_byte(dev, 0x13, 0x83 );
  461. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x41 );
  462. LT8911EXB_IIC_Write_byte(dev, 0x16, 0x0a );
  463. LT8911EXB_IIC_Write_byte(dev, 0x18, 0x0a );
  464. LT8911EXB_IIC_Write_byte(dev, 0x19, 0x33 );
  465. #endif
  466. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  467. for( i = 0; i < 5; i++ ) //Check Tx PLL
  468. {
  469. mdelay( 5 );
  470. if( LT8911EXB_IIC_Read_byte(dev, 0x37 ) & 0x02 )
  471. {
  472. debug( "\r\nLT8911 tx pll locked" );
  473. break;
  474. }else
  475. {
  476. debug( "\r\nLT8911 tx pll unlocked" );
  477. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  478. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfc );
  479. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfd );
  480. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x87 );
  481. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x10 );
  482. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x11 );
  483. }
  484. }
  485. // AUX reset
  486. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); // Change Reg bank
  487. LT8911EXB_IIC_Write_byte(dev, 0x07, 0xfe );
  488. LT8911EXB_IIC_Write_byte(dev, 0x07, 0xff );
  489. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0xfc );
  490. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0xfe );
  491. /* tx phy */
  492. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 ); // Change Reg bank
  493. LT8911EXB_IIC_Write_byte(dev, 0x11, 0x00 );
  494. LT8911EXB_IIC_Write_byte(dev, 0x13, 0x10 );
  495. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x0c );
  496. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x08 );
  497. LT8911EXB_IIC_Write_byte(dev, 0x13, 0x20 );
  498. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x82 ); // Change Reg bank
  499. LT8911EXB_IIC_Write_byte(dev, 0x0e, 0x35 );
  500. // LT8911EXB_IIC_Write_byte(dev, 0x12, 0xff );
  501. // LT8911EXB_IIC_Write_byte(dev, 0xff, 0x80 );
  502. // LT8911EXB_IIC_Write_byte(dev, 0x40, 0x22 );
  503. /*eDP Tx Digital */
  504. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa8 ); // Change Reg bank
  505. #ifdef _Test_Pattern_
  506. LT8911EXB_IIC_Write_byte(dev, 0x24, 0x50 ); // bit2 ~ bit 0 : test panttern image mode
  507. LT8911EXB_IIC_Write_byte(dev, 0x25, 0x70 ); // bit6 ~ bit 4 : test Pattern color
  508. LT8911EXB_IIC_Write_byte(dev, 0x27, 0x50 ); //0x50:Pattern; 0x10:mipi video
  509. // LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x00 ); // pure color setting
  510. // LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x84 ); // black color
  511. LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x88 ); // block
  512. #else
  513. LT8911EXB_IIC_Write_byte(dev, 0x27, 0x10 ); //0x50:Pattern; 0x10:mipi video
  514. #endif
  515. #ifdef _6bit_
  516. LT8911EXB_IIC_Write_byte(dev, 0x17, 0x00 );
  517. LT8911EXB_IIC_Write_byte(dev, 0x18, 0x00 );
  518. #else
  519. // _8bit_
  520. LT8911EXB_IIC_Write_byte(dev, 0x17, 0x10 );
  521. LT8911EXB_IIC_Write_byte(dev, 0x18, 0x20 );
  522. #endif
  523. /* nvid */
  524. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa0 ); // Change Reg bank
  525. LT8911EXB_IIC_Write_byte(dev, 0x00, (u8)( Nvid_Val[_Nvid] / 256 ) ); // 0x08
  526. LT8911EXB_IIC_Write_byte(dev, 0x01, (u8)( Nvid_Val[_Nvid] % 256 ) ); // 0x00
  527. }
  528. void LT8911EXB_video_check(struct udevice *dev)
  529. {
  530. u32 reg = 0x00;
  531. /* mipi byte clk check*/
  532. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 ); // Change Reg bank
  533. LT8911EXB_IIC_Write_byte(dev, 0x1d, 0x00 ); //FM select byte clk
  534. LT8911EXB_IIC_Write_byte(dev, 0x40, 0xf7 );
  535. LT8911EXB_IIC_Write_byte(dev, 0x41, 0x30 );
  536. //#ifdef _eDP_scramble_
  537. if( ScrambleMode )
  538. {
  539. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x82 ); //eDP scramble mode;
  540. }
  541. //#else
  542. else
  543. {
  544. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x02 ); // DP scramble mode;
  545. }
  546. //#endif
  547. // LT8911EXB_IIC_Write_byte(dev, 0x17, 0xf0 ); // 0xf0:Close scramble; 0xD0 : Open scramble
  548. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  549. LT8911EXB_IIC_Write_byte(dev, 0x09, 0x7d );
  550. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfd );
  551. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 );
  552. mdelay(20);
  553. if( LT8911EXB_IIC_Read_byte(dev, 0x50 ) == 0x03 )
  554. {
  555. reg = LT8911EXB_IIC_Read_byte(dev, 0x4d );
  556. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x4e );
  557. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x4f );
  558. debug( "\r\nvideo check: mipi byteclk = %d ", reg ); // mipi byteclk = reg * 1000
  559. debug( "\r\nvideo check: mipi bitrate = %d ", reg * 8 ); // mipi byteclk = reg * 1000
  560. debug( "\r\nvideo check: mipi pclk = %d ", reg /3 * 4 * 1000 ); // mipi byteclk = reg * 1000
  561. }else
  562. {
  563. debug( "\r\nvideo check: mipi clk unstable" );
  564. }
  565. /* mipi vtotal check*/
  566. reg = LT8911EXB_IIC_Read_byte(dev, 0x76 );
  567. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x77 );
  568. debug( "\r\nvideo check: Vtotal = %d", reg);
  569. /* mipi word count check*/
  570. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xd0 );
  571. reg = LT8911EXB_IIC_Read_byte(dev, 0x82 );
  572. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x83 );
  573. reg = reg / 3;
  574. debug( "\r\nvideo check: Hact(word counter) = %d", reg);
  575. /* mipi Vact check*/
  576. reg = LT8911EXB_IIC_Read_byte(dev, 0x85 );
  577. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x86 );
  578. debug( "\r\nvideo check: Vact = %d", reg);
  579. }
  580. void DpcdWrite(struct udevice *dev, u32 Address, u8 Data )
  581. {
  582. /***************************
  583. 注意大小端的问题!
  584. 这里默认是大端模式
  585. Pay attention to the Big-Endian and Little-Endian!
  586. The default mode is Big-Endian here.
  587. ****************************/
  588. u8 AddressH = 0x0f & ( Address >> 16 );
  589. u8 AddressM = 0xff & ( Address >> 8 );
  590. u8 AddressL = 0xff & Address;
  591. u8 reg;
  592. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa6 );
  593. LT8911EXB_IIC_Write_byte(dev, 0x2b, ( 0x80 | AddressH ) ); //CMD
  594. LT8911EXB_IIC_Write_byte(dev, 0x2b, AddressM ); //addr[15:8]
  595. LT8911EXB_IIC_Write_byte(dev, 0x2b, AddressL ); //addr[7:0]
  596. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x00 ); //data lenth
  597. LT8911EXB_IIC_Write_byte(dev, 0x2b, Data ); //data
  598. LT8911EXB_IIC_Write_byte(dev, 0x2c, 0x00 ); //start Aux
  599. mdelay( 20 ); //more than 10ms
  600. reg = LT8911EXB_IIC_Read_byte(dev, 0x25 );
  601. if( ( reg & 0x0f ) == 0x0c )
  602. {
  603. return;
  604. }
  605. }
  606. u8 DpcdRead(struct udevice *dev, u32 Address )
  607. {
  608. /***************************
  609. 注意大小端的问题!
  610. 这里默认是大端模式
  611. Pay attention to the Big-Endian and Little-Endian!
  612. The default mode is Big-Endian here.
  613. ****************************/
  614. u8 DpcdValue = 0x00;
  615. u8 AddressH = 0x0f & ( Address >> 16 );
  616. u8 AddressM = 0xff & ( Address >> 8 );
  617. u8 AddressL = 0xff & Address;
  618. u8 reg;
  619. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  620. LT8911EXB_IIC_Write_byte(dev, 0x00, 0x20 ); //Soft Link train
  621. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa6 );
  622. LT8911EXB_IIC_Write_byte(dev, 0x2a, 0x01 );
  623. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa6 );
  624. LT8911EXB_IIC_Write_byte(dev, 0x2b, ( 0x90 | AddressH ) ); //CMD
  625. LT8911EXB_IIC_Write_byte(dev, 0x2b, AddressM ); //addr[15:8]
  626. LT8911EXB_IIC_Write_byte(dev, 0x2b, AddressL ); //addr[7:0]
  627. LT8911EXB_IIC_Write_byte(dev, 0x2b, 0x00 ); //data lenth
  628. LT8911EXB_IIC_Write_byte(dev, 0x2c, 0x00 ); //start Aux read edid
  629. mdelay( 50 ); //more than 10ms
  630. reg = LT8911EXB_IIC_Read_byte(dev, 0x25 );
  631. if( ( reg & 0x0f ) == 0x0c )
  632. {
  633. if( LT8911EXB_IIC_Read_byte(dev, 0x39 ) == 0x22 )
  634. {
  635. LT8911EXB_IIC_Read_byte(dev, 0x2b );
  636. DpcdValue = LT8911EXB_IIC_Read_byte(dev, 0x2b );
  637. }
  638. /*
  639. else
  640. {
  641. // goto no_reply;
  642. // DpcdValue = 0xff;
  643. return DpcdValue;
  644. }//*/
  645. }else
  646. {
  647. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); // change bank
  648. LT8911EXB_IIC_Write_byte(dev, 0x07, 0xfe );
  649. LT8911EXB_IIC_Write_byte(dev, 0x07, 0xff );
  650. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0xfc );
  651. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0xfe );
  652. }
  653. return DpcdValue;
  654. }
  655. void LT8911EX_link_train(struct udevice *dev)
  656. {
  657. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  658. LT8911EXB_IIC_Write_byte(dev, 0x06, 0xdf ); // rset VID TX
  659. LT8911EXB_IIC_Write_byte(dev, 0x06, 0xff );
  660. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 );
  661. if( ScrambleMode )
  662. {
  663. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x82 ); // eDP scramble mode;
  664. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  665. LT8911EXB_IIC_Write_byte(dev, 0x00, 0x20 ); //Soft Link train
  666. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa6 );
  667. LT8911EXB_IIC_Write_byte(dev, 0x2a, 0x01 );
  668. DpcdWrite(dev, 0x010a, 0x01 );
  669. mdelay(10);
  670. DpcdWrite(dev, 0x0102, 0x00 );
  671. mdelay(10);
  672. DpcdWrite(dev, 0x010a, 0x01 );
  673. mdelay(10);
  674. //*/
  675. }
  676. //#else
  677. else
  678. {
  679. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x02 ); // DP scramble mode;
  680. }
  681. //#endif
  682. /* Aux setup */
  683. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  684. LT8911EXB_IIC_Write_byte(dev, 0x00, 0x60 ); //Soft Link train
  685. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa6 );
  686. LT8911EXB_IIC_Write_byte(dev, 0x2a, 0x00 );
  687. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 );
  688. LT8911EXB_IIC_Write_byte(dev, 0x07, 0xfe );
  689. LT8911EXB_IIC_Write_byte(dev, 0x07, 0xff );
  690. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0xfc );
  691. LT8911EXB_IIC_Write_byte(dev, 0x0a, 0xfe );
  692. /* link train */
  693. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 );
  694. LT8911EXB_IIC_Write_byte(dev, 0x1a, eDP_lane );
  695. #ifdef LINK_TRAIN_ENABLE
  696. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  697. LT8911EXB_IIC_Write_byte(dev, 0x00, 0x64 );
  698. LT8911EXB_IIC_Write_byte(dev, 0x01, 0x0a );
  699. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0x85 );
  700. LT8911EXB_IIC_Write_byte(dev, 0x0c, 0xc5 );
  701. #else
  702. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  703. LT8911EXB_IIC_Write_byte(dev, 0x00, 0x00 );
  704. LT8911EXB_IIC_Write_byte(dev, 0x01, 0x0a );
  705. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x80 );
  706. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x81 );
  707. mdelay( 50 );
  708. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x84 );
  709. mdelay( 50 );
  710. LT8911EXB_IIC_Write_byte(dev, 0x14, 0xc0 );
  711. #endif
  712. }
  713. static int LT8911EX_link_train_result(struct udevice *dev)
  714. {
  715. u8 i, reg;
  716. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  717. for( i = 0; i < 10; i++ )
  718. {
  719. reg = LT8911EXB_IIC_Read_byte(dev, 0x82 );
  720. // Debug_DispStrNum( "\r\n0x82 = ", reg );
  721. if( reg & 0x20 )
  722. {
  723. if( ( reg & 0x1f ) == 0x1e )
  724. {
  725. debug( "\r\nLink train success, 0x82 = 0x%x", reg );
  726. debug( "\r\npanel link rate: 0x%x", LT8911EXB_IIC_Read_byte(dev, 0x83 ) );
  727. debug( "\r\npanel link count: 0x%x", LT8911EXB_IIC_Read_byte(dev, 0x84 ) );
  728. mdelay( 10 );
  729. return 0;
  730. } else{
  731. debug( "\r\nLink train fail, 0x82 = 0x%x", reg );
  732. debug( "\r\npanel link rate: 0x%x", LT8911EXB_IIC_Read_byte(dev, 0x83 ) );
  733. debug( "\r\npanel link count: 0x%x", LT8911EXB_IIC_Read_byte(dev, 0x84 ) );
  734. mdelay( 10 );
  735. return -1;
  736. }
  737. }
  738. else{
  739. debug( "\r\nlink trian on going..." );
  740. mdelay( 1 );
  741. }
  742. }
  743. return -1;
  744. }
  745. void LT8911EXB_MainLoop(struct udevice *dev)
  746. {
  747. #ifndef _Test_Pattern_
  748. u16 reg;
  749. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 );
  750. //LT8911EXB_IIC_Write_byte(0x1d,0x00); //FM select byte clk
  751. //LT8911EXB_IIC_Write_byte(0x40,0xf7);
  752. //LT8911EXB_IIC_Write_byte(0x41,0x30);
  753. if( ScrambleMode )
  754. {
  755. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x82 ); //
  756. }else
  757. {
  758. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x02 ); //
  759. }
  760. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); //video check rst
  761. LT8911EXB_IIC_Write_byte(dev, 0x09, 0x7d );
  762. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfd );
  763. mdelay(10);
  764. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 );
  765. reg = LT8911EXB_IIC_Read_byte(dev, 0x76 );
  766. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x77 );
  767. // if( reg == MIPI_Timing[vtotal] )
  768. if( ( reg > ( MIPI_Timing[vtotal] - 5 ) ) && ( reg < ( MIPI_Timing[vtotal] + 5 ) ) )
  769. {
  770. if( !flag_mipi_on )
  771. {
  772. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); //PCR reset
  773. LT8911EXB_IIC_Write_byte(dev, 0x03, 0x7b );
  774. LT8911EXB_IIC_Write_byte(dev, 0x03, 0xff );
  775. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa8 );
  776. LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x88 );
  777. flag_mipi_on = 1;
  778. debug( "\r\nPCR reset" );
  779. }
  780. }else
  781. {
  782. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa8 );
  783. LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x8c ); //edp output idle pattern;
  784. flag_mipi_on = 0;
  785. }
  786. #ifdef UART_DEBUG
  787. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xd0 );
  788. reg = LT8911EXB_IIC_Read_byte(dev, 0x87 );
  789. // reg = reg * 256 + HDMI_ReadI2C_Byte( 0x77 );
  790. if( reg & 0x10 )
  791. {
  792. debug( "\r\nPCR Clock stable" );
  793. }else
  794. {
  795. debug( "\r\nPCR Clock unstable" );
  796. }
  797. debug( "\r\n " );
  798. #endif
  799. #endif
  800. }
  801. enum
  802. {
  803. _Level0_ = 0, // 27.8 mA 0x83/0x00
  804. _Level1_, // 26.2 mA 0x82/0xe0
  805. _Level2_, // 24.6 mA 0x82/0xc0
  806. _Level3_, // 23 mA 0x82/0xa0
  807. _Level4_, // 21.4 mA 0x82/0x80
  808. _Level5_, // 18.2 mA 0x82/0x40
  809. _Level6_, // 16.6 mA 0x82/0x20
  810. _Level7_, // 15mA 0x82/0x00 // level 1
  811. _Level8_, // 12.8mA 0x81/0x00 // level 2
  812. _Level9_, // 11.2mA 0x80/0xe0 // level 3
  813. _Level10_, // 9.6mA 0x80/0xc0 // level 4
  814. _Level11_, // 8mA 0x80/0xa0 // level 5
  815. _Level12_, // 6mA 0x80/0x80 // level 6
  816. };
  817. u8 Swing_Setting1[] = { 0x83, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x81, 0x80, 0x80, 0x80, 0x80 };
  818. u8 Swing_Setting2[] = { 0x00, 0xe0, 0xc0, 0xa0, 0x80, 0x40, 0x20, 0x00, 0x00, 0xe0, 0xc0, 0xa0, 0x80 };
  819. u8 Level = _Level7_;
  820. void LT8911EX_TxSwingPreSet(struct udevice *dev)
  821. {
  822. LT8911EXB_IIC_Write_byte(dev, 0xFF, 0x82 );
  823. LT8911EXB_IIC_Write_byte(dev, 0x22, Swing_Setting1[Level] ); //lane 0 tap0
  824. LT8911EXB_IIC_Write_byte(dev, 0x23, Swing_Setting2[Level] );
  825. LT8911EXB_IIC_Write_byte(dev, 0x24, 0x80 ); //lane 0 tap1
  826. LT8911EXB_IIC_Write_byte(dev, 0x25, 0x00 );
  827. #if ( eDP_lane == 2 )
  828. LT8911EXB_IIC_Write_byte(dev, 0x26, Swing_Setting1[Level] ); //lane 1 tap0
  829. LT8911EXB_IIC_Write_byte(dev, 0x27, Swing_Setting2[Level] );
  830. LT8911EXB_IIC_Write_byte(dev, 0x28, 0x80 ); //lane 1 tap1
  831. LT8911EXB_IIC_Write_byte(dev, 0x29, 0x00 );
  832. #endif
  833. }
  834. void PCR_Status(struct udevice *dev) // for debug
  835. {
  836. #ifdef UART_DEBUG
  837. u8 reg;
  838. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xd0 );
  839. reg = LT8911EXB_IIC_Read_byte(dev, 0x87 );
  840. debug( "\r\nReg0xD087 = ");
  841. debug( " 0x%x ", reg );
  842. debug( "\r\n " );
  843. if( reg & 0x10 )
  844. {
  845. debug( "\r\nPCR Clock stable" );
  846. }else
  847. {
  848. debug( "\r\nPCR Clock unstable" );
  849. }
  850. debug( "\r\n " );
  851. #endif
  852. }
  853. void LT8911_MainLoop(struct udevice *dev)
  854. {
  855. u16 reg, H_act, V_act;
  856. // bool flag_mipi_on = 0;
  857. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 );
  858. if( ScrambleMode )
  859. {
  860. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x82 ); //video check from mipi
  861. }else
  862. {
  863. LT8911EXB_IIC_Write_byte(dev, 0xa1, 0x02 );
  864. }
  865. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); //video check rst
  866. LT8911EXB_IIC_Write_byte(dev, 0x09, 0x7d );
  867. LT8911EXB_IIC_Write_byte(dev, 0x09, 0xfd );
  868. mdelay(10);
  869. /* mipi word count check*/
  870. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xd0 );
  871. reg = LT8911EXB_IIC_Read_byte(dev, 0x82 );
  872. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x83 );
  873. H_act = reg / 3;
  874. #ifdef UART_DEBUG
  875. debug( "\r\nHact(word counter) = %d\r\n", H_act ); // H active = word counter / 3
  876. #endif
  877. /* mipi Vact check*/
  878. reg = LT8911EXB_IIC_Read_byte(dev, 0x85 );
  879. V_act = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x86 );
  880. #ifdef UART_DEBUG
  881. debug( "\r\nVact = %d\r\n ",V_act );
  882. #endif
  883. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x85 );
  884. reg = LT8911EXB_IIC_Read_byte(dev, 0x76 );
  885. reg = reg * 256 + LT8911EXB_IIC_Read_byte(dev, 0x77 );
  886. #ifdef UART_DEBUG
  887. debug( "\r\nvideo check: Vtotal = %d\r\n ",reg );
  888. #endif
  889. // if( reg == MIPI_Timing[vtotal] )
  890. if( ( reg > ( MIPI_Timing[vtotal] - 5 ) ) && ( reg < ( MIPI_Timing[vtotal] + 5 ) ) )
  891. {
  892. if( !flag_mipi_on )
  893. {
  894. LT8911EXB_IIC_Write_byte(dev, 0xff, 0x81 ); //PCR reset
  895. LT8911EXB_IIC_Write_byte(dev, 0x03, 0x7b );
  896. LT8911EXB_IIC_Write_byte(dev, 0x03, 0xff );
  897. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa8 );
  898. LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x88 );
  899. flag_mipi_on = 1;
  900. #ifdef UART_DEBUG
  901. debug( "\r\nPCR reset" );
  902. #endif
  903. }
  904. }else
  905. {
  906. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xa8 );
  907. LT8911EXB_IIC_Write_byte(dev, 0x2d, 0x8c ); //edp output idle pattern;
  908. flag_mipi_on = 0;
  909. }
  910. #ifdef UART_DEBUG
  911. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xd0 );
  912. reg = LT8911EXB_IIC_Read_byte(dev, 0x87 );
  913. debug( "\r\nReg0xD087 = 0x%x\r\n ",reg );
  914. if( reg & 0x10 )
  915. {
  916. debug( "\r\nPCR Clock stable" );
  917. }else
  918. {
  919. debug( "\r\nPCR Clock unstable" );
  920. }
  921. debug( "\r\n " );
  922. #endif
  923. }
  924. /***********************************************************/
  925. void LT8911EXB_LinkTrainResultCheck(struct udevice *dev)
  926. {
  927. #ifdef LINK_TRAIN_ENABLE
  928. u8 i;
  929. u8 val;
  930. //int ret;
  931. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  932. for( i = 0; i < 10; i++ )
  933. {
  934. val = LT8911EXB_IIC_Read_byte(dev, 0x82 );
  935. if( val & 0x20 )
  936. {
  937. if( ( val & 0x1f ) == 0x1e )
  938. {
  939. #ifdef UART_DEBUG
  940. // debug("\r\nLT8911_LinkTrainResultCheck: edp link train successed: 0x%bx", val);
  941. debug( "\r\nedp link train successed: 0x%x", val );
  942. #endif
  943. return;
  944. }else
  945. {
  946. #ifdef UART_DEBUG
  947. //debug("\r\nLT8911_LinkTrainResultCheck: edp link train failed: 0x%bx", val);
  948. debug( "\r\nedp link train failed: 0x%x", val );
  949. #endif
  950. LT8911EXB_IIC_Write_byte(dev, 0xff, 0xac );
  951. LT8911EXB_IIC_Write_byte(dev, 0x00, 0x00 );
  952. LT8911EXB_IIC_Write_byte(dev, 0x01, 0x0a );
  953. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x80 );
  954. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x81 );
  955. mdelay(10);
  956. LT8911EXB_IIC_Write_byte(dev, 0x14, 0x84 );
  957. mdelay(10);
  958. LT8911EXB_IIC_Write_byte(dev, 0x14, 0xc0 );
  959. //debug("\r\nLT8911_LinkTrainResultCheck: Enable eDP video output while linktrian fail");
  960. }
  961. #ifdef UART_DEBUG
  962. val = LT8911EXB_IIC_Read_byte(dev, 0x83 );
  963. //debug("\r\nLT8911_LinkTrainResultCheck: panel link rate: 0x%bx",val);
  964. debug( "\r\npanel link rate: 0x%x", val );
  965. val = LT8911EXB_IIC_Read_byte(dev, 0x84 );
  966. //debug("\r\nLT8911_LinkTrainResultCheck: panel link count: 0x%bx",val);
  967. debug( "\r\npanel link count:0x%x ", val );
  968. #endif
  969. mdelay( 10 ); // return;
  970. }else
  971. {
  972. //debug("\r\nLT8911_LinkTrainResultCheck: link trian on going...");
  973. mdelay( 10 );
  974. }
  975. }
  976. #endif
  977. }
  978. static int edp_panel_enable_backlight(struct udevice *dev)
  979. {
  980. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  981. struct mipi_dsi_device *device = plat->device;
  982. int ret;
  983. debug("\r\nedp_panel_enable_backlight\r\n");
  984. ret = mipi_dsi_attach(device);
  985. if (ret < 0)
  986. return ret;
  987. Reset_LT8911EXB(dev); // 先Reset LT8911EXB ,用GPIO 先拉低LT8911EXB的复位脚 100ms左右,再拉高,保持100ms。
  988. LT8911EX_ChipID(dev); // read Chip ID
  989. LT8911EXB_eDP_Video_cfg(dev);
  990. LT8911EXB_init(dev);
  991. ScrambleMode = 0;
  992. LT8911EX_TxSwingPreSet(dev);
  993. LT8911EX_link_train(dev);
  994. LT8911EXB_LinkTrainResultCheck(dev);
  995. //======================================//
  996. ret = LT8911EX_link_train_result(dev); // for debug
  997. if (ret < 0)
  998. return ret;
  999. LT8911EXB_video_check(dev); // just for Check MIPI Input
  1000. debug("\r\nDpcdRead(0x0202) = 0x%x\r\n",DpcdRead(dev,0x0202));
  1001. PCR_Status(dev); // just for Check PCR CLK
  1002. return 0;
  1003. }
  1004. static int edp_panel_get_display_timing(struct udevice *dev,
  1005. struct display_timing *timings)
  1006. {
  1007. memcpy(timings, &default_timing, sizeof(*timings));
  1008. return 0;
  1009. }
  1010. static int edp_panel_of_to_plat(struct udevice *dev)
  1011. {
  1012. return 0;
  1013. }
  1014. static int edp_panel_probe(struct udevice *dev)
  1015. {
  1016. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  1017. struct edp_panel_priv *priv = dev_get_priv(dev);
  1018. u8 regval;
  1019. /* fill characteristics of DSI data link */
  1020. plat->lanes = 4;
  1021. plat->format = MIPI_DSI_FMT_RGB888;
  1022. plat->mode_flags = MIPI_DSI_MODE_VIDEO |
  1023. MIPI_DSI_MODE_VIDEO_BURST |
  1024. MIPI_DSI_MODE_LPM;
  1025. priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
  1026. GPIOD_IS_IN);
  1027. if (IS_ERR(priv->reset_gpio)) {
  1028. pr_err("Failed get reset gpio41\n");
  1029. return PTR_ERR(priv->reset_gpio);
  1030. }
  1031. priv->pwm_gpio = devm_gpiod_get_optional(dev, "pwm",
  1032. GPIOD_IS_OUT);
  1033. if (IS_ERR(priv->pwm_gpio)) {
  1034. pr_err("Failed get power gpio33\n");
  1035. return PTR_ERR(priv->pwm_gpio);
  1036. }
  1037. priv->bl_gpio = devm_gpiod_get_optional(dev, "bl",
  1038. GPIOD_IS_OUT);
  1039. if (IS_ERR(priv->bl_gpio)) {
  1040. pr_err("Failed get bl\n");
  1041. return PTR_ERR(priv->bl_gpio);
  1042. }
  1043. LT8911EXB_init(dev);
  1044. regval = DpcdRead(dev, 0x0101);
  1045. debug("0x0101 DpcdRead regval = 0x%x\n", regval);
  1046. if (regval == 0x00 || regval == 0xff ){
  1047. pr_err("no screen connected\n");
  1048. return -1;
  1049. }
  1050. return 0;
  1051. }
  1052. static const struct panel_ops edp_panel_ops = {
  1053. .enable_backlight = edp_panel_enable_backlight,
  1054. .get_display_timing = edp_panel_get_display_timing,
  1055. };
  1056. static const struct udevice_id edp_panel_ids[] = {
  1057. { .compatible = "lontium,lt8911exb" },
  1058. { }
  1059. };
  1060. U_BOOT_DRIVER(edp_panel) = {
  1061. .name = "edp_panel",
  1062. .id = UCLASS_PANEL,
  1063. .of_match = edp_panel_ids,
  1064. .ops = &edp_panel_ops,
  1065. .of_to_plat = edp_panel_of_to_plat,
  1066. .probe = edp_panel_probe,
  1067. .plat_auto = sizeof(struct mipi_dsi_panel_plat),
  1068. .priv_auto = sizeof(struct edp_panel_priv),
  1069. };