cpsw.c 24 KB

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  1. /*
  2. * CPSW Ethernet Switch Driver
  3. *
  4. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <common.h>
  16. #include <command.h>
  17. #include <net.h>
  18. #include <miiphy.h>
  19. #include <malloc.h>
  20. #include <net.h>
  21. #include <netdev.h>
  22. #include <cpsw.h>
  23. #include <asm/errno.h>
  24. #include <asm/io.h>
  25. #include <phy.h>
  26. #define BITMASK(bits) (BIT(bits) - 1)
  27. #define PHY_REG_MASK 0x1f
  28. #define PHY_ID_MASK 0x1f
  29. #define NUM_DESCS (PKTBUFSRX * 2)
  30. #define PKT_MIN 60
  31. #define PKT_MAX (1500 + 14 + 4 + 4)
  32. #define CLEAR_BIT 1
  33. #define GIGABITEN BIT(7)
  34. #define FULLDUPLEXEN BIT(0)
  35. #define MIIEN BIT(15)
  36. /* DMA Registers */
  37. #define CPDMA_TXCONTROL 0x004
  38. #define CPDMA_RXCONTROL 0x014
  39. #define CPDMA_SOFTRESET 0x01c
  40. #define CPDMA_RXFREE 0x0e0
  41. #define CPDMA_TXHDP_VER1 0x100
  42. #define CPDMA_TXHDP_VER2 0x200
  43. #define CPDMA_RXHDP_VER1 0x120
  44. #define CPDMA_RXHDP_VER2 0x220
  45. #define CPDMA_TXCP_VER1 0x140
  46. #define CPDMA_TXCP_VER2 0x240
  47. #define CPDMA_RXCP_VER1 0x160
  48. #define CPDMA_RXCP_VER2 0x260
  49. #define CPDMA_RAM_ADDR 0x4a102000
  50. /* Descriptor mode bits */
  51. #define CPDMA_DESC_SOP BIT(31)
  52. #define CPDMA_DESC_EOP BIT(30)
  53. #define CPDMA_DESC_OWNER BIT(29)
  54. #define CPDMA_DESC_EOQ BIT(28)
  55. /*
  56. * This timeout definition is a worst-case ultra defensive measure against
  57. * unexpected controller lock ups. Ideally, we should never ever hit this
  58. * scenario in practice.
  59. */
  60. #define MDIO_TIMEOUT 100 /* msecs */
  61. #define CPDMA_TIMEOUT 100 /* msecs */
  62. struct cpsw_mdio_regs {
  63. u32 version;
  64. u32 control;
  65. #define CONTROL_IDLE BIT(31)
  66. #define CONTROL_ENABLE BIT(30)
  67. u32 alive;
  68. u32 link;
  69. u32 linkintraw;
  70. u32 linkintmasked;
  71. u32 __reserved_0[2];
  72. u32 userintraw;
  73. u32 userintmasked;
  74. u32 userintmaskset;
  75. u32 userintmaskclr;
  76. u32 __reserved_1[20];
  77. struct {
  78. u32 access;
  79. u32 physel;
  80. #define USERACCESS_GO BIT(31)
  81. #define USERACCESS_WRITE BIT(30)
  82. #define USERACCESS_ACK BIT(29)
  83. #define USERACCESS_READ (0)
  84. #define USERACCESS_DATA (0xffff)
  85. } user[0];
  86. };
  87. struct cpsw_regs {
  88. u32 id_ver;
  89. u32 control;
  90. u32 soft_reset;
  91. u32 stat_port_en;
  92. u32 ptype;
  93. };
  94. struct cpsw_slave_regs {
  95. u32 max_blks;
  96. u32 blk_cnt;
  97. u32 flow_thresh;
  98. u32 port_vlan;
  99. u32 tx_pri_map;
  100. u32 gap_thresh;
  101. u32 sa_lo;
  102. u32 sa_hi;
  103. };
  104. struct cpsw_host_regs {
  105. u32 max_blks;
  106. u32 blk_cnt;
  107. u32 flow_thresh;
  108. u32 port_vlan;
  109. u32 tx_pri_map;
  110. u32 cpdma_tx_pri_map;
  111. u32 cpdma_rx_chan_map;
  112. };
  113. struct cpsw_sliver_regs {
  114. u32 id_ver;
  115. u32 mac_control;
  116. u32 mac_status;
  117. u32 soft_reset;
  118. u32 rx_maxlen;
  119. u32 __reserved_0;
  120. u32 rx_pause;
  121. u32 tx_pause;
  122. u32 __reserved_1;
  123. u32 rx_pri_map;
  124. };
  125. #define ALE_ENTRY_BITS 68
  126. #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
  127. /* ALE Registers */
  128. #define ALE_CONTROL 0x08
  129. #define ALE_UNKNOWNVLAN 0x18
  130. #define ALE_TABLE_CONTROL 0x20
  131. #define ALE_TABLE 0x34
  132. #define ALE_PORTCTL 0x40
  133. #define ALE_TABLE_WRITE BIT(31)
  134. #define ALE_TYPE_FREE 0
  135. #define ALE_TYPE_ADDR 1
  136. #define ALE_TYPE_VLAN 2
  137. #define ALE_TYPE_VLAN_ADDR 3
  138. #define ALE_UCAST_PERSISTANT 0
  139. #define ALE_UCAST_UNTOUCHED 1
  140. #define ALE_UCAST_OUI 2
  141. #define ALE_UCAST_TOUCHED 3
  142. #define ALE_MCAST_FWD 0
  143. #define ALE_MCAST_BLOCK_LEARN_FWD 1
  144. #define ALE_MCAST_FWD_LEARN 2
  145. #define ALE_MCAST_FWD_2 3
  146. enum cpsw_ale_port_state {
  147. ALE_PORT_STATE_DISABLE = 0x00,
  148. ALE_PORT_STATE_BLOCK = 0x01,
  149. ALE_PORT_STATE_LEARN = 0x02,
  150. ALE_PORT_STATE_FORWARD = 0x03,
  151. };
  152. /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
  153. #define ALE_SECURE 1
  154. #define ALE_BLOCKED 2
  155. struct cpsw_slave {
  156. struct cpsw_slave_regs *regs;
  157. struct cpsw_sliver_regs *sliver;
  158. int slave_num;
  159. u32 mac_control;
  160. struct cpsw_slave_data *data;
  161. };
  162. struct cpdma_desc {
  163. /* hardware fields */
  164. u32 hw_next;
  165. u32 hw_buffer;
  166. u32 hw_len;
  167. u32 hw_mode;
  168. /* software fields */
  169. u32 sw_buffer;
  170. u32 sw_len;
  171. };
  172. struct cpdma_chan {
  173. struct cpdma_desc *head, *tail;
  174. void *hdp, *cp, *rxfree;
  175. };
  176. #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
  177. #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
  178. #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
  179. #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
  180. #define chan_read(chan, fld) __raw_readl((chan)->fld)
  181. #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
  182. #define for_each_slave(slave, priv) \
  183. for (slave = (priv)->slaves; slave != (priv)->slaves + \
  184. (priv)->data.slaves; slave++)
  185. struct cpsw_priv {
  186. struct eth_device *dev;
  187. struct cpsw_platform_data data;
  188. int host_port;
  189. struct cpsw_regs *regs;
  190. void *dma_regs;
  191. struct cpsw_host_regs *host_port_regs;
  192. void *ale_regs;
  193. struct cpdma_desc *descs;
  194. struct cpdma_desc *desc_free;
  195. struct cpdma_chan rx_chan, tx_chan;
  196. struct cpsw_slave *slaves;
  197. struct phy_device *phydev;
  198. struct mii_dev *bus;
  199. u32 mdio_link;
  200. u32 phy_mask;
  201. };
  202. static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
  203. {
  204. int idx;
  205. idx = start / 32;
  206. start -= idx * 32;
  207. idx = 2 - idx; /* flip */
  208. return (ale_entry[idx] >> start) & BITMASK(bits);
  209. }
  210. static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
  211. u32 value)
  212. {
  213. int idx;
  214. value &= BITMASK(bits);
  215. idx = start / 32;
  216. start -= idx * 32;
  217. idx = 2 - idx; /* flip */
  218. ale_entry[idx] &= ~(BITMASK(bits) << start);
  219. ale_entry[idx] |= (value << start);
  220. }
  221. #define DEFINE_ALE_FIELD(name, start, bits) \
  222. static inline int cpsw_ale_get_##name(u32 *ale_entry) \
  223. { \
  224. return cpsw_ale_get_field(ale_entry, start, bits); \
  225. } \
  226. static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
  227. { \
  228. cpsw_ale_set_field(ale_entry, start, bits, value); \
  229. }
  230. DEFINE_ALE_FIELD(entry_type, 60, 2)
  231. DEFINE_ALE_FIELD(mcast_state, 62, 2)
  232. DEFINE_ALE_FIELD(port_mask, 66, 3)
  233. DEFINE_ALE_FIELD(ucast_type, 62, 2)
  234. DEFINE_ALE_FIELD(port_num, 66, 2)
  235. DEFINE_ALE_FIELD(blocked, 65, 1)
  236. DEFINE_ALE_FIELD(secure, 64, 1)
  237. DEFINE_ALE_FIELD(mcast, 40, 1)
  238. /* The MAC address field in the ALE entry cannot be macroized as above */
  239. static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
  240. {
  241. int i;
  242. for (i = 0; i < 6; i++)
  243. addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
  244. }
  245. static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
  246. {
  247. int i;
  248. for (i = 0; i < 6; i++)
  249. cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
  250. }
  251. static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
  252. {
  253. int i;
  254. __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
  255. for (i = 0; i < ALE_ENTRY_WORDS; i++)
  256. ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
  257. return idx;
  258. }
  259. static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
  260. {
  261. int i;
  262. for (i = 0; i < ALE_ENTRY_WORDS; i++)
  263. __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
  264. __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
  265. return idx;
  266. }
  267. static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
  268. {
  269. u32 ale_entry[ALE_ENTRY_WORDS];
  270. int type, idx;
  271. for (idx = 0; idx < priv->data.ale_entries; idx++) {
  272. u8 entry_addr[6];
  273. cpsw_ale_read(priv, idx, ale_entry);
  274. type = cpsw_ale_get_entry_type(ale_entry);
  275. if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
  276. continue;
  277. cpsw_ale_get_addr(ale_entry, entry_addr);
  278. if (memcmp(entry_addr, addr, 6) == 0)
  279. return idx;
  280. }
  281. return -ENOENT;
  282. }
  283. static int cpsw_ale_match_free(struct cpsw_priv *priv)
  284. {
  285. u32 ale_entry[ALE_ENTRY_WORDS];
  286. int type, idx;
  287. for (idx = 0; idx < priv->data.ale_entries; idx++) {
  288. cpsw_ale_read(priv, idx, ale_entry);
  289. type = cpsw_ale_get_entry_type(ale_entry);
  290. if (type == ALE_TYPE_FREE)
  291. return idx;
  292. }
  293. return -ENOENT;
  294. }
  295. static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
  296. {
  297. u32 ale_entry[ALE_ENTRY_WORDS];
  298. int type, idx;
  299. for (idx = 0; idx < priv->data.ale_entries; idx++) {
  300. cpsw_ale_read(priv, idx, ale_entry);
  301. type = cpsw_ale_get_entry_type(ale_entry);
  302. if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
  303. continue;
  304. if (cpsw_ale_get_mcast(ale_entry))
  305. continue;
  306. type = cpsw_ale_get_ucast_type(ale_entry);
  307. if (type != ALE_UCAST_PERSISTANT &&
  308. type != ALE_UCAST_OUI)
  309. return idx;
  310. }
  311. return -ENOENT;
  312. }
  313. static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
  314. int port, int flags)
  315. {
  316. u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
  317. int idx;
  318. cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
  319. cpsw_ale_set_addr(ale_entry, addr);
  320. cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
  321. cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
  322. cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
  323. cpsw_ale_set_port_num(ale_entry, port);
  324. idx = cpsw_ale_match_addr(priv, addr);
  325. if (idx < 0)
  326. idx = cpsw_ale_match_free(priv);
  327. if (idx < 0)
  328. idx = cpsw_ale_find_ageable(priv);
  329. if (idx < 0)
  330. return -ENOMEM;
  331. cpsw_ale_write(priv, idx, ale_entry);
  332. return 0;
  333. }
  334. static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
  335. {
  336. u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
  337. int idx, mask;
  338. idx = cpsw_ale_match_addr(priv, addr);
  339. if (idx >= 0)
  340. cpsw_ale_read(priv, idx, ale_entry);
  341. cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
  342. cpsw_ale_set_addr(ale_entry, addr);
  343. cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
  344. mask = cpsw_ale_get_port_mask(ale_entry);
  345. port_mask |= mask;
  346. cpsw_ale_set_port_mask(ale_entry, port_mask);
  347. if (idx < 0)
  348. idx = cpsw_ale_match_free(priv);
  349. if (idx < 0)
  350. idx = cpsw_ale_find_ageable(priv);
  351. if (idx < 0)
  352. return -ENOMEM;
  353. cpsw_ale_write(priv, idx, ale_entry);
  354. return 0;
  355. }
  356. static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
  357. {
  358. u32 tmp, mask = BIT(bit);
  359. tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
  360. tmp &= ~mask;
  361. tmp |= val ? mask : 0;
  362. __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
  363. }
  364. #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
  365. #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
  366. #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
  367. static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
  368. int val)
  369. {
  370. int offset = ALE_PORTCTL + 4 * port;
  371. u32 tmp, mask = 0x3;
  372. tmp = __raw_readl(priv->ale_regs + offset);
  373. tmp &= ~mask;
  374. tmp |= val & mask;
  375. __raw_writel(tmp, priv->ale_regs + offset);
  376. }
  377. static struct cpsw_mdio_regs *mdio_regs;
  378. /* wait until hardware is ready for another user access */
  379. static inline u32 wait_for_user_access(void)
  380. {
  381. u32 reg = 0;
  382. int timeout = MDIO_TIMEOUT;
  383. while (timeout-- &&
  384. ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
  385. udelay(10);
  386. if (timeout == -1) {
  387. printf("wait_for_user_access Timeout\n");
  388. return -ETIMEDOUT;
  389. }
  390. return reg;
  391. }
  392. /* wait until hardware state machine is idle */
  393. static inline void wait_for_idle(void)
  394. {
  395. int timeout = MDIO_TIMEOUT;
  396. while (timeout-- &&
  397. ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
  398. udelay(10);
  399. if (timeout == -1)
  400. printf("wait_for_idle Timeout\n");
  401. }
  402. static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
  403. int dev_addr, int phy_reg)
  404. {
  405. unsigned short data;
  406. u32 reg;
  407. if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
  408. return -EINVAL;
  409. wait_for_user_access();
  410. reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
  411. (phy_id << 16));
  412. __raw_writel(reg, &mdio_regs->user[0].access);
  413. reg = wait_for_user_access();
  414. data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
  415. return data;
  416. }
  417. static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
  418. int phy_reg, u16 data)
  419. {
  420. u32 reg;
  421. if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
  422. return -EINVAL;
  423. wait_for_user_access();
  424. reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
  425. (phy_id << 16) | (data & USERACCESS_DATA));
  426. __raw_writel(reg, &mdio_regs->user[0].access);
  427. wait_for_user_access();
  428. return 0;
  429. }
  430. static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
  431. {
  432. struct mii_dev *bus = mdio_alloc();
  433. mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
  434. /* set enable and clock divider */
  435. __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
  436. /*
  437. * wait for scan logic to settle:
  438. * the scan time consists of (a) a large fixed component, and (b) a
  439. * small component that varies with the mii bus frequency. These
  440. * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
  441. * silicon. Since the effect of (b) was found to be largely
  442. * negligible, we keep things simple here.
  443. */
  444. udelay(1000);
  445. bus->read = cpsw_mdio_read;
  446. bus->write = cpsw_mdio_write;
  447. sprintf(bus->name, name);
  448. mdio_register(bus);
  449. }
  450. /* Set a self-clearing bit in a register, and wait for it to clear */
  451. static inline void setbit_and_wait_for_clear32(void *addr)
  452. {
  453. __raw_writel(CLEAR_BIT, addr);
  454. while (__raw_readl(addr) & CLEAR_BIT)
  455. ;
  456. }
  457. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  458. ((mac)[2] << 16) | ((mac)[3] << 24))
  459. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  460. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  461. struct cpsw_priv *priv)
  462. {
  463. __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
  464. __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
  465. }
  466. static void cpsw_slave_update_link(struct cpsw_slave *slave,
  467. struct cpsw_priv *priv, int *link)
  468. {
  469. struct phy_device *phy = priv->phydev;
  470. u32 mac_control = 0;
  471. phy_startup(phy);
  472. *link = phy->link;
  473. if (*link) { /* link up */
  474. mac_control = priv->data.mac_control;
  475. if (phy->speed == 1000)
  476. mac_control |= GIGABITEN;
  477. if (phy->duplex == DUPLEX_FULL)
  478. mac_control |= FULLDUPLEXEN;
  479. if (phy->speed == 100)
  480. mac_control |= MIIEN;
  481. }
  482. if (mac_control == slave->mac_control)
  483. return;
  484. if (mac_control) {
  485. printf("link up on port %d, speed %d, %s duplex\n",
  486. slave->slave_num, phy->speed,
  487. (phy->duplex == DUPLEX_FULL) ? "full" : "half");
  488. } else {
  489. printf("link down on port %d\n", slave->slave_num);
  490. }
  491. __raw_writel(mac_control, &slave->sliver->mac_control);
  492. slave->mac_control = mac_control;
  493. }
  494. static int cpsw_update_link(struct cpsw_priv *priv)
  495. {
  496. int link = 0;
  497. struct cpsw_slave *slave;
  498. for_each_slave(slave, priv)
  499. cpsw_slave_update_link(slave, priv, &link);
  500. priv->mdio_link = readl(&mdio_regs->link);
  501. return link;
  502. }
  503. static int cpsw_check_link(struct cpsw_priv *priv)
  504. {
  505. u32 link = 0;
  506. link = __raw_readl(&mdio_regs->link) & priv->phy_mask;
  507. if ((link) && (link == priv->mdio_link))
  508. return 1;
  509. return cpsw_update_link(priv);
  510. }
  511. static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  512. {
  513. if (priv->host_port == 0)
  514. return slave_num + 1;
  515. else
  516. return slave_num;
  517. }
  518. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
  519. {
  520. u32 slave_port;
  521. setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
  522. /* setup priority mapping */
  523. __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
  524. __raw_writel(0x33221100, &slave->regs->tx_pri_map);
  525. /* setup max packet size, and mac address */
  526. __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
  527. cpsw_set_slave_mac(slave, priv);
  528. slave->mac_control = 0; /* no link yet */
  529. /* enable forwarding */
  530. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  531. cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
  532. cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
  533. priv->phy_mask |= 1 << slave->data->phy_id;
  534. }
  535. static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
  536. {
  537. struct cpdma_desc *desc = priv->desc_free;
  538. if (desc)
  539. priv->desc_free = desc_read_ptr(desc, hw_next);
  540. return desc;
  541. }
  542. static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
  543. {
  544. if (desc) {
  545. desc_write(desc, hw_next, priv->desc_free);
  546. priv->desc_free = desc;
  547. }
  548. }
  549. static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
  550. void *buffer, int len)
  551. {
  552. struct cpdma_desc *desc, *prev;
  553. u32 mode;
  554. desc = cpdma_desc_alloc(priv);
  555. if (!desc)
  556. return -ENOMEM;
  557. if (len < PKT_MIN)
  558. len = PKT_MIN;
  559. mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
  560. desc_write(desc, hw_next, 0);
  561. desc_write(desc, hw_buffer, buffer);
  562. desc_write(desc, hw_len, len);
  563. desc_write(desc, hw_mode, mode | len);
  564. desc_write(desc, sw_buffer, buffer);
  565. desc_write(desc, sw_len, len);
  566. if (!chan->head) {
  567. /* simple case - first packet enqueued */
  568. chan->head = desc;
  569. chan->tail = desc;
  570. chan_write(chan, hdp, desc);
  571. goto done;
  572. }
  573. /* not the first packet - enqueue at the tail */
  574. prev = chan->tail;
  575. desc_write(prev, hw_next, desc);
  576. chan->tail = desc;
  577. /* next check if EOQ has been triggered already */
  578. if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
  579. chan_write(chan, hdp, desc);
  580. done:
  581. if (chan->rxfree)
  582. chan_write(chan, rxfree, 1);
  583. return 0;
  584. }
  585. static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
  586. void **buffer, int *len)
  587. {
  588. struct cpdma_desc *desc = chan->head;
  589. u32 status;
  590. if (!desc)
  591. return -ENOENT;
  592. status = desc_read(desc, hw_mode);
  593. if (len)
  594. *len = status & 0x7ff;
  595. if (buffer)
  596. *buffer = desc_read_ptr(desc, sw_buffer);
  597. if (status & CPDMA_DESC_OWNER) {
  598. if (chan_read(chan, hdp) == 0) {
  599. if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
  600. chan_write(chan, hdp, desc);
  601. }
  602. return -EBUSY;
  603. }
  604. chan->head = desc_read_ptr(desc, hw_next);
  605. chan_write(chan, cp, desc);
  606. cpdma_desc_free(priv, desc);
  607. return 0;
  608. }
  609. static int cpsw_init(struct eth_device *dev, bd_t *bis)
  610. {
  611. struct cpsw_priv *priv = dev->priv;
  612. struct cpsw_slave *slave;
  613. int i, ret;
  614. /* soft reset the controller and initialize priv */
  615. setbit_and_wait_for_clear32(&priv->regs->soft_reset);
  616. /* initialize and reset the address lookup engine */
  617. cpsw_ale_enable(priv, 1);
  618. cpsw_ale_clear(priv, 1);
  619. cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
  620. /* setup host port priority mapping */
  621. __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
  622. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  623. /* disable priority elevation and enable statistics on all ports */
  624. __raw_writel(0, &priv->regs->ptype);
  625. /* enable statistics collection only on the host port */
  626. __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
  627. cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
  628. cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
  629. ALE_SECURE);
  630. cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
  631. for_each_slave(slave, priv)
  632. cpsw_slave_init(slave, priv);
  633. cpsw_update_link(priv);
  634. /* init descriptor pool */
  635. for (i = 0; i < NUM_DESCS; i++) {
  636. desc_write(&priv->descs[i], hw_next,
  637. (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
  638. }
  639. priv->desc_free = &priv->descs[0];
  640. /* initialize channels */
  641. if (priv->data.version == CPSW_CTRL_VERSION_2) {
  642. memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
  643. priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
  644. priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
  645. priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
  646. memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
  647. priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
  648. priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
  649. } else {
  650. memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
  651. priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
  652. priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
  653. priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
  654. memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
  655. priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
  656. priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
  657. }
  658. /* clear dma state */
  659. setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
  660. if (priv->data.version == CPSW_CTRL_VERSION_2) {
  661. for (i = 0; i < priv->data.channels; i++) {
  662. __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
  663. * i);
  664. __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
  665. * i);
  666. __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
  667. * i);
  668. __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
  669. * i);
  670. __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
  671. * i);
  672. }
  673. } else {
  674. for (i = 0; i < priv->data.channels; i++) {
  675. __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
  676. * i);
  677. __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
  678. * i);
  679. __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
  680. * i);
  681. __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
  682. * i);
  683. __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
  684. * i);
  685. }
  686. }
  687. __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
  688. __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
  689. /* submit rx descs */
  690. for (i = 0; i < PKTBUFSRX; i++) {
  691. ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
  692. PKTSIZE);
  693. if (ret < 0) {
  694. printf("error %d submitting rx desc\n", ret);
  695. break;
  696. }
  697. }
  698. return 0;
  699. }
  700. static void cpsw_halt(struct eth_device *dev)
  701. {
  702. struct cpsw_priv *priv = dev->priv;
  703. writel(0, priv->dma_regs + CPDMA_TXCONTROL);
  704. writel(0, priv->dma_regs + CPDMA_RXCONTROL);
  705. /* soft reset the controller and initialize priv */
  706. setbit_and_wait_for_clear32(&priv->regs->soft_reset);
  707. /* clear dma state */
  708. setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
  709. priv->data.control(0);
  710. }
  711. static int cpsw_send(struct eth_device *dev, void *packet, int length)
  712. {
  713. struct cpsw_priv *priv = dev->priv;
  714. void *buffer;
  715. int len;
  716. int timeout = CPDMA_TIMEOUT;
  717. if (!cpsw_check_link(priv))
  718. return -EIO;
  719. flush_dcache_range((unsigned long)packet,
  720. (unsigned long)packet + length);
  721. /* first reap completed packets */
  722. while (timeout-- &&
  723. (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
  724. ;
  725. if (timeout == -1) {
  726. printf("cpdma_process timeout\n");
  727. return -ETIMEDOUT;
  728. }
  729. return cpdma_submit(priv, &priv->tx_chan, packet, length);
  730. }
  731. static int cpsw_recv(struct eth_device *dev)
  732. {
  733. struct cpsw_priv *priv = dev->priv;
  734. void *buffer;
  735. int len;
  736. cpsw_update_link(priv);
  737. while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
  738. invalidate_dcache_range((unsigned long)buffer,
  739. (unsigned long)buffer + PKTSIZE_ALIGN);
  740. NetReceive(buffer, len);
  741. cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
  742. }
  743. return 0;
  744. }
  745. static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
  746. struct cpsw_priv *priv)
  747. {
  748. void *regs = priv->regs;
  749. struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
  750. slave->slave_num = slave_num;
  751. slave->data = data;
  752. slave->regs = regs + data->slave_reg_ofs;
  753. slave->sliver = regs + data->sliver_reg_ofs;
  754. }
  755. static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
  756. {
  757. struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
  758. struct phy_device *phydev;
  759. u32 supported = (SUPPORTED_10baseT_Half |
  760. SUPPORTED_10baseT_Full |
  761. SUPPORTED_100baseT_Half |
  762. SUPPORTED_100baseT_Full |
  763. SUPPORTED_1000baseT_Full);
  764. phydev = phy_connect(priv->bus,
  765. CONFIG_PHY_ADDR,
  766. dev,
  767. slave->data->phy_if);
  768. phydev->supported &= supported;
  769. phydev->advertising = phydev->supported;
  770. priv->phydev = phydev;
  771. phy_config(phydev);
  772. return 1;
  773. }
  774. int cpsw_register(struct cpsw_platform_data *data)
  775. {
  776. struct cpsw_priv *priv;
  777. struct cpsw_slave *slave;
  778. void *regs = (void *)data->cpsw_base;
  779. struct eth_device *dev;
  780. dev = calloc(sizeof(*dev), 1);
  781. if (!dev)
  782. return -ENOMEM;
  783. priv = calloc(sizeof(*priv), 1);
  784. if (!priv) {
  785. free(dev);
  786. return -ENOMEM;
  787. }
  788. priv->data = *data;
  789. priv->dev = dev;
  790. priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
  791. if (!priv->slaves) {
  792. free(dev);
  793. free(priv);
  794. return -ENOMEM;
  795. }
  796. priv->descs = (void *)CPDMA_RAM_ADDR;
  797. priv->host_port = data->host_port_num;
  798. priv->regs = regs;
  799. priv->host_port_regs = regs + data->host_port_reg_ofs;
  800. priv->dma_regs = regs + data->cpdma_reg_ofs;
  801. priv->ale_regs = regs + data->ale_reg_ofs;
  802. int idx = 0;
  803. for_each_slave(slave, priv) {
  804. cpsw_slave_setup(slave, idx, priv);
  805. idx = idx + 1;
  806. }
  807. strcpy(dev->name, "cpsw");
  808. dev->iobase = 0;
  809. dev->init = cpsw_init;
  810. dev->halt = cpsw_halt;
  811. dev->send = cpsw_send;
  812. dev->recv = cpsw_recv;
  813. dev->priv = priv;
  814. eth_register(dev);
  815. cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
  816. priv->bus = miiphy_get_dev_by_name(dev->name);
  817. for_each_slave(slave, priv)
  818. cpsw_phy_init(dev, slave);
  819. return 1;
  820. }