ps7_init_gpl.c 536 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) Xilinx, Inc.
  4. */
  5. #include <asm/arch/ps7_init_gpl.h>
  6. unsigned long ps7_pll_init_data_3_0[] = {
  7. /* START: top */
  8. /* .. START: SLCR SETTINGS */
  9. /* .. UNLOCK_KEY = 0XDF0D */
  10. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  11. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  12. /* .. */
  13. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  14. /* .. FINISH: SLCR SETTINGS */
  15. /* .. START: PLL SLCR REGISTERS */
  16. /* .. .. START: ARM PLL INIT */
  17. /* .. .. PLL_RES = 0xc */
  18. /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
  19. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  20. /* .. .. PLL_CP = 0x2 */
  21. /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
  22. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  23. /* .. .. LOCK_CNT = 0x177 */
  24. /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
  25. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
  26. /* .. .. */
  27. EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
  28. /* .. .. .. START: UPDATE FB_DIV */
  29. /* .. .. .. PLL_FDIV = 0x1a */
  30. /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
  31. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
  32. /* .. .. .. */
  33. EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
  34. /* .. .. .. FINISH: UPDATE FB_DIV */
  35. /* .. .. .. START: BY PASS PLL */
  36. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  37. /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
  38. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  39. /* .. .. .. */
  40. EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
  41. /* .. .. .. FINISH: BY PASS PLL */
  42. /* .. .. .. START: ASSERT RESET */
  43. /* .. .. .. PLL_RESET = 1 */
  44. /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
  45. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  46. /* .. .. .. */
  47. EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
  48. /* .. .. .. FINISH: ASSERT RESET */
  49. /* .. .. .. START: DEASSERT RESET */
  50. /* .. .. .. PLL_RESET = 0 */
  51. /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
  52. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  53. /* .. .. .. */
  54. EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
  55. /* .. .. .. FINISH: DEASSERT RESET */
  56. /* .. .. .. START: CHECK PLL STATUS */
  57. /* .. .. .. ARM_PLL_LOCK = 1 */
  58. /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
  59. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  60. /* .. .. .. */
  61. EMIT_MASKPOLL(0XF800010C, 0x00000001U),
  62. /* .. .. .. FINISH: CHECK PLL STATUS */
  63. /* .. .. .. START: REMOVE PLL BY PASS */
  64. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  65. /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
  66. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  67. /* .. .. .. */
  68. EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
  69. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  70. /* .. .. .. SRCSEL = 0x0 */
  71. /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
  72. /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  73. /* .. .. .. DIVISOR = 0x2 */
  74. /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
  75. /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
  76. /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
  77. /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
  78. /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
  79. /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
  80. /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
  81. /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
  82. /* .. .. .. CPU_2XCLKACT = 0x1 */
  83. /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
  84. /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
  85. /* .. .. .. CPU_1XCLKACT = 0x1 */
  86. /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
  87. /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
  88. /* .. .. .. CPU_PERI_CLKACT = 0x1 */
  89. /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
  90. /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  91. /* .. .. .. */
  92. EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
  93. /* .. .. FINISH: ARM PLL INIT */
  94. /* .. .. START: DDR PLL INIT */
  95. /* .. .. PLL_RES = 0xc */
  96. /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
  97. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  98. /* .. .. PLL_CP = 0x2 */
  99. /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
  100. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  101. /* .. .. LOCK_CNT = 0x1db */
  102. /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
  103. /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
  104. /* .. .. */
  105. EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
  106. /* .. .. .. START: UPDATE FB_DIV */
  107. /* .. .. .. PLL_FDIV = 0x15 */
  108. /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
  109. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
  110. /* .. .. .. */
  111. EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
  112. /* .. .. .. FINISH: UPDATE FB_DIV */
  113. /* .. .. .. START: BY PASS PLL */
  114. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  115. /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
  116. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  117. /* .. .. .. */
  118. EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
  119. /* .. .. .. FINISH: BY PASS PLL */
  120. /* .. .. .. START: ASSERT RESET */
  121. /* .. .. .. PLL_RESET = 1 */
  122. /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
  123. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  124. /* .. .. .. */
  125. EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
  126. /* .. .. .. FINISH: ASSERT RESET */
  127. /* .. .. .. START: DEASSERT RESET */
  128. /* .. .. .. PLL_RESET = 0 */
  129. /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
  130. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  131. /* .. .. .. */
  132. EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
  133. /* .. .. .. FINISH: DEASSERT RESET */
  134. /* .. .. .. START: CHECK PLL STATUS */
  135. /* .. .. .. DDR_PLL_LOCK = 1 */
  136. /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
  137. /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  138. /* .. .. .. */
  139. EMIT_MASKPOLL(0XF800010C, 0x00000002U),
  140. /* .. .. .. FINISH: CHECK PLL STATUS */
  141. /* .. .. .. START: REMOVE PLL BY PASS */
  142. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  143. /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
  144. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  145. /* .. .. .. */
  146. EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
  147. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  148. /* .. .. .. DDR_3XCLKACT = 0x1 */
  149. /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
  150. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  151. /* .. .. .. DDR_2XCLKACT = 0x1 */
  152. /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
  153. /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  154. /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
  155. /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
  156. /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
  157. /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
  158. /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
  159. /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
  160. /* .. .. .. */
  161. EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
  162. /* .. .. FINISH: DDR PLL INIT */
  163. /* .. .. START: IO PLL INIT */
  164. /* .. .. PLL_RES = 0xc */
  165. /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
  166. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  167. /* .. .. PLL_CP = 0x2 */
  168. /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
  169. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  170. /* .. .. LOCK_CNT = 0x1f4 */
  171. /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
  172. /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
  173. /* .. .. */
  174. EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
  175. /* .. .. .. START: UPDATE FB_DIV */
  176. /* .. .. .. PLL_FDIV = 0x14 */
  177. /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
  178. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
  179. /* .. .. .. */
  180. EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
  181. /* .. .. .. FINISH: UPDATE FB_DIV */
  182. /* .. .. .. START: BY PASS PLL */
  183. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  184. /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
  185. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  186. /* .. .. .. */
  187. EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
  188. /* .. .. .. FINISH: BY PASS PLL */
  189. /* .. .. .. START: ASSERT RESET */
  190. /* .. .. .. PLL_RESET = 1 */
  191. /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
  192. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  193. /* .. .. .. */
  194. EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
  195. /* .. .. .. FINISH: ASSERT RESET */
  196. /* .. .. .. START: DEASSERT RESET */
  197. /* .. .. .. PLL_RESET = 0 */
  198. /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
  199. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  200. /* .. .. .. */
  201. EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
  202. /* .. .. .. FINISH: DEASSERT RESET */
  203. /* .. .. .. START: CHECK PLL STATUS */
  204. /* .. .. .. IO_PLL_LOCK = 1 */
  205. /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
  206. /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  207. /* .. .. .. */
  208. EMIT_MASKPOLL(0XF800010C, 0x00000004U),
  209. /* .. .. .. FINISH: CHECK PLL STATUS */
  210. /* .. .. .. START: REMOVE PLL BY PASS */
  211. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  212. /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
  213. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  214. /* .. .. .. */
  215. EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
  216. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  217. /* .. .. FINISH: IO PLL INIT */
  218. /* .. FINISH: PLL SLCR REGISTERS */
  219. /* .. START: LOCK IT BACK */
  220. /* .. LOCK_KEY = 0X767B */
  221. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  222. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  223. /* .. */
  224. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  225. /* .. FINISH: LOCK IT BACK */
  226. /* FINISH: top */
  227. /* */
  228. EMIT_EXIT(),
  229. /* */
  230. };
  231. unsigned long ps7_clock_init_data_3_0[] = {
  232. /* START: top */
  233. /* .. START: SLCR SETTINGS */
  234. /* .. UNLOCK_KEY = 0XDF0D */
  235. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  236. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  237. /* .. */
  238. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  239. /* .. FINISH: SLCR SETTINGS */
  240. /* .. START: CLOCK CONTROL SLCR REGISTERS */
  241. /* .. CLKACT = 0x1 */
  242. /* .. ==> 0XF8000128[0:0] = 0x00000001U */
  243. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  244. /* .. DIVISOR0 = 0x34 */
  245. /* .. ==> 0XF8000128[13:8] = 0x00000034U */
  246. /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
  247. /* .. DIVISOR1 = 0x2 */
  248. /* .. ==> 0XF8000128[25:20] = 0x00000002U */
  249. /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
  250. /* .. */
  251. EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
  252. /* .. CLKACT = 0x1 */
  253. /* .. ==> 0XF8000138[0:0] = 0x00000001U */
  254. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  255. /* .. SRCSEL = 0x0 */
  256. /* .. ==> 0XF8000138[4:4] = 0x00000000U */
  257. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  258. /* .. */
  259. EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
  260. /* .. CLKACT = 0x1 */
  261. /* .. ==> 0XF8000140[0:0] = 0x00000001U */
  262. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  263. /* .. SRCSEL = 0x0 */
  264. /* .. ==> 0XF8000140[6:4] = 0x00000000U */
  265. /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  266. /* .. DIVISOR = 0x8 */
  267. /* .. ==> 0XF8000140[13:8] = 0x00000008U */
  268. /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
  269. /* .. DIVISOR1 = 0x1 */
  270. /* .. ==> 0XF8000140[25:20] = 0x00000001U */
  271. /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  272. /* .. */
  273. EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
  274. /* .. CLKACT = 0x1 */
  275. /* .. ==> 0XF800014C[0:0] = 0x00000001U */
  276. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  277. /* .. SRCSEL = 0x0 */
  278. /* .. ==> 0XF800014C[5:4] = 0x00000000U */
  279. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  280. /* .. DIVISOR = 0x5 */
  281. /* .. ==> 0XF800014C[13:8] = 0x00000005U */
  282. /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  283. /* .. */
  284. EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
  285. /* .. CLKACT0 = 0x1 */
  286. /* .. ==> 0XF8000150[0:0] = 0x00000001U */
  287. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  288. /* .. CLKACT1 = 0x0 */
  289. /* .. ==> 0XF8000150[1:1] = 0x00000000U */
  290. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  291. /* .. SRCSEL = 0x0 */
  292. /* .. ==> 0XF8000150[5:4] = 0x00000000U */
  293. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  294. /* .. DIVISOR = 0x14 */
  295. /* .. ==> 0XF8000150[13:8] = 0x00000014U */
  296. /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
  297. /* .. */
  298. EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
  299. /* .. CLKACT0 = 0x0 */
  300. /* .. ==> 0XF8000154[0:0] = 0x00000000U */
  301. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  302. /* .. CLKACT1 = 0x1 */
  303. /* .. ==> 0XF8000154[1:1] = 0x00000001U */
  304. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  305. /* .. SRCSEL = 0x0 */
  306. /* .. ==> 0XF8000154[5:4] = 0x00000000U */
  307. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  308. /* .. DIVISOR = 0xa */
  309. /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
  310. /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
  311. /* .. */
  312. EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
  313. /* .. .. START: TRACE CLOCK */
  314. /* .. .. FINISH: TRACE CLOCK */
  315. /* .. .. CLKACT = 0x1 */
  316. /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
  317. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  318. /* .. .. SRCSEL = 0x0 */
  319. /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
  320. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  321. /* .. .. DIVISOR = 0x5 */
  322. /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
  323. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  324. /* .. .. */
  325. EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
  326. /* .. .. SRCSEL = 0x0 */
  327. /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
  328. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  329. /* .. .. DIVISOR0 = 0xa */
  330. /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
  331. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
  332. /* .. .. DIVISOR1 = 0x1 */
  333. /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
  334. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  335. /* .. .. */
  336. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
  337. /* .. .. SRCSEL = 0x0 */
  338. /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
  339. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  340. /* .. .. DIVISOR0 = 0x7 */
  341. /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
  342. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
  343. /* .. .. DIVISOR1 = 0x1 */
  344. /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
  345. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  346. /* .. .. */
  347. EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
  348. /* .. .. SRCSEL = 0x0 */
  349. /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
  350. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  351. /* .. .. DIVISOR0 = 0x5 */
  352. /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
  353. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  354. /* .. .. DIVISOR1 = 0x1 */
  355. /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
  356. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  357. /* .. .. */
  358. EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
  359. /* .. .. SRCSEL = 0x0 */
  360. /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
  361. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  362. /* .. .. DIVISOR0 = 0x14 */
  363. /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
  364. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
  365. /* .. .. DIVISOR1 = 0x1 */
  366. /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
  367. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  368. /* .. .. */
  369. EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
  370. /* .. .. CLK_621_TRUE = 0x1 */
  371. /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
  372. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  373. /* .. .. */
  374. EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
  375. /* .. .. DMA_CPU_2XCLKACT = 0x1 */
  376. /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
  377. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  378. /* .. .. USB0_CPU_1XCLKACT = 0x1 */
  379. /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
  380. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  381. /* .. .. USB1_CPU_1XCLKACT = 0x1 */
  382. /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
  383. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
  384. /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
  385. /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
  386. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
  387. /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
  388. /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
  389. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  390. /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
  391. /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
  392. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
  393. /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
  394. /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
  395. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  396. /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
  397. /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
  398. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  399. /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
  400. /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
  401. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  402. /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
  403. /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
  404. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  405. /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
  406. /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
  407. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  408. /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
  409. /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
  410. /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
  411. /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
  412. /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
  413. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  414. /* .. .. UART0_CPU_1XCLKACT = 0x0 */
  415. /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
  416. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  417. /* .. .. UART1_CPU_1XCLKACT = 0x1 */
  418. /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
  419. /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
  420. /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
  421. /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
  422. /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
  423. /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
  424. /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
  425. /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
  426. /* .. .. SMC_CPU_1XCLKACT = 0x1 */
  427. /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
  428. /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
  429. /* .. .. */
  430. EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
  431. /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
  432. /* .. START: THIS SHOULD BE BLANK */
  433. /* .. FINISH: THIS SHOULD BE BLANK */
  434. /* .. START: LOCK IT BACK */
  435. /* .. LOCK_KEY = 0X767B */
  436. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  437. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  438. /* .. */
  439. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  440. /* .. FINISH: LOCK IT BACK */
  441. /* FINISH: top */
  442. /* */
  443. EMIT_EXIT(),
  444. /* */
  445. };
  446. unsigned long ps7_ddr_init_data_3_0[] = {
  447. /* START: top */
  448. /* .. START: DDR INITIALIZATION */
  449. /* .. .. START: LOCK DDR */
  450. /* .. .. reg_ddrc_soft_rstb = 0 */
  451. /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
  452. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  453. /* .. .. reg_ddrc_powerdown_en = 0x0 */
  454. /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
  455. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  456. /* .. .. reg_ddrc_data_bus_width = 0x0 */
  457. /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
  458. /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
  459. /* .. .. reg_ddrc_burst8_refresh = 0x0 */
  460. /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
  461. /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  462. /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
  463. /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
  464. /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
  465. /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
  466. /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
  467. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  468. /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
  469. /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
  470. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  471. /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
  472. /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
  473. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  474. /* .. .. */
  475. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
  476. /* .. .. FINISH: LOCK DDR */
  477. /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
  478. /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
  479. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
  480. /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
  481. /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
  482. /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
  483. /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
  484. /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
  485. /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
  486. /* .. .. */
  487. EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
  488. /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
  489. /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
  490. /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
  491. /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
  492. /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
  493. /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
  494. /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
  495. /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
  496. /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
  497. /* .. .. */
  498. EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
  499. /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
  500. /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
  501. /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
  502. /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
  503. /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
  504. /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
  505. /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
  506. /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
  507. /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
  508. /* .. .. */
  509. EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
  510. /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
  511. /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
  512. /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
  513. /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
  514. /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
  515. /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
  516. /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
  517. /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
  518. /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
  519. /* .. .. */
  520. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
  521. /* .. .. reg_ddrc_t_rc = 0x1a */
  522. /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
  523. /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
  524. /* .. .. reg_ddrc_t_rfc_min = 0x54 */
  525. /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
  526. /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
  527. /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
  528. /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
  529. /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
  530. /* .. .. */
  531. EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
  532. /* .. .. reg_ddrc_wr2pre = 0x12 */
  533. /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
  534. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
  535. /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
  536. /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
  537. /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
  538. /* .. .. reg_ddrc_t_faw = 0x15 */
  539. /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
  540. /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
  541. /* .. .. reg_ddrc_t_ras_max = 0x23 */
  542. /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
  543. /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
  544. /* .. .. reg_ddrc_t_ras_min = 0x13 */
  545. /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
  546. /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
  547. /* .. .. reg_ddrc_t_cke = 0x4 */
  548. /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
  549. /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
  550. /* .. .. */
  551. EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
  552. /* .. .. reg_ddrc_write_latency = 0x5 */
  553. /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
  554. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
  555. /* .. .. reg_ddrc_rd2wr = 0x7 */
  556. /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
  557. /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
  558. /* .. .. reg_ddrc_wr2rd = 0xe */
  559. /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
  560. /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
  561. /* .. .. reg_ddrc_t_xp = 0x4 */
  562. /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
  563. /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
  564. /* .. .. reg_ddrc_pad_pd = 0x0 */
  565. /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
  566. /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
  567. /* .. .. reg_ddrc_rd2pre = 0x4 */
  568. /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
  569. /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
  570. /* .. .. reg_ddrc_t_rcd = 0x7 */
  571. /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
  572. /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
  573. /* .. .. */
  574. EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
  575. /* .. .. reg_ddrc_t_ccd = 0x4 */
  576. /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
  577. /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
  578. /* .. .. reg_ddrc_t_rrd = 0x6 */
  579. /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
  580. /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
  581. /* .. .. reg_ddrc_refresh_margin = 0x2 */
  582. /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
  583. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  584. /* .. .. reg_ddrc_t_rp = 0x7 */
  585. /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
  586. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
  587. /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
  588. /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
  589. /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
  590. /* .. .. reg_ddrc_mobile = 0x0 */
  591. /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
  592. /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  593. /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
  594. /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
  595. /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  596. /* .. .. reg_ddrc_read_latency = 0x7 */
  597. /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
  598. /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
  599. /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
  600. /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
  601. /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
  602. /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
  603. /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
  604. /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
  605. /* .. .. */
  606. EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
  607. /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
  608. /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
  609. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  610. /* .. .. reg_ddrc_prefer_write = 0x0 */
  611. /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
  612. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  613. /* .. .. reg_ddrc_mr_wr = 0x0 */
  614. /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
  615. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
  616. /* .. .. reg_ddrc_mr_addr = 0x0 */
  617. /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
  618. /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
  619. /* .. .. reg_ddrc_mr_data = 0x0 */
  620. /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
  621. /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
  622. /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
  623. /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
  624. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  625. /* .. .. reg_ddrc_mr_type = 0x0 */
  626. /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
  627. /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
  628. /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
  629. /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
  630. /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
  631. /* .. .. */
  632. EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
  633. /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
  634. /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
  635. /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
  636. /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
  637. /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
  638. /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
  639. /* .. .. reg_ddrc_t_mrd = 0x4 */
  640. /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
  641. /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
  642. /* .. .. */
  643. EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
  644. /* .. .. reg_ddrc_emr2 = 0x8 */
  645. /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
  646. /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
  647. /* .. .. reg_ddrc_emr3 = 0x0 */
  648. /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
  649. /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
  650. /* .. .. */
  651. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
  652. /* .. .. reg_ddrc_mr = 0x930 */
  653. /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
  654. /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
  655. /* .. .. reg_ddrc_emr = 0x4 */
  656. /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
  657. /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
  658. /* .. .. */
  659. EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
  660. /* .. .. reg_ddrc_burst_rdwr = 0x4 */
  661. /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
  662. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
  663. /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
  664. /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
  665. /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
  666. /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
  667. /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
  668. /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
  669. /* .. .. reg_ddrc_burstchop = 0x0 */
  670. /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
  671. /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
  672. /* .. .. */
  673. EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
  674. /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
  675. /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
  676. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  677. /* .. .. reg_ddrc_dis_dq = 0x0 */
  678. /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
  679. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  680. /* .. .. */
  681. EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
  682. /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
  683. /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
  684. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
  685. /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
  686. /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
  687. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
  688. /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
  689. /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
  690. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
  691. /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
  692. /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
  693. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
  694. /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
  695. /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
  696. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
  697. /* .. .. */
  698. EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
  699. /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
  700. /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
  701. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  702. /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
  703. /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
  704. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  705. /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
  706. /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
  707. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
  708. /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
  709. /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
  710. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
  711. /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
  712. /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
  713. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
  714. /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
  715. /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
  716. /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
  717. /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
  718. /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
  719. /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
  720. /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
  721. /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
  722. /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
  723. /* .. .. */
  724. EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
  725. /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
  726. /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
  727. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
  728. /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
  729. /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
  730. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
  731. /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
  732. /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
  733. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
  734. /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
  735. /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
  736. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
  737. /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
  738. /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
  739. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
  740. /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
  741. /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
  742. /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
  743. /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
  744. /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
  745. /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
  746. /* .. .. */
  747. EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
  748. /* .. .. reg_phy_rd_local_odt = 0x0 */
  749. /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
  750. /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
  751. /* .. .. reg_phy_wr_local_odt = 0x3 */
  752. /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
  753. /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
  754. /* .. .. reg_phy_idle_local_odt = 0x3 */
  755. /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
  756. /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
  757. /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
  758. /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
  759. /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
  760. /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
  761. /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
  762. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
  763. /* .. .. */
  764. EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
  765. /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
  766. /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
  767. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  768. /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
  769. /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
  770. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  771. /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
  772. /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
  773. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
  774. /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
  775. /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
  776. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  777. /* .. .. reg_phy_use_fixed_re = 0x1 */
  778. /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
  779. /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
  780. /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
  781. /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
  782. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  783. /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
  784. /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
  785. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  786. /* .. .. reg_phy_clk_stall_level = 0x0 */
  787. /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
  788. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  789. /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
  790. /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
  791. /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
  792. /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
  793. /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
  794. /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
  795. /* .. .. */
  796. EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
  797. /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
  798. /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
  799. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  800. /* .. .. */
  801. EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
  802. /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
  803. /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
  804. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
  805. /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
  806. /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
  807. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  808. /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
  809. /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
  810. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
  811. /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
  812. /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
  813. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
  814. /* .. .. */
  815. EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
  816. /* .. .. reg_ddrc_pageclose = 0x0 */
  817. /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
  818. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  819. /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
  820. /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
  821. /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
  822. /* .. .. reg_ddrc_auto_pre_en = 0x0 */
  823. /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
  824. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  825. /* .. .. reg_ddrc_refresh_update_level = 0x0 */
  826. /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
  827. /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  828. /* .. .. reg_ddrc_dis_wc = 0x0 */
  829. /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
  830. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  831. /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
  832. /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
  833. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  834. /* .. .. reg_ddrc_selfref_en = 0x0 */
  835. /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
  836. /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  837. /* .. .. */
  838. EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
  839. /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
  840. /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
  841. /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
  842. /* .. .. reg_arb_go2critical_en = 0x1 */
  843. /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
  844. /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
  845. /* .. .. */
  846. EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
  847. /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
  848. /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
  849. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
  850. /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
  851. /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
  852. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
  853. /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
  854. /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
  855. /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
  856. /* .. .. */
  857. EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
  858. /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
  859. /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
  860. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
  861. /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
  862. /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
  863. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
  864. /* .. .. */
  865. EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
  866. /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
  867. /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
  868. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
  869. /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
  870. /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
  871. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
  872. /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
  873. /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
  874. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
  875. /* .. .. reg_ddrc_t_cksre = 0x6 */
  876. /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
  877. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
  878. /* .. .. reg_ddrc_t_cksrx = 0x6 */
  879. /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
  880. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
  881. /* .. .. reg_ddrc_t_ckesr = 0x4 */
  882. /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
  883. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
  884. /* .. .. */
  885. EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
  886. /* .. .. reg_ddrc_t_ckpde = 0x2 */
  887. /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
  888. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
  889. /* .. .. reg_ddrc_t_ckpdx = 0x2 */
  890. /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
  891. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
  892. /* .. .. reg_ddrc_t_ckdpde = 0x2 */
  893. /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
  894. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  895. /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
  896. /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
  897. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
  898. /* .. .. reg_ddrc_t_ckcsx = 0x3 */
  899. /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
  900. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
  901. /* .. .. */
  902. EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
  903. /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
  904. /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
  905. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  906. /* .. .. reg_ddrc_ddr3 = 0x1 */
  907. /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
  908. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  909. /* .. .. reg_ddrc_t_mod = 0x200 */
  910. /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
  911. /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
  912. /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
  913. /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
  914. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
  915. /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
  916. /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
  917. /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
  918. /* .. .. */
  919. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
  920. /* .. .. t_zq_short_interval_x1024 = 0xc845 */
  921. /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
  922. /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
  923. /* .. .. dram_rstn_x1024 = 0x67 */
  924. /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
  925. /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
  926. /* .. .. */
  927. EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
  928. /* .. .. deeppowerdown_en = 0x0 */
  929. /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
  930. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  931. /* .. .. deeppowerdown_to_x1024 = 0xff */
  932. /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
  933. /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
  934. /* .. .. */
  935. EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
  936. /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
  937. /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
  938. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
  939. /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
  940. /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
  941. /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
  942. /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
  943. /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
  944. /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  945. /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
  946. /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
  947. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  948. /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
  949. /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
  950. /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
  951. /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
  952. /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
  953. /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
  954. /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
  955. /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
  956. /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  957. /* .. .. */
  958. EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
  959. /* .. .. reg_ddrc_skip_ocd = 0x1 */
  960. /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
  961. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
  962. /* .. .. */
  963. EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
  964. /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
  965. /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
  966. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
  967. /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
  968. /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
  969. /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
  970. /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
  971. /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
  972. /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
  973. /* .. .. */
  974. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
  975. /* .. .. START: RESET ECC ERROR */
  976. /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
  977. /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
  978. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  979. /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
  980. /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
  981. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  982. /* .. .. */
  983. EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
  984. /* .. .. FINISH: RESET ECC ERROR */
  985. /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
  986. /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
  987. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  988. /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
  989. /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
  990. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  991. /* .. .. */
  992. EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
  993. /* .. .. CORR_ECC_LOG_VALID = 0x0 */
  994. /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
  995. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  996. /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
  997. /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
  998. /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
  999. /* .. .. */
  1000. EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
  1001. /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
  1002. /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
  1003. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1004. /* .. .. */
  1005. EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
  1006. /* .. .. STAT_NUM_CORR_ERR = 0x0 */
  1007. /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
  1008. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
  1009. /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
  1010. /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
  1011. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
  1012. /* .. .. */
  1013. EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
  1014. /* .. .. reg_ddrc_ecc_mode = 0x0 */
  1015. /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
  1016. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
  1017. /* .. .. reg_ddrc_dis_scrub = 0x1 */
  1018. /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
  1019. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
  1020. /* .. .. */
  1021. EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
  1022. /* .. .. reg_phy_dif_on = 0x0 */
  1023. /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
  1024. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  1025. /* .. .. reg_phy_dif_off = 0x0 */
  1026. /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
  1027. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  1028. /* .. .. */
  1029. EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
  1030. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  1031. /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
  1032. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1033. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  1034. /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
  1035. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  1036. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  1037. /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
  1038. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  1039. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  1040. /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
  1041. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1042. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  1043. /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
  1044. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  1045. /* .. .. reg_phy_bist_err_clr = 0x0 */
  1046. /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
  1047. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  1048. /* .. .. reg_phy_dq_offset = 0x40 */
  1049. /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
  1050. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  1051. /* .. .. */
  1052. EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
  1053. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  1054. /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
  1055. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1056. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  1057. /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
  1058. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  1059. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  1060. /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
  1061. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  1062. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  1063. /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
  1064. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1065. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  1066. /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
  1067. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  1068. /* .. .. reg_phy_bist_err_clr = 0x0 */
  1069. /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
  1070. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  1071. /* .. .. reg_phy_dq_offset = 0x40 */
  1072. /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
  1073. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  1074. /* .. .. */
  1075. EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
  1076. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  1077. /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
  1078. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1079. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  1080. /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
  1081. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  1082. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  1083. /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
  1084. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  1085. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  1086. /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
  1087. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1088. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  1089. /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
  1090. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  1091. /* .. .. reg_phy_bist_err_clr = 0x0 */
  1092. /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
  1093. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  1094. /* .. .. reg_phy_dq_offset = 0x40 */
  1095. /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
  1096. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  1097. /* .. .. */
  1098. EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
  1099. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  1100. /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
  1101. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1102. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  1103. /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
  1104. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  1105. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  1106. /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
  1107. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  1108. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  1109. /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
  1110. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1111. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  1112. /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
  1113. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  1114. /* .. .. reg_phy_bist_err_clr = 0x0 */
  1115. /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
  1116. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  1117. /* .. .. reg_phy_dq_offset = 0x40 */
  1118. /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
  1119. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  1120. /* .. .. */
  1121. EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
  1122. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  1123. /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
  1124. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  1125. /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
  1126. /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
  1127. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
  1128. /* .. .. */
  1129. EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
  1130. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  1131. /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
  1132. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  1133. /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
  1134. /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
  1135. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
  1136. /* .. .. */
  1137. EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
  1138. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  1139. /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
  1140. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  1141. /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
  1142. /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
  1143. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
  1144. /* .. .. */
  1145. EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
  1146. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  1147. /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
  1148. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  1149. /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
  1150. /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
  1151. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
  1152. /* .. .. */
  1153. EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
  1154. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  1155. /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
  1156. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  1157. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  1158. /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
  1159. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1160. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  1161. /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
  1162. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1163. /* .. .. */
  1164. EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
  1165. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  1166. /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
  1167. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  1168. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  1169. /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
  1170. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1171. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  1172. /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
  1173. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1174. /* .. .. */
  1175. EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
  1176. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  1177. /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
  1178. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  1179. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  1180. /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
  1181. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1182. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  1183. /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
  1184. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1185. /* .. .. */
  1186. EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
  1187. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  1188. /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
  1189. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  1190. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  1191. /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
  1192. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1193. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  1194. /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
  1195. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1196. /* .. .. */
  1197. EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
  1198. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
  1199. /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
  1200. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
  1201. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  1202. /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
  1203. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1204. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  1205. /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
  1206. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1207. /* .. .. */
  1208. EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
  1209. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
  1210. /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
  1211. /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
  1212. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  1213. /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
  1214. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1215. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  1216. /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
  1217. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1218. /* .. .. */
  1219. EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
  1220. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
  1221. /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
  1222. /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
  1223. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  1224. /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
  1225. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1226. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  1227. /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
  1228. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1229. /* .. .. */
  1230. EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
  1231. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
  1232. /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
  1233. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
  1234. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  1235. /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
  1236. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1237. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  1238. /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
  1239. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1240. /* .. .. */
  1241. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
  1242. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
  1243. /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
  1244. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
  1245. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  1246. /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
  1247. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1248. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  1249. /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
  1250. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  1251. /* .. .. */
  1252. EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
  1253. /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
  1254. /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
  1255. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
  1256. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  1257. /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
  1258. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1259. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  1260. /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
  1261. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  1262. /* .. .. */
  1263. EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
  1264. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
  1265. /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
  1266. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
  1267. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  1268. /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
  1269. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1270. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  1271. /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
  1272. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  1273. /* .. .. */
  1274. EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
  1275. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
  1276. /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
  1277. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
  1278. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  1279. /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
  1280. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1281. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  1282. /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
  1283. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  1284. /* .. .. */
  1285. EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
  1286. /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
  1287. /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
  1288. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
  1289. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  1290. /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
  1291. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1292. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  1293. /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
  1294. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1295. /* .. .. */
  1296. EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
  1297. /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
  1298. /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
  1299. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
  1300. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  1301. /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
  1302. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1303. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  1304. /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
  1305. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1306. /* .. .. */
  1307. EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
  1308. /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
  1309. /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
  1310. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
  1311. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  1312. /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
  1313. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1314. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  1315. /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
  1316. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1317. /* .. .. */
  1318. EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
  1319. /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
  1320. /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
  1321. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
  1322. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  1323. /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
  1324. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  1325. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  1326. /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
  1327. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  1328. /* .. .. */
  1329. EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
  1330. /* .. .. reg_phy_bl2 = 0x0 */
  1331. /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
  1332. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  1333. /* .. .. reg_phy_at_spd_atpg = 0x0 */
  1334. /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
  1335. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  1336. /* .. .. reg_phy_bist_enable = 0x0 */
  1337. /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
  1338. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1339. /* .. .. reg_phy_bist_force_err = 0x0 */
  1340. /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
  1341. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  1342. /* .. .. reg_phy_bist_mode = 0x0 */
  1343. /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
  1344. /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  1345. /* .. .. reg_phy_invert_clkout = 0x1 */
  1346. /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
  1347. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  1348. /* .. .. reg_phy_sel_logic = 0x0 */
  1349. /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
  1350. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  1351. /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
  1352. /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
  1353. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
  1354. /* .. .. reg_phy_ctrl_slave_force = 0x0 */
  1355. /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
  1356. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  1357. /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
  1358. /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
  1359. /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
  1360. /* .. .. reg_phy_lpddr = 0x0 */
  1361. /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
  1362. /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
  1363. /* .. .. reg_phy_cmd_latency = 0x0 */
  1364. /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
  1365. /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
  1366. /* .. .. */
  1367. EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
  1368. /* .. .. reg_phy_wr_rl_delay = 0x2 */
  1369. /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
  1370. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
  1371. /* .. .. reg_phy_rd_rl_delay = 0x4 */
  1372. /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
  1373. /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
  1374. /* .. .. reg_phy_dll_lock_diff = 0xf */
  1375. /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
  1376. /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
  1377. /* .. .. reg_phy_use_wr_level = 0x1 */
  1378. /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
  1379. /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
  1380. /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
  1381. /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
  1382. /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
  1383. /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
  1384. /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
  1385. /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
  1386. /* .. .. reg_phy_dis_calib_rst = 0x0 */
  1387. /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
  1388. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1389. /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
  1390. /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
  1391. /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
  1392. /* .. .. */
  1393. EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
  1394. /* .. .. reg_arb_page_addr_mask = 0x0 */
  1395. /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
  1396. /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
  1397. /* .. .. */
  1398. EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
  1399. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  1400. /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
  1401. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1402. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  1403. /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
  1404. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1405. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  1406. /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
  1407. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1408. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  1409. /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
  1410. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1411. /* .. .. */
  1412. EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
  1413. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  1414. /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
  1415. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1416. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  1417. /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
  1418. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1419. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  1420. /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
  1421. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1422. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  1423. /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
  1424. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1425. /* .. .. */
  1426. EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
  1427. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  1428. /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
  1429. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1430. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  1431. /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
  1432. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1433. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  1434. /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
  1435. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1436. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  1437. /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
  1438. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1439. /* .. .. */
  1440. EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
  1441. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  1442. /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
  1443. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1444. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  1445. /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
  1446. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1447. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  1448. /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
  1449. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1450. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  1451. /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
  1452. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1453. /* .. .. */
  1454. EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
  1455. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  1456. /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
  1457. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1458. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  1459. /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
  1460. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1461. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  1462. /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
  1463. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1464. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  1465. /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
  1466. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1467. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  1468. /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
  1469. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  1470. /* .. .. */
  1471. EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
  1472. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  1473. /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
  1474. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1475. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  1476. /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
  1477. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1478. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  1479. /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
  1480. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1481. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  1482. /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
  1483. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1484. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  1485. /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
  1486. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  1487. /* .. .. */
  1488. EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
  1489. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  1490. /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
  1491. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1492. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  1493. /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
  1494. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1495. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  1496. /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
  1497. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1498. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  1499. /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
  1500. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1501. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  1502. /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
  1503. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  1504. /* .. .. */
  1505. EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
  1506. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  1507. /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
  1508. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  1509. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  1510. /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
  1511. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1512. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  1513. /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
  1514. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  1515. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  1516. /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
  1517. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  1518. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  1519. /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
  1520. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  1521. /* .. .. */
  1522. EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
  1523. /* .. .. reg_ddrc_lpddr2 = 0x0 */
  1524. /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
  1525. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1526. /* .. .. reg_ddrc_derate_enable = 0x0 */
  1527. /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
  1528. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  1529. /* .. .. reg_ddrc_mr4_margin = 0x0 */
  1530. /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
  1531. /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
  1532. /* .. .. */
  1533. EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
  1534. /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
  1535. /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
  1536. /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
  1537. /* .. .. */
  1538. EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
  1539. /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
  1540. /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
  1541. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
  1542. /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
  1543. /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
  1544. /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
  1545. /* .. .. reg_ddrc_t_mrw = 0x5 */
  1546. /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
  1547. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
  1548. /* .. .. */
  1549. EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
  1550. /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
  1551. /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
  1552. /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
  1553. /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
  1554. /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
  1555. /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
  1556. /* .. .. */
  1557. EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
  1558. /* .. .. START: POLL ON DCI STATUS */
  1559. /* .. .. DONE = 1 */
  1560. /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
  1561. /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  1562. /* .. .. */
  1563. EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
  1564. /* .. .. FINISH: POLL ON DCI STATUS */
  1565. /* .. .. START: UNLOCK DDR */
  1566. /* .. .. reg_ddrc_soft_rstb = 0x1 */
  1567. /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
  1568. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1569. /* .. .. reg_ddrc_powerdown_en = 0x0 */
  1570. /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
  1571. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  1572. /* .. .. reg_ddrc_data_bus_width = 0x0 */
  1573. /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
  1574. /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
  1575. /* .. .. reg_ddrc_burst8_refresh = 0x0 */
  1576. /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
  1577. /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  1578. /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
  1579. /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
  1580. /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
  1581. /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
  1582. /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
  1583. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  1584. /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
  1585. /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
  1586. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  1587. /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
  1588. /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
  1589. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  1590. /* .. .. */
  1591. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
  1592. /* .. .. FINISH: UNLOCK DDR */
  1593. /* .. .. START: CHECK DDR STATUS */
  1594. /* .. .. ddrc_reg_operating_mode = 1 */
  1595. /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
  1596. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
  1597. /* .. .. */
  1598. EMIT_MASKPOLL(0XF8006054, 0x00000007U),
  1599. /* .. .. FINISH: CHECK DDR STATUS */
  1600. /* .. FINISH: DDR INITIALIZATION */
  1601. /* FINISH: top */
  1602. /* */
  1603. EMIT_EXIT(),
  1604. /* */
  1605. };
  1606. unsigned long ps7_mio_init_data_3_0[] = {
  1607. /* START: top */
  1608. /* .. START: SLCR SETTINGS */
  1609. /* .. UNLOCK_KEY = 0XDF0D */
  1610. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  1611. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  1612. /* .. */
  1613. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  1614. /* .. FINISH: SLCR SETTINGS */
  1615. /* .. START: OCM REMAPPING */
  1616. /* .. VREF_EN = 0x1 */
  1617. /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
  1618. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1619. /* .. VREF_SEL = 0x0 */
  1620. /* .. ==> 0XF8000B00[6:4] = 0x00000000U */
  1621. /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  1622. /* .. */
  1623. EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
  1624. /* .. FINISH: OCM REMAPPING */
  1625. /* .. START: DDRIOB SETTINGS */
  1626. /* .. reserved_INP_POWER = 0x0 */
  1627. /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
  1628. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1629. /* .. INP_TYPE = 0x0 */
  1630. /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
  1631. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  1632. /* .. DCI_UPDATE_B = 0x0 */
  1633. /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
  1634. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1635. /* .. TERM_EN = 0x0 */
  1636. /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
  1637. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  1638. /* .. DCI_TYPE = 0x0 */
  1639. /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
  1640. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  1641. /* .. IBUF_DISABLE_MODE = 0x0 */
  1642. /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
  1643. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  1644. /* .. TERM_DISABLE_MODE = 0x0 */
  1645. /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
  1646. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  1647. /* .. OUTPUT_EN = 0x3 */
  1648. /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
  1649. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  1650. /* .. PULLUP_EN = 0x0 */
  1651. /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
  1652. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1653. /* .. */
  1654. EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
  1655. /* .. reserved_INP_POWER = 0x0 */
  1656. /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
  1657. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1658. /* .. INP_TYPE = 0x0 */
  1659. /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
  1660. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  1661. /* .. DCI_UPDATE_B = 0x0 */
  1662. /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
  1663. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1664. /* .. TERM_EN = 0x0 */
  1665. /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
  1666. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  1667. /* .. DCI_TYPE = 0x0 */
  1668. /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
  1669. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  1670. /* .. IBUF_DISABLE_MODE = 0x0 */
  1671. /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
  1672. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  1673. /* .. TERM_DISABLE_MODE = 0x0 */
  1674. /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
  1675. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  1676. /* .. OUTPUT_EN = 0x3 */
  1677. /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
  1678. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  1679. /* .. PULLUP_EN = 0x0 */
  1680. /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
  1681. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1682. /* .. */
  1683. EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
  1684. /* .. reserved_INP_POWER = 0x0 */
  1685. /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
  1686. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1687. /* .. INP_TYPE = 0x1 */
  1688. /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
  1689. /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
  1690. /* .. DCI_UPDATE_B = 0x0 */
  1691. /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
  1692. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1693. /* .. TERM_EN = 0x1 */
  1694. /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
  1695. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  1696. /* .. DCI_TYPE = 0x3 */
  1697. /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
  1698. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  1699. /* .. IBUF_DISABLE_MODE = 0 */
  1700. /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
  1701. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  1702. /* .. TERM_DISABLE_MODE = 0 */
  1703. /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
  1704. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  1705. /* .. OUTPUT_EN = 0x3 */
  1706. /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
  1707. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  1708. /* .. PULLUP_EN = 0x0 */
  1709. /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
  1710. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1711. /* .. */
  1712. EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
  1713. /* .. reserved_INP_POWER = 0x0 */
  1714. /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
  1715. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1716. /* .. INP_TYPE = 0x1 */
  1717. /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
  1718. /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
  1719. /* .. DCI_UPDATE_B = 0x0 */
  1720. /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
  1721. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1722. /* .. TERM_EN = 0x1 */
  1723. /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
  1724. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  1725. /* .. DCI_TYPE = 0x3 */
  1726. /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
  1727. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  1728. /* .. IBUF_DISABLE_MODE = 0 */
  1729. /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
  1730. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  1731. /* .. TERM_DISABLE_MODE = 0 */
  1732. /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
  1733. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  1734. /* .. OUTPUT_EN = 0x3 */
  1735. /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
  1736. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  1737. /* .. PULLUP_EN = 0x0 */
  1738. /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
  1739. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1740. /* .. */
  1741. EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
  1742. /* .. reserved_INP_POWER = 0x0 */
  1743. /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
  1744. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1745. /* .. INP_TYPE = 0x2 */
  1746. /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
  1747. /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
  1748. /* .. DCI_UPDATE_B = 0x0 */
  1749. /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
  1750. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1751. /* .. TERM_EN = 0x1 */
  1752. /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
  1753. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  1754. /* .. DCI_TYPE = 0x3 */
  1755. /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
  1756. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  1757. /* .. IBUF_DISABLE_MODE = 0 */
  1758. /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
  1759. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  1760. /* .. TERM_DISABLE_MODE = 0 */
  1761. /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
  1762. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  1763. /* .. OUTPUT_EN = 0x3 */
  1764. /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
  1765. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  1766. /* .. PULLUP_EN = 0x0 */
  1767. /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
  1768. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1769. /* .. */
  1770. EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
  1771. /* .. reserved_INP_POWER = 0x0 */
  1772. /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
  1773. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1774. /* .. INP_TYPE = 0x2 */
  1775. /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
  1776. /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
  1777. /* .. DCI_UPDATE_B = 0x0 */
  1778. /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
  1779. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1780. /* .. TERM_EN = 0x1 */
  1781. /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
  1782. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  1783. /* .. DCI_TYPE = 0x3 */
  1784. /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
  1785. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  1786. /* .. IBUF_DISABLE_MODE = 0 */
  1787. /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
  1788. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  1789. /* .. TERM_DISABLE_MODE = 0 */
  1790. /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
  1791. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  1792. /* .. OUTPUT_EN = 0x3 */
  1793. /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
  1794. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  1795. /* .. PULLUP_EN = 0x0 */
  1796. /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
  1797. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1798. /* .. */
  1799. EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
  1800. /* .. reserved_INP_POWER = 0x0 */
  1801. /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
  1802. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1803. /* .. INP_TYPE = 0x0 */
  1804. /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
  1805. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  1806. /* .. DCI_UPDATE_B = 0x0 */
  1807. /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
  1808. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1809. /* .. TERM_EN = 0x0 */
  1810. /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
  1811. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  1812. /* .. DCI_TYPE = 0x0 */
  1813. /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
  1814. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  1815. /* .. IBUF_DISABLE_MODE = 0x0 */
  1816. /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
  1817. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  1818. /* .. TERM_DISABLE_MODE = 0x0 */
  1819. /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
  1820. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  1821. /* .. OUTPUT_EN = 0x3 */
  1822. /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
  1823. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  1824. /* .. PULLUP_EN = 0x0 */
  1825. /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
  1826. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  1827. /* .. */
  1828. EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
  1829. /* .. reserved_DRIVE_P = 0x1c */
  1830. /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
  1831. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  1832. /* .. reserved_DRIVE_N = 0xc */
  1833. /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
  1834. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  1835. /* .. reserved_SLEW_P = 0x3 */
  1836. /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
  1837. /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
  1838. /* .. reserved_SLEW_N = 0x3 */
  1839. /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
  1840. /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
  1841. /* .. reserved_GTL = 0x0 */
  1842. /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
  1843. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  1844. /* .. reserved_RTERM = 0x0 */
  1845. /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
  1846. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  1847. /* .. */
  1848. EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
  1849. /* .. reserved_DRIVE_P = 0x1c */
  1850. /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
  1851. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  1852. /* .. reserved_DRIVE_N = 0xc */
  1853. /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
  1854. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  1855. /* .. reserved_SLEW_P = 0x6 */
  1856. /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
  1857. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  1858. /* .. reserved_SLEW_N = 0x1f */
  1859. /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
  1860. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  1861. /* .. reserved_GTL = 0x0 */
  1862. /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
  1863. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  1864. /* .. reserved_RTERM = 0x0 */
  1865. /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
  1866. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  1867. /* .. */
  1868. EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
  1869. /* .. reserved_DRIVE_P = 0x1c */
  1870. /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
  1871. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  1872. /* .. reserved_DRIVE_N = 0xc */
  1873. /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
  1874. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  1875. /* .. reserved_SLEW_P = 0x6 */
  1876. /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
  1877. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  1878. /* .. reserved_SLEW_N = 0x1f */
  1879. /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
  1880. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  1881. /* .. reserved_GTL = 0x0 */
  1882. /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
  1883. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  1884. /* .. reserved_RTERM = 0x0 */
  1885. /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
  1886. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  1887. /* .. */
  1888. EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
  1889. /* .. reserved_DRIVE_P = 0x1c */
  1890. /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
  1891. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  1892. /* .. reserved_DRIVE_N = 0xc */
  1893. /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
  1894. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  1895. /* .. reserved_SLEW_P = 0x6 */
  1896. /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
  1897. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  1898. /* .. reserved_SLEW_N = 0x1f */
  1899. /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
  1900. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  1901. /* .. reserved_GTL = 0x0 */
  1902. /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
  1903. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  1904. /* .. reserved_RTERM = 0x0 */
  1905. /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
  1906. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  1907. /* .. */
  1908. EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
  1909. /* .. VREF_INT_EN = 0x0 */
  1910. /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
  1911. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1912. /* .. VREF_SEL = 0x0 */
  1913. /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
  1914. /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
  1915. /* .. VREF_EXT_EN = 0x3 */
  1916. /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
  1917. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  1918. /* .. reserved_VREF_PULLUP_EN = 0x0 */
  1919. /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
  1920. /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
  1921. /* .. REFIO_EN = 0x1 */
  1922. /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
  1923. /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
  1924. /* .. reserved_REFIO_TEST = 0x0 */
  1925. /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
  1926. /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
  1927. /* .. reserved_REFIO_PULLUP_EN = 0x0 */
  1928. /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
  1929. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  1930. /* .. reserved_DRST_B_PULLUP_EN = 0x0 */
  1931. /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
  1932. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  1933. /* .. reserved_CKE_PULLUP_EN = 0x0 */
  1934. /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
  1935. /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  1936. /* .. */
  1937. EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
  1938. /* .. .. START: ASSERT RESET */
  1939. /* .. .. RESET = 1 */
  1940. /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
  1941. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1942. /* .. .. */
  1943. EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
  1944. /* .. .. FINISH: ASSERT RESET */
  1945. /* .. .. START: DEASSERT RESET */
  1946. /* .. .. RESET = 0 */
  1947. /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
  1948. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  1949. /* .. .. reserved_VRN_OUT = 0x1 */
  1950. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  1951. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  1952. /* .. .. */
  1953. EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
  1954. /* .. .. FINISH: DEASSERT RESET */
  1955. /* .. .. RESET = 0x1 */
  1956. /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
  1957. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  1958. /* .. .. ENABLE = 0x1 */
  1959. /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
  1960. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  1961. /* .. .. reserved_VRP_TRI = 0x0 */
  1962. /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
  1963. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  1964. /* .. .. reserved_VRN_TRI = 0x0 */
  1965. /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
  1966. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  1967. /* .. .. reserved_VRP_OUT = 0x0 */
  1968. /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
  1969. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  1970. /* .. .. reserved_VRN_OUT = 0x1 */
  1971. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  1972. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  1973. /* .. .. NREF_OPT1 = 0x0 */
  1974. /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
  1975. /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
  1976. /* .. .. NREF_OPT2 = 0x0 */
  1977. /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
  1978. /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
  1979. /* .. .. NREF_OPT4 = 0x1 */
  1980. /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
  1981. /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
  1982. /* .. .. PREF_OPT1 = 0x0 */
  1983. /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
  1984. /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
  1985. /* .. .. PREF_OPT2 = 0x0 */
  1986. /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
  1987. /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
  1988. /* .. .. UPDATE_CONTROL = 0x0 */
  1989. /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
  1990. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  1991. /* .. .. reserved_INIT_COMPLETE = 0x0 */
  1992. /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
  1993. /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  1994. /* .. .. reserved_TST_CLK = 0x0 */
  1995. /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
  1996. /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  1997. /* .. .. reserved_TST_HLN = 0x0 */
  1998. /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
  1999. /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  2000. /* .. .. reserved_TST_HLP = 0x0 */
  2001. /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
  2002. /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  2003. /* .. .. reserved_TST_RST = 0x0 */
  2004. /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
  2005. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  2006. /* .. .. reserved_INT_DCI_EN = 0x0 */
  2007. /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
  2008. /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
  2009. /* .. .. */
  2010. EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
  2011. /* .. FINISH: DDRIOB SETTINGS */
  2012. /* .. START: MIO PROGRAMMING */
  2013. /* .. TRI_ENABLE = 0 */
  2014. /* .. ==> 0XF8000700[0:0] = 0x00000000U */
  2015. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2016. /* .. L0_SEL = 0 */
  2017. /* .. ==> 0XF8000700[1:1] = 0x00000000U */
  2018. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2019. /* .. L1_SEL = 0 */
  2020. /* .. ==> 0XF8000700[2:2] = 0x00000000U */
  2021. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2022. /* .. L2_SEL = 0 */
  2023. /* .. ==> 0XF8000700[4:3] = 0x00000000U */
  2024. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2025. /* .. L3_SEL = 0 */
  2026. /* .. ==> 0XF8000700[7:5] = 0x00000000U */
  2027. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2028. /* .. Speed = 0 */
  2029. /* .. ==> 0XF8000700[8:8] = 0x00000000U */
  2030. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2031. /* .. IO_Type = 3 */
  2032. /* .. ==> 0XF8000700[11:9] = 0x00000003U */
  2033. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2034. /* .. PULLUP = 1 */
  2035. /* .. ==> 0XF8000700[12:12] = 0x00000001U */
  2036. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2037. /* .. DisableRcvr = 0 */
  2038. /* .. ==> 0XF8000700[13:13] = 0x00000000U */
  2039. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2040. /* .. */
  2041. EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
  2042. /* .. TRI_ENABLE = 0 */
  2043. /* .. ==> 0XF8000704[0:0] = 0x00000000U */
  2044. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2045. /* .. L0_SEL = 1 */
  2046. /* .. ==> 0XF8000704[1:1] = 0x00000001U */
  2047. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2048. /* .. L1_SEL = 0 */
  2049. /* .. ==> 0XF8000704[2:2] = 0x00000000U */
  2050. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2051. /* .. L2_SEL = 0 */
  2052. /* .. ==> 0XF8000704[4:3] = 0x00000000U */
  2053. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2054. /* .. L3_SEL = 0 */
  2055. /* .. ==> 0XF8000704[7:5] = 0x00000000U */
  2056. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2057. /* .. Speed = 1 */
  2058. /* .. ==> 0XF8000704[8:8] = 0x00000001U */
  2059. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2060. /* .. IO_Type = 3 */
  2061. /* .. ==> 0XF8000704[11:9] = 0x00000003U */
  2062. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2063. /* .. PULLUP = 0 */
  2064. /* .. ==> 0XF8000704[12:12] = 0x00000000U */
  2065. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2066. /* .. DisableRcvr = 0 */
  2067. /* .. ==> 0XF8000704[13:13] = 0x00000000U */
  2068. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2069. /* .. */
  2070. EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
  2071. /* .. TRI_ENABLE = 0 */
  2072. /* .. ==> 0XF8000708[0:0] = 0x00000000U */
  2073. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2074. /* .. L0_SEL = 1 */
  2075. /* .. ==> 0XF8000708[1:1] = 0x00000001U */
  2076. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2077. /* .. L1_SEL = 0 */
  2078. /* .. ==> 0XF8000708[2:2] = 0x00000000U */
  2079. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2080. /* .. L2_SEL = 0 */
  2081. /* .. ==> 0XF8000708[4:3] = 0x00000000U */
  2082. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2083. /* .. L3_SEL = 0 */
  2084. /* .. ==> 0XF8000708[7:5] = 0x00000000U */
  2085. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2086. /* .. Speed = 1 */
  2087. /* .. ==> 0XF8000708[8:8] = 0x00000001U */
  2088. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2089. /* .. IO_Type = 3 */
  2090. /* .. ==> 0XF8000708[11:9] = 0x00000003U */
  2091. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2092. /* .. PULLUP = 0 */
  2093. /* .. ==> 0XF8000708[12:12] = 0x00000000U */
  2094. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2095. /* .. DisableRcvr = 0 */
  2096. /* .. ==> 0XF8000708[13:13] = 0x00000000U */
  2097. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2098. /* .. */
  2099. EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
  2100. /* .. TRI_ENABLE = 0 */
  2101. /* .. ==> 0XF800070C[0:0] = 0x00000000U */
  2102. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2103. /* .. L0_SEL = 1 */
  2104. /* .. ==> 0XF800070C[1:1] = 0x00000001U */
  2105. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2106. /* .. L1_SEL = 0 */
  2107. /* .. ==> 0XF800070C[2:2] = 0x00000000U */
  2108. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2109. /* .. L2_SEL = 0 */
  2110. /* .. ==> 0XF800070C[4:3] = 0x00000000U */
  2111. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2112. /* .. L3_SEL = 0 */
  2113. /* .. ==> 0XF800070C[7:5] = 0x00000000U */
  2114. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2115. /* .. Speed = 1 */
  2116. /* .. ==> 0XF800070C[8:8] = 0x00000001U */
  2117. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2118. /* .. IO_Type = 3 */
  2119. /* .. ==> 0XF800070C[11:9] = 0x00000003U */
  2120. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2121. /* .. PULLUP = 0 */
  2122. /* .. ==> 0XF800070C[12:12] = 0x00000000U */
  2123. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2124. /* .. DisableRcvr = 0 */
  2125. /* .. ==> 0XF800070C[13:13] = 0x00000000U */
  2126. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2127. /* .. */
  2128. EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
  2129. /* .. TRI_ENABLE = 0 */
  2130. /* .. ==> 0XF8000710[0:0] = 0x00000000U */
  2131. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2132. /* .. L0_SEL = 1 */
  2133. /* .. ==> 0XF8000710[1:1] = 0x00000001U */
  2134. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2135. /* .. L1_SEL = 0 */
  2136. /* .. ==> 0XF8000710[2:2] = 0x00000000U */
  2137. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2138. /* .. L2_SEL = 0 */
  2139. /* .. ==> 0XF8000710[4:3] = 0x00000000U */
  2140. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2141. /* .. L3_SEL = 0 */
  2142. /* .. ==> 0XF8000710[7:5] = 0x00000000U */
  2143. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2144. /* .. Speed = 1 */
  2145. /* .. ==> 0XF8000710[8:8] = 0x00000001U */
  2146. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2147. /* .. IO_Type = 3 */
  2148. /* .. ==> 0XF8000710[11:9] = 0x00000003U */
  2149. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2150. /* .. PULLUP = 0 */
  2151. /* .. ==> 0XF8000710[12:12] = 0x00000000U */
  2152. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2153. /* .. DisableRcvr = 0 */
  2154. /* .. ==> 0XF8000710[13:13] = 0x00000000U */
  2155. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2156. /* .. */
  2157. EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
  2158. /* .. TRI_ENABLE = 0 */
  2159. /* .. ==> 0XF8000714[0:0] = 0x00000000U */
  2160. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2161. /* .. L0_SEL = 1 */
  2162. /* .. ==> 0XF8000714[1:1] = 0x00000001U */
  2163. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2164. /* .. L1_SEL = 0 */
  2165. /* .. ==> 0XF8000714[2:2] = 0x00000000U */
  2166. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2167. /* .. L2_SEL = 0 */
  2168. /* .. ==> 0XF8000714[4:3] = 0x00000000U */
  2169. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2170. /* .. L3_SEL = 0 */
  2171. /* .. ==> 0XF8000714[7:5] = 0x00000000U */
  2172. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2173. /* .. Speed = 1 */
  2174. /* .. ==> 0XF8000714[8:8] = 0x00000001U */
  2175. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2176. /* .. IO_Type = 3 */
  2177. /* .. ==> 0XF8000714[11:9] = 0x00000003U */
  2178. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2179. /* .. PULLUP = 0 */
  2180. /* .. ==> 0XF8000714[12:12] = 0x00000000U */
  2181. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2182. /* .. DisableRcvr = 0 */
  2183. /* .. ==> 0XF8000714[13:13] = 0x00000000U */
  2184. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2185. /* .. */
  2186. EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
  2187. /* .. TRI_ENABLE = 0 */
  2188. /* .. ==> 0XF8000718[0:0] = 0x00000000U */
  2189. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2190. /* .. L0_SEL = 1 */
  2191. /* .. ==> 0XF8000718[1:1] = 0x00000001U */
  2192. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2193. /* .. L1_SEL = 0 */
  2194. /* .. ==> 0XF8000718[2:2] = 0x00000000U */
  2195. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2196. /* .. L2_SEL = 0 */
  2197. /* .. ==> 0XF8000718[4:3] = 0x00000000U */
  2198. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2199. /* .. L3_SEL = 0 */
  2200. /* .. ==> 0XF8000718[7:5] = 0x00000000U */
  2201. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2202. /* .. Speed = 1 */
  2203. /* .. ==> 0XF8000718[8:8] = 0x00000001U */
  2204. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2205. /* .. IO_Type = 3 */
  2206. /* .. ==> 0XF8000718[11:9] = 0x00000003U */
  2207. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2208. /* .. PULLUP = 0 */
  2209. /* .. ==> 0XF8000718[12:12] = 0x00000000U */
  2210. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2211. /* .. DisableRcvr = 0 */
  2212. /* .. ==> 0XF8000718[13:13] = 0x00000000U */
  2213. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2214. /* .. */
  2215. EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
  2216. /* .. TRI_ENABLE = 0 */
  2217. /* .. ==> 0XF800071C[0:0] = 0x00000000U */
  2218. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2219. /* .. L0_SEL = 0 */
  2220. /* .. ==> 0XF800071C[1:1] = 0x00000000U */
  2221. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2222. /* .. L1_SEL = 0 */
  2223. /* .. ==> 0XF800071C[2:2] = 0x00000000U */
  2224. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2225. /* .. L2_SEL = 0 */
  2226. /* .. ==> 0XF800071C[4:3] = 0x00000000U */
  2227. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2228. /* .. L3_SEL = 0 */
  2229. /* .. ==> 0XF800071C[7:5] = 0x00000000U */
  2230. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2231. /* .. Speed = 0 */
  2232. /* .. ==> 0XF800071C[8:8] = 0x00000000U */
  2233. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2234. /* .. IO_Type = 3 */
  2235. /* .. ==> 0XF800071C[11:9] = 0x00000003U */
  2236. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2237. /* .. PULLUP = 0 */
  2238. /* .. ==> 0XF800071C[12:12] = 0x00000000U */
  2239. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2240. /* .. DisableRcvr = 0 */
  2241. /* .. ==> 0XF800071C[13:13] = 0x00000000U */
  2242. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2243. /* .. */
  2244. EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
  2245. /* .. TRI_ENABLE = 0 */
  2246. /* .. ==> 0XF8000720[0:0] = 0x00000000U */
  2247. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2248. /* .. L0_SEL = 1 */
  2249. /* .. ==> 0XF8000720[1:1] = 0x00000001U */
  2250. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2251. /* .. L1_SEL = 0 */
  2252. /* .. ==> 0XF8000720[2:2] = 0x00000000U */
  2253. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2254. /* .. L2_SEL = 0 */
  2255. /* .. ==> 0XF8000720[4:3] = 0x00000000U */
  2256. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2257. /* .. L3_SEL = 0 */
  2258. /* .. ==> 0XF8000720[7:5] = 0x00000000U */
  2259. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2260. /* .. Speed = 1 */
  2261. /* .. ==> 0XF8000720[8:8] = 0x00000001U */
  2262. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2263. /* .. IO_Type = 3 */
  2264. /* .. ==> 0XF8000720[11:9] = 0x00000003U */
  2265. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2266. /* .. PULLUP = 0 */
  2267. /* .. ==> 0XF8000720[12:12] = 0x00000000U */
  2268. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2269. /* .. DisableRcvr = 0 */
  2270. /* .. ==> 0XF8000720[13:13] = 0x00000000U */
  2271. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2272. /* .. */
  2273. EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
  2274. /* .. TRI_ENABLE = 0 */
  2275. /* .. ==> 0XF8000724[0:0] = 0x00000000U */
  2276. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2277. /* .. L0_SEL = 0 */
  2278. /* .. ==> 0XF8000724[1:1] = 0x00000000U */
  2279. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2280. /* .. L1_SEL = 0 */
  2281. /* .. ==> 0XF8000724[2:2] = 0x00000000U */
  2282. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2283. /* .. L2_SEL = 0 */
  2284. /* .. ==> 0XF8000724[4:3] = 0x00000000U */
  2285. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2286. /* .. L3_SEL = 0 */
  2287. /* .. ==> 0XF8000724[7:5] = 0x00000000U */
  2288. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2289. /* .. Speed = 0 */
  2290. /* .. ==> 0XF8000724[8:8] = 0x00000000U */
  2291. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2292. /* .. IO_Type = 3 */
  2293. /* .. ==> 0XF8000724[11:9] = 0x00000003U */
  2294. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2295. /* .. PULLUP = 1 */
  2296. /* .. ==> 0XF8000724[12:12] = 0x00000001U */
  2297. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2298. /* .. DisableRcvr = 0 */
  2299. /* .. ==> 0XF8000724[13:13] = 0x00000000U */
  2300. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2301. /* .. */
  2302. EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
  2303. /* .. TRI_ENABLE = 0 */
  2304. /* .. ==> 0XF8000728[0:0] = 0x00000000U */
  2305. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2306. /* .. L0_SEL = 0 */
  2307. /* .. ==> 0XF8000728[1:1] = 0x00000000U */
  2308. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2309. /* .. L1_SEL = 0 */
  2310. /* .. ==> 0XF8000728[2:2] = 0x00000000U */
  2311. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2312. /* .. L2_SEL = 0 */
  2313. /* .. ==> 0XF8000728[4:3] = 0x00000000U */
  2314. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2315. /* .. L3_SEL = 0 */
  2316. /* .. ==> 0XF8000728[7:5] = 0x00000000U */
  2317. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2318. /* .. Speed = 0 */
  2319. /* .. ==> 0XF8000728[8:8] = 0x00000000U */
  2320. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2321. /* .. IO_Type = 3 */
  2322. /* .. ==> 0XF8000728[11:9] = 0x00000003U */
  2323. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2324. /* .. PULLUP = 1 */
  2325. /* .. ==> 0XF8000728[12:12] = 0x00000001U */
  2326. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2327. /* .. DisableRcvr = 0 */
  2328. /* .. ==> 0XF8000728[13:13] = 0x00000000U */
  2329. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2330. /* .. */
  2331. EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
  2332. /* .. TRI_ENABLE = 0 */
  2333. /* .. ==> 0XF800072C[0:0] = 0x00000000U */
  2334. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2335. /* .. L0_SEL = 0 */
  2336. /* .. ==> 0XF800072C[1:1] = 0x00000000U */
  2337. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2338. /* .. L1_SEL = 0 */
  2339. /* .. ==> 0XF800072C[2:2] = 0x00000000U */
  2340. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2341. /* .. L2_SEL = 0 */
  2342. /* .. ==> 0XF800072C[4:3] = 0x00000000U */
  2343. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2344. /* .. L3_SEL = 0 */
  2345. /* .. ==> 0XF800072C[7:5] = 0x00000000U */
  2346. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2347. /* .. Speed = 0 */
  2348. /* .. ==> 0XF800072C[8:8] = 0x00000000U */
  2349. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2350. /* .. IO_Type = 3 */
  2351. /* .. ==> 0XF800072C[11:9] = 0x00000003U */
  2352. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2353. /* .. PULLUP = 1 */
  2354. /* .. ==> 0XF800072C[12:12] = 0x00000001U */
  2355. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2356. /* .. DisableRcvr = 0 */
  2357. /* .. ==> 0XF800072C[13:13] = 0x00000000U */
  2358. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2359. /* .. */
  2360. EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
  2361. /* .. TRI_ENABLE = 0 */
  2362. /* .. ==> 0XF8000730[0:0] = 0x00000000U */
  2363. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2364. /* .. L0_SEL = 0 */
  2365. /* .. ==> 0XF8000730[1:1] = 0x00000000U */
  2366. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2367. /* .. L1_SEL = 0 */
  2368. /* .. ==> 0XF8000730[2:2] = 0x00000000U */
  2369. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2370. /* .. L2_SEL = 0 */
  2371. /* .. ==> 0XF8000730[4:3] = 0x00000000U */
  2372. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2373. /* .. L3_SEL = 0 */
  2374. /* .. ==> 0XF8000730[7:5] = 0x00000000U */
  2375. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2376. /* .. Speed = 0 */
  2377. /* .. ==> 0XF8000730[8:8] = 0x00000000U */
  2378. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2379. /* .. IO_Type = 3 */
  2380. /* .. ==> 0XF8000730[11:9] = 0x00000003U */
  2381. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2382. /* .. PULLUP = 1 */
  2383. /* .. ==> 0XF8000730[12:12] = 0x00000001U */
  2384. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2385. /* .. DisableRcvr = 0 */
  2386. /* .. ==> 0XF8000730[13:13] = 0x00000000U */
  2387. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2388. /* .. */
  2389. EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
  2390. /* .. TRI_ENABLE = 0 */
  2391. /* .. ==> 0XF8000734[0:0] = 0x00000000U */
  2392. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2393. /* .. L0_SEL = 0 */
  2394. /* .. ==> 0XF8000734[1:1] = 0x00000000U */
  2395. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2396. /* .. L1_SEL = 0 */
  2397. /* .. ==> 0XF8000734[2:2] = 0x00000000U */
  2398. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2399. /* .. L2_SEL = 0 */
  2400. /* .. ==> 0XF8000734[4:3] = 0x00000000U */
  2401. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2402. /* .. L3_SEL = 0 */
  2403. /* .. ==> 0XF8000734[7:5] = 0x00000000U */
  2404. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2405. /* .. Speed = 0 */
  2406. /* .. ==> 0XF8000734[8:8] = 0x00000000U */
  2407. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2408. /* .. IO_Type = 3 */
  2409. /* .. ==> 0XF8000734[11:9] = 0x00000003U */
  2410. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2411. /* .. PULLUP = 1 */
  2412. /* .. ==> 0XF8000734[12:12] = 0x00000001U */
  2413. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2414. /* .. DisableRcvr = 0 */
  2415. /* .. ==> 0XF8000734[13:13] = 0x00000000U */
  2416. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2417. /* .. */
  2418. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
  2419. /* .. TRI_ENABLE = 0 */
  2420. /* .. ==> 0XF8000738[0:0] = 0x00000000U */
  2421. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2422. /* .. L0_SEL = 0 */
  2423. /* .. ==> 0XF8000738[1:1] = 0x00000000U */
  2424. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2425. /* .. L1_SEL = 0 */
  2426. /* .. ==> 0XF8000738[2:2] = 0x00000000U */
  2427. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2428. /* .. L2_SEL = 0 */
  2429. /* .. ==> 0XF8000738[4:3] = 0x00000000U */
  2430. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2431. /* .. L3_SEL = 0 */
  2432. /* .. ==> 0XF8000738[7:5] = 0x00000000U */
  2433. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2434. /* .. Speed = 0 */
  2435. /* .. ==> 0XF8000738[8:8] = 0x00000000U */
  2436. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2437. /* .. IO_Type = 3 */
  2438. /* .. ==> 0XF8000738[11:9] = 0x00000003U */
  2439. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2440. /* .. PULLUP = 1 */
  2441. /* .. ==> 0XF8000738[12:12] = 0x00000001U */
  2442. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2443. /* .. DisableRcvr = 0 */
  2444. /* .. ==> 0XF8000738[13:13] = 0x00000000U */
  2445. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2446. /* .. */
  2447. EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
  2448. /* .. TRI_ENABLE = 0 */
  2449. /* .. ==> 0XF800073C[0:0] = 0x00000000U */
  2450. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2451. /* .. L0_SEL = 0 */
  2452. /* .. ==> 0XF800073C[1:1] = 0x00000000U */
  2453. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2454. /* .. L1_SEL = 0 */
  2455. /* .. ==> 0XF800073C[2:2] = 0x00000000U */
  2456. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2457. /* .. L2_SEL = 0 */
  2458. /* .. ==> 0XF800073C[4:3] = 0x00000000U */
  2459. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2460. /* .. L3_SEL = 0 */
  2461. /* .. ==> 0XF800073C[7:5] = 0x00000000U */
  2462. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2463. /* .. Speed = 0 */
  2464. /* .. ==> 0XF800073C[8:8] = 0x00000000U */
  2465. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  2466. /* .. IO_Type = 3 */
  2467. /* .. ==> 0XF800073C[11:9] = 0x00000003U */
  2468. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  2469. /* .. PULLUP = 1 */
  2470. /* .. ==> 0XF800073C[12:12] = 0x00000001U */
  2471. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  2472. /* .. DisableRcvr = 0 */
  2473. /* .. ==> 0XF800073C[13:13] = 0x00000000U */
  2474. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2475. /* .. */
  2476. EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
  2477. /* .. TRI_ENABLE = 0 */
  2478. /* .. ==> 0XF8000740[0:0] = 0x00000000U */
  2479. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2480. /* .. L0_SEL = 1 */
  2481. /* .. ==> 0XF8000740[1:1] = 0x00000001U */
  2482. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2483. /* .. L1_SEL = 0 */
  2484. /* .. ==> 0XF8000740[2:2] = 0x00000000U */
  2485. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2486. /* .. L2_SEL = 0 */
  2487. /* .. ==> 0XF8000740[4:3] = 0x00000000U */
  2488. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2489. /* .. L3_SEL = 0 */
  2490. /* .. ==> 0XF8000740[7:5] = 0x00000000U */
  2491. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2492. /* .. Speed = 1 */
  2493. /* .. ==> 0XF8000740[8:8] = 0x00000001U */
  2494. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2495. /* .. IO_Type = 4 */
  2496. /* .. ==> 0XF8000740[11:9] = 0x00000004U */
  2497. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2498. /* .. PULLUP = 0 */
  2499. /* .. ==> 0XF8000740[12:12] = 0x00000000U */
  2500. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2501. /* .. DisableRcvr = 1 */
  2502. /* .. ==> 0XF8000740[13:13] = 0x00000001U */
  2503. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  2504. /* .. */
  2505. EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
  2506. /* .. TRI_ENABLE = 0 */
  2507. /* .. ==> 0XF8000744[0:0] = 0x00000000U */
  2508. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2509. /* .. L0_SEL = 1 */
  2510. /* .. ==> 0XF8000744[1:1] = 0x00000001U */
  2511. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2512. /* .. L1_SEL = 0 */
  2513. /* .. ==> 0XF8000744[2:2] = 0x00000000U */
  2514. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2515. /* .. L2_SEL = 0 */
  2516. /* .. ==> 0XF8000744[4:3] = 0x00000000U */
  2517. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2518. /* .. L3_SEL = 0 */
  2519. /* .. ==> 0XF8000744[7:5] = 0x00000000U */
  2520. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2521. /* .. Speed = 1 */
  2522. /* .. ==> 0XF8000744[8:8] = 0x00000001U */
  2523. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2524. /* .. IO_Type = 4 */
  2525. /* .. ==> 0XF8000744[11:9] = 0x00000004U */
  2526. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2527. /* .. PULLUP = 0 */
  2528. /* .. ==> 0XF8000744[12:12] = 0x00000000U */
  2529. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2530. /* .. DisableRcvr = 1 */
  2531. /* .. ==> 0XF8000744[13:13] = 0x00000001U */
  2532. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  2533. /* .. */
  2534. EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
  2535. /* .. TRI_ENABLE = 0 */
  2536. /* .. ==> 0XF8000748[0:0] = 0x00000000U */
  2537. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2538. /* .. L0_SEL = 1 */
  2539. /* .. ==> 0XF8000748[1:1] = 0x00000001U */
  2540. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2541. /* .. L1_SEL = 0 */
  2542. /* .. ==> 0XF8000748[2:2] = 0x00000000U */
  2543. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2544. /* .. L2_SEL = 0 */
  2545. /* .. ==> 0XF8000748[4:3] = 0x00000000U */
  2546. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2547. /* .. L3_SEL = 0 */
  2548. /* .. ==> 0XF8000748[7:5] = 0x00000000U */
  2549. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2550. /* .. Speed = 1 */
  2551. /* .. ==> 0XF8000748[8:8] = 0x00000001U */
  2552. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2553. /* .. IO_Type = 4 */
  2554. /* .. ==> 0XF8000748[11:9] = 0x00000004U */
  2555. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2556. /* .. PULLUP = 0 */
  2557. /* .. ==> 0XF8000748[12:12] = 0x00000000U */
  2558. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2559. /* .. DisableRcvr = 1 */
  2560. /* .. ==> 0XF8000748[13:13] = 0x00000001U */
  2561. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  2562. /* .. */
  2563. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
  2564. /* .. TRI_ENABLE = 0 */
  2565. /* .. ==> 0XF800074C[0:0] = 0x00000000U */
  2566. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2567. /* .. L0_SEL = 1 */
  2568. /* .. ==> 0XF800074C[1:1] = 0x00000001U */
  2569. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2570. /* .. L1_SEL = 0 */
  2571. /* .. ==> 0XF800074C[2:2] = 0x00000000U */
  2572. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2573. /* .. L2_SEL = 0 */
  2574. /* .. ==> 0XF800074C[4:3] = 0x00000000U */
  2575. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2576. /* .. L3_SEL = 0 */
  2577. /* .. ==> 0XF800074C[7:5] = 0x00000000U */
  2578. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2579. /* .. Speed = 1 */
  2580. /* .. ==> 0XF800074C[8:8] = 0x00000001U */
  2581. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2582. /* .. IO_Type = 4 */
  2583. /* .. ==> 0XF800074C[11:9] = 0x00000004U */
  2584. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2585. /* .. PULLUP = 0 */
  2586. /* .. ==> 0XF800074C[12:12] = 0x00000000U */
  2587. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2588. /* .. DisableRcvr = 1 */
  2589. /* .. ==> 0XF800074C[13:13] = 0x00000001U */
  2590. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  2591. /* .. */
  2592. EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
  2593. /* .. TRI_ENABLE = 0 */
  2594. /* .. ==> 0XF8000750[0:0] = 0x00000000U */
  2595. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2596. /* .. L0_SEL = 1 */
  2597. /* .. ==> 0XF8000750[1:1] = 0x00000001U */
  2598. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2599. /* .. L1_SEL = 0 */
  2600. /* .. ==> 0XF8000750[2:2] = 0x00000000U */
  2601. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2602. /* .. L2_SEL = 0 */
  2603. /* .. ==> 0XF8000750[4:3] = 0x00000000U */
  2604. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2605. /* .. L3_SEL = 0 */
  2606. /* .. ==> 0XF8000750[7:5] = 0x00000000U */
  2607. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2608. /* .. Speed = 1 */
  2609. /* .. ==> 0XF8000750[8:8] = 0x00000001U */
  2610. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2611. /* .. IO_Type = 4 */
  2612. /* .. ==> 0XF8000750[11:9] = 0x00000004U */
  2613. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2614. /* .. PULLUP = 0 */
  2615. /* .. ==> 0XF8000750[12:12] = 0x00000000U */
  2616. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2617. /* .. DisableRcvr = 1 */
  2618. /* .. ==> 0XF8000750[13:13] = 0x00000001U */
  2619. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  2620. /* .. */
  2621. EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
  2622. /* .. TRI_ENABLE = 0 */
  2623. /* .. ==> 0XF8000754[0:0] = 0x00000000U */
  2624. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2625. /* .. L0_SEL = 1 */
  2626. /* .. ==> 0XF8000754[1:1] = 0x00000001U */
  2627. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2628. /* .. L1_SEL = 0 */
  2629. /* .. ==> 0XF8000754[2:2] = 0x00000000U */
  2630. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2631. /* .. L2_SEL = 0 */
  2632. /* .. ==> 0XF8000754[4:3] = 0x00000000U */
  2633. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2634. /* .. L3_SEL = 0 */
  2635. /* .. ==> 0XF8000754[7:5] = 0x00000000U */
  2636. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2637. /* .. Speed = 1 */
  2638. /* .. ==> 0XF8000754[8:8] = 0x00000001U */
  2639. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2640. /* .. IO_Type = 4 */
  2641. /* .. ==> 0XF8000754[11:9] = 0x00000004U */
  2642. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2643. /* .. PULLUP = 0 */
  2644. /* .. ==> 0XF8000754[12:12] = 0x00000000U */
  2645. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2646. /* .. DisableRcvr = 1 */
  2647. /* .. ==> 0XF8000754[13:13] = 0x00000001U */
  2648. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  2649. /* .. */
  2650. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
  2651. /* .. TRI_ENABLE = 1 */
  2652. /* .. ==> 0XF8000758[0:0] = 0x00000001U */
  2653. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2654. /* .. L0_SEL = 1 */
  2655. /* .. ==> 0XF8000758[1:1] = 0x00000001U */
  2656. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2657. /* .. L1_SEL = 0 */
  2658. /* .. ==> 0XF8000758[2:2] = 0x00000000U */
  2659. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2660. /* .. L2_SEL = 0 */
  2661. /* .. ==> 0XF8000758[4:3] = 0x00000000U */
  2662. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2663. /* .. L3_SEL = 0 */
  2664. /* .. ==> 0XF8000758[7:5] = 0x00000000U */
  2665. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2666. /* .. Speed = 1 */
  2667. /* .. ==> 0XF8000758[8:8] = 0x00000001U */
  2668. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2669. /* .. IO_Type = 4 */
  2670. /* .. ==> 0XF8000758[11:9] = 0x00000004U */
  2671. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2672. /* .. PULLUP = 0 */
  2673. /* .. ==> 0XF8000758[12:12] = 0x00000000U */
  2674. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2675. /* .. DisableRcvr = 0 */
  2676. /* .. ==> 0XF8000758[13:13] = 0x00000000U */
  2677. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2678. /* .. */
  2679. EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
  2680. /* .. TRI_ENABLE = 1 */
  2681. /* .. ==> 0XF800075C[0:0] = 0x00000001U */
  2682. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2683. /* .. L0_SEL = 1 */
  2684. /* .. ==> 0XF800075C[1:1] = 0x00000001U */
  2685. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2686. /* .. L1_SEL = 0 */
  2687. /* .. ==> 0XF800075C[2:2] = 0x00000000U */
  2688. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2689. /* .. L2_SEL = 0 */
  2690. /* .. ==> 0XF800075C[4:3] = 0x00000000U */
  2691. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2692. /* .. L3_SEL = 0 */
  2693. /* .. ==> 0XF800075C[7:5] = 0x00000000U */
  2694. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2695. /* .. Speed = 1 */
  2696. /* .. ==> 0XF800075C[8:8] = 0x00000001U */
  2697. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2698. /* .. IO_Type = 4 */
  2699. /* .. ==> 0XF800075C[11:9] = 0x00000004U */
  2700. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2701. /* .. PULLUP = 0 */
  2702. /* .. ==> 0XF800075C[12:12] = 0x00000000U */
  2703. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2704. /* .. DisableRcvr = 0 */
  2705. /* .. ==> 0XF800075C[13:13] = 0x00000000U */
  2706. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2707. /* .. */
  2708. EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
  2709. /* .. TRI_ENABLE = 1 */
  2710. /* .. ==> 0XF8000760[0:0] = 0x00000001U */
  2711. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2712. /* .. L0_SEL = 1 */
  2713. /* .. ==> 0XF8000760[1:1] = 0x00000001U */
  2714. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2715. /* .. L1_SEL = 0 */
  2716. /* .. ==> 0XF8000760[2:2] = 0x00000000U */
  2717. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2718. /* .. L2_SEL = 0 */
  2719. /* .. ==> 0XF8000760[4:3] = 0x00000000U */
  2720. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2721. /* .. L3_SEL = 0 */
  2722. /* .. ==> 0XF8000760[7:5] = 0x00000000U */
  2723. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2724. /* .. Speed = 1 */
  2725. /* .. ==> 0XF8000760[8:8] = 0x00000001U */
  2726. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2727. /* .. IO_Type = 4 */
  2728. /* .. ==> 0XF8000760[11:9] = 0x00000004U */
  2729. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2730. /* .. PULLUP = 0 */
  2731. /* .. ==> 0XF8000760[12:12] = 0x00000000U */
  2732. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2733. /* .. DisableRcvr = 0 */
  2734. /* .. ==> 0XF8000760[13:13] = 0x00000000U */
  2735. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2736. /* .. */
  2737. EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
  2738. /* .. TRI_ENABLE = 1 */
  2739. /* .. ==> 0XF8000764[0:0] = 0x00000001U */
  2740. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2741. /* .. L0_SEL = 1 */
  2742. /* .. ==> 0XF8000764[1:1] = 0x00000001U */
  2743. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2744. /* .. L1_SEL = 0 */
  2745. /* .. ==> 0XF8000764[2:2] = 0x00000000U */
  2746. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2747. /* .. L2_SEL = 0 */
  2748. /* .. ==> 0XF8000764[4:3] = 0x00000000U */
  2749. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2750. /* .. L3_SEL = 0 */
  2751. /* .. ==> 0XF8000764[7:5] = 0x00000000U */
  2752. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2753. /* .. Speed = 1 */
  2754. /* .. ==> 0XF8000764[8:8] = 0x00000001U */
  2755. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2756. /* .. IO_Type = 4 */
  2757. /* .. ==> 0XF8000764[11:9] = 0x00000004U */
  2758. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2759. /* .. PULLUP = 0 */
  2760. /* .. ==> 0XF8000764[12:12] = 0x00000000U */
  2761. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2762. /* .. DisableRcvr = 0 */
  2763. /* .. ==> 0XF8000764[13:13] = 0x00000000U */
  2764. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2765. /* .. */
  2766. EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
  2767. /* .. TRI_ENABLE = 1 */
  2768. /* .. ==> 0XF8000768[0:0] = 0x00000001U */
  2769. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2770. /* .. L0_SEL = 1 */
  2771. /* .. ==> 0XF8000768[1:1] = 0x00000001U */
  2772. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2773. /* .. L1_SEL = 0 */
  2774. /* .. ==> 0XF8000768[2:2] = 0x00000000U */
  2775. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2776. /* .. L2_SEL = 0 */
  2777. /* .. ==> 0XF8000768[4:3] = 0x00000000U */
  2778. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2779. /* .. L3_SEL = 0 */
  2780. /* .. ==> 0XF8000768[7:5] = 0x00000000U */
  2781. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2782. /* .. Speed = 1 */
  2783. /* .. ==> 0XF8000768[8:8] = 0x00000001U */
  2784. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2785. /* .. IO_Type = 4 */
  2786. /* .. ==> 0XF8000768[11:9] = 0x00000004U */
  2787. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2788. /* .. PULLUP = 0 */
  2789. /* .. ==> 0XF8000768[12:12] = 0x00000000U */
  2790. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2791. /* .. DisableRcvr = 0 */
  2792. /* .. ==> 0XF8000768[13:13] = 0x00000000U */
  2793. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2794. /* .. */
  2795. EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
  2796. /* .. TRI_ENABLE = 1 */
  2797. /* .. ==> 0XF800076C[0:0] = 0x00000001U */
  2798. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2799. /* .. L0_SEL = 1 */
  2800. /* .. ==> 0XF800076C[1:1] = 0x00000001U */
  2801. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  2802. /* .. L1_SEL = 0 */
  2803. /* .. ==> 0XF800076C[2:2] = 0x00000000U */
  2804. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  2805. /* .. L2_SEL = 0 */
  2806. /* .. ==> 0XF800076C[4:3] = 0x00000000U */
  2807. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2808. /* .. L3_SEL = 0 */
  2809. /* .. ==> 0XF800076C[7:5] = 0x00000000U */
  2810. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2811. /* .. Speed = 1 */
  2812. /* .. ==> 0XF800076C[8:8] = 0x00000001U */
  2813. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2814. /* .. IO_Type = 4 */
  2815. /* .. ==> 0XF800076C[11:9] = 0x00000004U */
  2816. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  2817. /* .. PULLUP = 0 */
  2818. /* .. ==> 0XF800076C[12:12] = 0x00000000U */
  2819. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2820. /* .. DisableRcvr = 0 */
  2821. /* .. ==> 0XF800076C[13:13] = 0x00000000U */
  2822. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2823. /* .. */
  2824. EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
  2825. /* .. TRI_ENABLE = 0 */
  2826. /* .. ==> 0XF8000770[0:0] = 0x00000000U */
  2827. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2828. /* .. L0_SEL = 0 */
  2829. /* .. ==> 0XF8000770[1:1] = 0x00000000U */
  2830. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2831. /* .. L1_SEL = 1 */
  2832. /* .. ==> 0XF8000770[2:2] = 0x00000001U */
  2833. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  2834. /* .. L2_SEL = 0 */
  2835. /* .. ==> 0XF8000770[4:3] = 0x00000000U */
  2836. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2837. /* .. L3_SEL = 0 */
  2838. /* .. ==> 0XF8000770[7:5] = 0x00000000U */
  2839. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2840. /* .. Speed = 1 */
  2841. /* .. ==> 0XF8000770[8:8] = 0x00000001U */
  2842. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2843. /* .. IO_Type = 1 */
  2844. /* .. ==> 0XF8000770[11:9] = 0x00000001U */
  2845. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  2846. /* .. PULLUP = 0 */
  2847. /* .. ==> 0XF8000770[12:12] = 0x00000000U */
  2848. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2849. /* .. DisableRcvr = 0 */
  2850. /* .. ==> 0XF8000770[13:13] = 0x00000000U */
  2851. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2852. /* .. */
  2853. EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
  2854. /* .. TRI_ENABLE = 1 */
  2855. /* .. ==> 0XF8000774[0:0] = 0x00000001U */
  2856. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2857. /* .. L0_SEL = 0 */
  2858. /* .. ==> 0XF8000774[1:1] = 0x00000000U */
  2859. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2860. /* .. L1_SEL = 1 */
  2861. /* .. ==> 0XF8000774[2:2] = 0x00000001U */
  2862. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  2863. /* .. L2_SEL = 0 */
  2864. /* .. ==> 0XF8000774[4:3] = 0x00000000U */
  2865. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2866. /* .. L3_SEL = 0 */
  2867. /* .. ==> 0XF8000774[7:5] = 0x00000000U */
  2868. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2869. /* .. Speed = 1 */
  2870. /* .. ==> 0XF8000774[8:8] = 0x00000001U */
  2871. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2872. /* .. IO_Type = 1 */
  2873. /* .. ==> 0XF8000774[11:9] = 0x00000001U */
  2874. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  2875. /* .. PULLUP = 0 */
  2876. /* .. ==> 0XF8000774[12:12] = 0x00000000U */
  2877. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2878. /* .. DisableRcvr = 0 */
  2879. /* .. ==> 0XF8000774[13:13] = 0x00000000U */
  2880. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2881. /* .. */
  2882. EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
  2883. /* .. TRI_ENABLE = 0 */
  2884. /* .. ==> 0XF8000778[0:0] = 0x00000000U */
  2885. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2886. /* .. L0_SEL = 0 */
  2887. /* .. ==> 0XF8000778[1:1] = 0x00000000U */
  2888. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2889. /* .. L1_SEL = 1 */
  2890. /* .. ==> 0XF8000778[2:2] = 0x00000001U */
  2891. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  2892. /* .. L2_SEL = 0 */
  2893. /* .. ==> 0XF8000778[4:3] = 0x00000000U */
  2894. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2895. /* .. L3_SEL = 0 */
  2896. /* .. ==> 0XF8000778[7:5] = 0x00000000U */
  2897. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2898. /* .. Speed = 1 */
  2899. /* .. ==> 0XF8000778[8:8] = 0x00000001U */
  2900. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2901. /* .. IO_Type = 1 */
  2902. /* .. ==> 0XF8000778[11:9] = 0x00000001U */
  2903. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  2904. /* .. PULLUP = 0 */
  2905. /* .. ==> 0XF8000778[12:12] = 0x00000000U */
  2906. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2907. /* .. DisableRcvr = 0 */
  2908. /* .. ==> 0XF8000778[13:13] = 0x00000000U */
  2909. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2910. /* .. */
  2911. EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
  2912. /* .. TRI_ENABLE = 1 */
  2913. /* .. ==> 0XF800077C[0:0] = 0x00000001U */
  2914. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  2915. /* .. L0_SEL = 0 */
  2916. /* .. ==> 0XF800077C[1:1] = 0x00000000U */
  2917. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2918. /* .. L1_SEL = 1 */
  2919. /* .. ==> 0XF800077C[2:2] = 0x00000001U */
  2920. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  2921. /* .. L2_SEL = 0 */
  2922. /* .. ==> 0XF800077C[4:3] = 0x00000000U */
  2923. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2924. /* .. L3_SEL = 0 */
  2925. /* .. ==> 0XF800077C[7:5] = 0x00000000U */
  2926. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2927. /* .. Speed = 1 */
  2928. /* .. ==> 0XF800077C[8:8] = 0x00000001U */
  2929. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2930. /* .. IO_Type = 1 */
  2931. /* .. ==> 0XF800077C[11:9] = 0x00000001U */
  2932. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  2933. /* .. PULLUP = 0 */
  2934. /* .. ==> 0XF800077C[12:12] = 0x00000000U */
  2935. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2936. /* .. DisableRcvr = 0 */
  2937. /* .. ==> 0XF800077C[13:13] = 0x00000000U */
  2938. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2939. /* .. */
  2940. EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
  2941. /* .. TRI_ENABLE = 0 */
  2942. /* .. ==> 0XF8000780[0:0] = 0x00000000U */
  2943. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2944. /* .. L0_SEL = 0 */
  2945. /* .. ==> 0XF8000780[1:1] = 0x00000000U */
  2946. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2947. /* .. L1_SEL = 1 */
  2948. /* .. ==> 0XF8000780[2:2] = 0x00000001U */
  2949. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  2950. /* .. L2_SEL = 0 */
  2951. /* .. ==> 0XF8000780[4:3] = 0x00000000U */
  2952. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2953. /* .. L3_SEL = 0 */
  2954. /* .. ==> 0XF8000780[7:5] = 0x00000000U */
  2955. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2956. /* .. Speed = 1 */
  2957. /* .. ==> 0XF8000780[8:8] = 0x00000001U */
  2958. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2959. /* .. IO_Type = 1 */
  2960. /* .. ==> 0XF8000780[11:9] = 0x00000001U */
  2961. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  2962. /* .. PULLUP = 0 */
  2963. /* .. ==> 0XF8000780[12:12] = 0x00000000U */
  2964. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2965. /* .. DisableRcvr = 0 */
  2966. /* .. ==> 0XF8000780[13:13] = 0x00000000U */
  2967. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2968. /* .. */
  2969. EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
  2970. /* .. TRI_ENABLE = 0 */
  2971. /* .. ==> 0XF8000784[0:0] = 0x00000000U */
  2972. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  2973. /* .. L0_SEL = 0 */
  2974. /* .. ==> 0XF8000784[1:1] = 0x00000000U */
  2975. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  2976. /* .. L1_SEL = 1 */
  2977. /* .. ==> 0XF8000784[2:2] = 0x00000001U */
  2978. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  2979. /* .. L2_SEL = 0 */
  2980. /* .. ==> 0XF8000784[4:3] = 0x00000000U */
  2981. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  2982. /* .. L3_SEL = 0 */
  2983. /* .. ==> 0XF8000784[7:5] = 0x00000000U */
  2984. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  2985. /* .. Speed = 1 */
  2986. /* .. ==> 0XF8000784[8:8] = 0x00000001U */
  2987. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  2988. /* .. IO_Type = 1 */
  2989. /* .. ==> 0XF8000784[11:9] = 0x00000001U */
  2990. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  2991. /* .. PULLUP = 0 */
  2992. /* .. ==> 0XF8000784[12:12] = 0x00000000U */
  2993. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  2994. /* .. DisableRcvr = 0 */
  2995. /* .. ==> 0XF8000784[13:13] = 0x00000000U */
  2996. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  2997. /* .. */
  2998. EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
  2999. /* .. TRI_ENABLE = 0 */
  3000. /* .. ==> 0XF8000788[0:0] = 0x00000000U */
  3001. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3002. /* .. L0_SEL = 0 */
  3003. /* .. ==> 0XF8000788[1:1] = 0x00000000U */
  3004. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3005. /* .. L1_SEL = 1 */
  3006. /* .. ==> 0XF8000788[2:2] = 0x00000001U */
  3007. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  3008. /* .. L2_SEL = 0 */
  3009. /* .. ==> 0XF8000788[4:3] = 0x00000000U */
  3010. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3011. /* .. L3_SEL = 0 */
  3012. /* .. ==> 0XF8000788[7:5] = 0x00000000U */
  3013. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3014. /* .. Speed = 1 */
  3015. /* .. ==> 0XF8000788[8:8] = 0x00000001U */
  3016. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3017. /* .. IO_Type = 1 */
  3018. /* .. ==> 0XF8000788[11:9] = 0x00000001U */
  3019. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3020. /* .. PULLUP = 0 */
  3021. /* .. ==> 0XF8000788[12:12] = 0x00000000U */
  3022. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3023. /* .. DisableRcvr = 0 */
  3024. /* .. ==> 0XF8000788[13:13] = 0x00000000U */
  3025. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3026. /* .. */
  3027. EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
  3028. /* .. TRI_ENABLE = 0 */
  3029. /* .. ==> 0XF800078C[0:0] = 0x00000000U */
  3030. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3031. /* .. L0_SEL = 0 */
  3032. /* .. ==> 0XF800078C[1:1] = 0x00000000U */
  3033. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3034. /* .. L1_SEL = 1 */
  3035. /* .. ==> 0XF800078C[2:2] = 0x00000001U */
  3036. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  3037. /* .. L2_SEL = 0 */
  3038. /* .. ==> 0XF800078C[4:3] = 0x00000000U */
  3039. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3040. /* .. L3_SEL = 0 */
  3041. /* .. ==> 0XF800078C[7:5] = 0x00000000U */
  3042. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3043. /* .. Speed = 1 */
  3044. /* .. ==> 0XF800078C[8:8] = 0x00000001U */
  3045. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3046. /* .. IO_Type = 1 */
  3047. /* .. ==> 0XF800078C[11:9] = 0x00000001U */
  3048. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3049. /* .. PULLUP = 0 */
  3050. /* .. ==> 0XF800078C[12:12] = 0x00000000U */
  3051. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3052. /* .. DisableRcvr = 0 */
  3053. /* .. ==> 0XF800078C[13:13] = 0x00000000U */
  3054. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3055. /* .. */
  3056. EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
  3057. /* .. TRI_ENABLE = 1 */
  3058. /* .. ==> 0XF8000790[0:0] = 0x00000001U */
  3059. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  3060. /* .. L0_SEL = 0 */
  3061. /* .. ==> 0XF8000790[1:1] = 0x00000000U */
  3062. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3063. /* .. L1_SEL = 1 */
  3064. /* .. ==> 0XF8000790[2:2] = 0x00000001U */
  3065. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  3066. /* .. L2_SEL = 0 */
  3067. /* .. ==> 0XF8000790[4:3] = 0x00000000U */
  3068. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3069. /* .. L3_SEL = 0 */
  3070. /* .. ==> 0XF8000790[7:5] = 0x00000000U */
  3071. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3072. /* .. Speed = 1 */
  3073. /* .. ==> 0XF8000790[8:8] = 0x00000001U */
  3074. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3075. /* .. IO_Type = 1 */
  3076. /* .. ==> 0XF8000790[11:9] = 0x00000001U */
  3077. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3078. /* .. PULLUP = 0 */
  3079. /* .. ==> 0XF8000790[12:12] = 0x00000000U */
  3080. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3081. /* .. DisableRcvr = 0 */
  3082. /* .. ==> 0XF8000790[13:13] = 0x00000000U */
  3083. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3084. /* .. */
  3085. EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
  3086. /* .. TRI_ENABLE = 0 */
  3087. /* .. ==> 0XF8000794[0:0] = 0x00000000U */
  3088. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3089. /* .. L0_SEL = 0 */
  3090. /* .. ==> 0XF8000794[1:1] = 0x00000000U */
  3091. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3092. /* .. L1_SEL = 1 */
  3093. /* .. ==> 0XF8000794[2:2] = 0x00000001U */
  3094. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  3095. /* .. L2_SEL = 0 */
  3096. /* .. ==> 0XF8000794[4:3] = 0x00000000U */
  3097. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3098. /* .. L3_SEL = 0 */
  3099. /* .. ==> 0XF8000794[7:5] = 0x00000000U */
  3100. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3101. /* .. Speed = 1 */
  3102. /* .. ==> 0XF8000794[8:8] = 0x00000001U */
  3103. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3104. /* .. IO_Type = 1 */
  3105. /* .. ==> 0XF8000794[11:9] = 0x00000001U */
  3106. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3107. /* .. PULLUP = 0 */
  3108. /* .. ==> 0XF8000794[12:12] = 0x00000000U */
  3109. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3110. /* .. DisableRcvr = 0 */
  3111. /* .. ==> 0XF8000794[13:13] = 0x00000000U */
  3112. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3113. /* .. */
  3114. EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
  3115. /* .. TRI_ENABLE = 0 */
  3116. /* .. ==> 0XF8000798[0:0] = 0x00000000U */
  3117. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3118. /* .. L0_SEL = 0 */
  3119. /* .. ==> 0XF8000798[1:1] = 0x00000000U */
  3120. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3121. /* .. L1_SEL = 1 */
  3122. /* .. ==> 0XF8000798[2:2] = 0x00000001U */
  3123. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  3124. /* .. L2_SEL = 0 */
  3125. /* .. ==> 0XF8000798[4:3] = 0x00000000U */
  3126. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3127. /* .. L3_SEL = 0 */
  3128. /* .. ==> 0XF8000798[7:5] = 0x00000000U */
  3129. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3130. /* .. Speed = 1 */
  3131. /* .. ==> 0XF8000798[8:8] = 0x00000001U */
  3132. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3133. /* .. IO_Type = 1 */
  3134. /* .. ==> 0XF8000798[11:9] = 0x00000001U */
  3135. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3136. /* .. PULLUP = 0 */
  3137. /* .. ==> 0XF8000798[12:12] = 0x00000000U */
  3138. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3139. /* .. DisableRcvr = 0 */
  3140. /* .. ==> 0XF8000798[13:13] = 0x00000000U */
  3141. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3142. /* .. */
  3143. EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
  3144. /* .. TRI_ENABLE = 0 */
  3145. /* .. ==> 0XF800079C[0:0] = 0x00000000U */
  3146. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3147. /* .. L0_SEL = 0 */
  3148. /* .. ==> 0XF800079C[1:1] = 0x00000000U */
  3149. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3150. /* .. L1_SEL = 1 */
  3151. /* .. ==> 0XF800079C[2:2] = 0x00000001U */
  3152. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  3153. /* .. L2_SEL = 0 */
  3154. /* .. ==> 0XF800079C[4:3] = 0x00000000U */
  3155. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3156. /* .. L3_SEL = 0 */
  3157. /* .. ==> 0XF800079C[7:5] = 0x00000000U */
  3158. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3159. /* .. Speed = 1 */
  3160. /* .. ==> 0XF800079C[8:8] = 0x00000001U */
  3161. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3162. /* .. IO_Type = 1 */
  3163. /* .. ==> 0XF800079C[11:9] = 0x00000001U */
  3164. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3165. /* .. PULLUP = 0 */
  3166. /* .. ==> 0XF800079C[12:12] = 0x00000000U */
  3167. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3168. /* .. DisableRcvr = 0 */
  3169. /* .. ==> 0XF800079C[13:13] = 0x00000000U */
  3170. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3171. /* .. */
  3172. EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
  3173. /* .. TRI_ENABLE = 0 */
  3174. /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
  3175. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3176. /* .. L0_SEL = 0 */
  3177. /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
  3178. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3179. /* .. L1_SEL = 0 */
  3180. /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
  3181. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3182. /* .. L2_SEL = 0 */
  3183. /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
  3184. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3185. /* .. L3_SEL = 4 */
  3186. /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
  3187. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3188. /* .. Speed = 1 */
  3189. /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
  3190. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3191. /* .. IO_Type = 1 */
  3192. /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
  3193. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3194. /* .. PULLUP = 0 */
  3195. /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
  3196. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3197. /* .. DisableRcvr = 0 */
  3198. /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
  3199. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3200. /* .. */
  3201. EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
  3202. /* .. TRI_ENABLE = 0 */
  3203. /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
  3204. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3205. /* .. L0_SEL = 0 */
  3206. /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
  3207. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3208. /* .. L1_SEL = 0 */
  3209. /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
  3210. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3211. /* .. L2_SEL = 0 */
  3212. /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
  3213. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3214. /* .. L3_SEL = 4 */
  3215. /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
  3216. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3217. /* .. Speed = 1 */
  3218. /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
  3219. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3220. /* .. IO_Type = 1 */
  3221. /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
  3222. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3223. /* .. PULLUP = 0 */
  3224. /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
  3225. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3226. /* .. DisableRcvr = 0 */
  3227. /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
  3228. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3229. /* .. */
  3230. EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
  3231. /* .. TRI_ENABLE = 0 */
  3232. /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
  3233. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3234. /* .. L0_SEL = 0 */
  3235. /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
  3236. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3237. /* .. L1_SEL = 0 */
  3238. /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
  3239. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3240. /* .. L2_SEL = 0 */
  3241. /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
  3242. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3243. /* .. L3_SEL = 4 */
  3244. /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
  3245. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3246. /* .. Speed = 1 */
  3247. /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
  3248. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3249. /* .. IO_Type = 1 */
  3250. /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
  3251. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3252. /* .. PULLUP = 0 */
  3253. /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
  3254. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3255. /* .. DisableRcvr = 0 */
  3256. /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
  3257. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3258. /* .. */
  3259. EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
  3260. /* .. TRI_ENABLE = 0 */
  3261. /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
  3262. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3263. /* .. L0_SEL = 0 */
  3264. /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
  3265. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3266. /* .. L1_SEL = 0 */
  3267. /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
  3268. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3269. /* .. L2_SEL = 0 */
  3270. /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
  3271. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3272. /* .. L3_SEL = 4 */
  3273. /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
  3274. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3275. /* .. Speed = 1 */
  3276. /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
  3277. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3278. /* .. IO_Type = 1 */
  3279. /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
  3280. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3281. /* .. PULLUP = 0 */
  3282. /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
  3283. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3284. /* .. DisableRcvr = 0 */
  3285. /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
  3286. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3287. /* .. */
  3288. EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
  3289. /* .. TRI_ENABLE = 0 */
  3290. /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
  3291. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3292. /* .. L0_SEL = 0 */
  3293. /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
  3294. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3295. /* .. L1_SEL = 0 */
  3296. /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
  3297. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3298. /* .. L2_SEL = 0 */
  3299. /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
  3300. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3301. /* .. L3_SEL = 4 */
  3302. /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
  3303. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3304. /* .. Speed = 1 */
  3305. /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
  3306. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3307. /* .. IO_Type = 1 */
  3308. /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
  3309. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3310. /* .. PULLUP = 0 */
  3311. /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
  3312. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3313. /* .. DisableRcvr = 0 */
  3314. /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
  3315. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3316. /* .. */
  3317. EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
  3318. /* .. TRI_ENABLE = 0 */
  3319. /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
  3320. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3321. /* .. L0_SEL = 0 */
  3322. /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
  3323. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3324. /* .. L1_SEL = 0 */
  3325. /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
  3326. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3327. /* .. L2_SEL = 0 */
  3328. /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
  3329. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3330. /* .. L3_SEL = 4 */
  3331. /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
  3332. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3333. /* .. Speed = 1 */
  3334. /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
  3335. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3336. /* .. IO_Type = 1 */
  3337. /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
  3338. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3339. /* .. PULLUP = 0 */
  3340. /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
  3341. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3342. /* .. DisableRcvr = 0 */
  3343. /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
  3344. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3345. /* .. */
  3346. EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
  3347. /* .. TRI_ENABLE = 0 */
  3348. /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
  3349. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3350. /* .. L0_SEL = 0 */
  3351. /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
  3352. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3353. /* .. L1_SEL = 0 */
  3354. /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
  3355. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3356. /* .. L2_SEL = 0 */
  3357. /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
  3358. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3359. /* .. L3_SEL = 0 */
  3360. /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
  3361. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3362. /* .. Speed = 0 */
  3363. /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
  3364. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3365. /* .. IO_Type = 1 */
  3366. /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
  3367. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3368. /* .. PULLUP = 1 */
  3369. /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
  3370. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  3371. /* .. DisableRcvr = 0 */
  3372. /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
  3373. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3374. /* .. */
  3375. EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
  3376. /* .. TRI_ENABLE = 1 */
  3377. /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
  3378. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  3379. /* .. Speed = 0 */
  3380. /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
  3381. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3382. /* .. IO_Type = 1 */
  3383. /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
  3384. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3385. /* .. PULLUP = 0 */
  3386. /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
  3387. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3388. /* .. DisableRcvr = 0 */
  3389. /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
  3390. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3391. /* .. */
  3392. EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
  3393. /* .. TRI_ENABLE = 0 */
  3394. /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
  3395. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3396. /* .. L0_SEL = 0 */
  3397. /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
  3398. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3399. /* .. L1_SEL = 0 */
  3400. /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
  3401. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3402. /* .. L2_SEL = 0 */
  3403. /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
  3404. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3405. /* .. L3_SEL = 7 */
  3406. /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
  3407. /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
  3408. /* .. Speed = 0 */
  3409. /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
  3410. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3411. /* .. IO_Type = 1 */
  3412. /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
  3413. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3414. /* .. PULLUP = 0 */
  3415. /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
  3416. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3417. /* .. DisableRcvr = 0 */
  3418. /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
  3419. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3420. /* .. */
  3421. EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
  3422. /* .. TRI_ENABLE = 1 */
  3423. /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
  3424. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  3425. /* .. L0_SEL = 0 */
  3426. /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
  3427. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3428. /* .. L1_SEL = 0 */
  3429. /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
  3430. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3431. /* .. L2_SEL = 0 */
  3432. /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
  3433. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3434. /* .. L3_SEL = 7 */
  3435. /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
  3436. /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
  3437. /* .. Speed = 0 */
  3438. /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
  3439. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3440. /* .. IO_Type = 1 */
  3441. /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
  3442. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3443. /* .. PULLUP = 0 */
  3444. /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
  3445. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3446. /* .. DisableRcvr = 0 */
  3447. /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
  3448. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3449. /* .. */
  3450. EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
  3451. /* .. TRI_ENABLE = 0 */
  3452. /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
  3453. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3454. /* .. L0_SEL = 0 */
  3455. /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
  3456. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3457. /* .. L1_SEL = 0 */
  3458. /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
  3459. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3460. /* .. L2_SEL = 0 */
  3461. /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
  3462. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3463. /* .. L3_SEL = 0 */
  3464. /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
  3465. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3466. /* .. Speed = 0 */
  3467. /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
  3468. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3469. /* .. IO_Type = 1 */
  3470. /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
  3471. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3472. /* .. PULLUP = 0 */
  3473. /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
  3474. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3475. /* .. DisableRcvr = 0 */
  3476. /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
  3477. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3478. /* .. */
  3479. EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
  3480. /* .. TRI_ENABLE = 0 */
  3481. /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
  3482. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3483. /* .. L0_SEL = 0 */
  3484. /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
  3485. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3486. /* .. L1_SEL = 0 */
  3487. /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
  3488. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3489. /* .. L2_SEL = 0 */
  3490. /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
  3491. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3492. /* .. L3_SEL = 0 */
  3493. /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
  3494. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  3495. /* .. Speed = 0 */
  3496. /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
  3497. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3498. /* .. IO_Type = 1 */
  3499. /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
  3500. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3501. /* .. PULLUP = 0 */
  3502. /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
  3503. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3504. /* .. DisableRcvr = 0 */
  3505. /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
  3506. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3507. /* .. */
  3508. EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
  3509. /* .. TRI_ENABLE = 0 */
  3510. /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
  3511. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3512. /* .. L0_SEL = 0 */
  3513. /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
  3514. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3515. /* .. L1_SEL = 0 */
  3516. /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
  3517. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3518. /* .. L2_SEL = 0 */
  3519. /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
  3520. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3521. /* .. L3_SEL = 4 */
  3522. /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
  3523. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3524. /* .. Speed = 0 */
  3525. /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
  3526. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3527. /* .. IO_Type = 1 */
  3528. /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
  3529. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3530. /* .. PULLUP = 0 */
  3531. /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
  3532. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3533. /* .. DisableRcvr = 0 */
  3534. /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
  3535. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3536. /* .. */
  3537. EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
  3538. /* .. TRI_ENABLE = 0 */
  3539. /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
  3540. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  3541. /* .. L0_SEL = 0 */
  3542. /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
  3543. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  3544. /* .. L1_SEL = 0 */
  3545. /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
  3546. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  3547. /* .. L2_SEL = 0 */
  3548. /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
  3549. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  3550. /* .. L3_SEL = 4 */
  3551. /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
  3552. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  3553. /* .. Speed = 0 */
  3554. /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
  3555. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  3556. /* .. IO_Type = 1 */
  3557. /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
  3558. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  3559. /* .. PULLUP = 0 */
  3560. /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
  3561. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  3562. /* .. DisableRcvr = 0 */
  3563. /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
  3564. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  3565. /* .. */
  3566. EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
  3567. /* .. SDIO0_WP_SEL = 55 */
  3568. /* .. ==> 0XF8000830[5:0] = 0x00000037U */
  3569. /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
  3570. /* .. SDIO0_CD_SEL = 47 */
  3571. /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
  3572. /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
  3573. /* .. */
  3574. EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
  3575. /* .. FINISH: MIO PROGRAMMING */
  3576. /* .. START: LOCK IT BACK */
  3577. /* .. LOCK_KEY = 0X767B */
  3578. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  3579. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  3580. /* .. */
  3581. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  3582. /* .. FINISH: LOCK IT BACK */
  3583. /* FINISH: top */
  3584. /* */
  3585. EMIT_EXIT(),
  3586. /* */
  3587. };
  3588. unsigned long ps7_peripherals_init_data_3_0[] = {
  3589. /* START: top */
  3590. /* .. START: SLCR SETTINGS */
  3591. /* .. UNLOCK_KEY = 0XDF0D */
  3592. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  3593. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  3594. /* .. */
  3595. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  3596. /* .. FINISH: SLCR SETTINGS */
  3597. /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
  3598. /* .. IBUF_DISABLE_MODE = 0x1 */
  3599. /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
  3600. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  3601. /* .. TERM_DISABLE_MODE = 0x1 */
  3602. /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
  3603. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3604. /* .. */
  3605. EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
  3606. /* .. IBUF_DISABLE_MODE = 0x1 */
  3607. /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
  3608. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  3609. /* .. TERM_DISABLE_MODE = 0x1 */
  3610. /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
  3611. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3612. /* .. */
  3613. EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
  3614. /* .. IBUF_DISABLE_MODE = 0x1 */
  3615. /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
  3616. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  3617. /* .. TERM_DISABLE_MODE = 0x1 */
  3618. /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
  3619. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3620. /* .. */
  3621. EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
  3622. /* .. IBUF_DISABLE_MODE = 0x1 */
  3623. /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
  3624. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  3625. /* .. TERM_DISABLE_MODE = 0x1 */
  3626. /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
  3627. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  3628. /* .. */
  3629. EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
  3630. /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
  3631. /* .. START: LOCK IT BACK */
  3632. /* .. LOCK_KEY = 0X767B */
  3633. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  3634. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  3635. /* .. */
  3636. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  3637. /* .. FINISH: LOCK IT BACK */
  3638. /* .. START: SRAM/NOR SET OPMODE */
  3639. /* .. FINISH: SRAM/NOR SET OPMODE */
  3640. /* .. START: QSPI REGISTERS */
  3641. /* .. Holdb_dr = 1 */
  3642. /* .. ==> 0XE000D000[19:19] = 0x00000001U */
  3643. /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  3644. /* .. */
  3645. EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
  3646. /* .. FINISH: QSPI REGISTERS */
  3647. /* .. START: PL POWER ON RESET REGISTERS */
  3648. /* .. PCFG_POR_CNT_4K = 0 */
  3649. /* .. ==> 0XF8007000[29:29] = 0x00000000U */
  3650. /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
  3651. /* .. */
  3652. EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
  3653. /* .. FINISH: PL POWER ON RESET REGISTERS */
  3654. /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
  3655. /* .. .. START: NAND SET CYCLE */
  3656. /* .. .. FINISH: NAND SET CYCLE */
  3657. /* .. .. START: OPMODE */
  3658. /* .. .. FINISH: OPMODE */
  3659. /* .. .. START: DIRECT COMMAND */
  3660. /* .. .. FINISH: DIRECT COMMAND */
  3661. /* .. .. START: SRAM/NOR CS0 SET CYCLE */
  3662. /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
  3663. /* .. .. START: DIRECT COMMAND */
  3664. /* .. .. FINISH: DIRECT COMMAND */
  3665. /* .. .. START: NOR CS0 BASE ADDRESS */
  3666. /* .. .. FINISH: NOR CS0 BASE ADDRESS */
  3667. /* .. .. START: SRAM/NOR CS1 SET CYCLE */
  3668. /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
  3669. /* .. .. START: DIRECT COMMAND */
  3670. /* .. .. FINISH: DIRECT COMMAND */
  3671. /* .. .. START: NOR CS1 BASE ADDRESS */
  3672. /* .. .. FINISH: NOR CS1 BASE ADDRESS */
  3673. /* .. .. START: USB RESET */
  3674. /* .. .. .. START: USB0 RESET */
  3675. /* .. .. .. .. START: DIR MODE BANK 0 */
  3676. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  3677. /* .. .. .. .. START: DIR MODE BANK 1 */
  3678. /* .. .. .. .. DIRECTION_1 = 0x4000 */
  3679. /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
  3680. /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
  3681. /* .. .. .. .. */
  3682. EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
  3683. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  3684. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3685. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3686. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3687. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3688. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3689. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  3690. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  3691. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  3692. /* .. .. .. .. DATA_1_LSW = 0x4000 */
  3693. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
  3694. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
  3695. /* .. .. .. .. */
  3696. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
  3697. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3698. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3699. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3700. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  3701. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  3702. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  3703. /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
  3704. /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
  3705. /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
  3706. /* .. .. .. .. */
  3707. EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
  3708. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  3709. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  3710. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  3711. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  3712. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  3713. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  3714. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  3715. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  3716. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  3717. /* .. .. .. .. DATA_1_LSW = 0x0 */
  3718. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
  3719. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
  3720. /* .. .. .. .. */
  3721. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
  3722. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  3723. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  3724. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  3725. /* .. .. .. .. START: ADD 1 MS DELAY */
  3726. /* .. .. .. .. */
  3727. EMIT_MASKDELAY(0XF8F00200, 1),
  3728. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  3729. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3730. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3731. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3732. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3733. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3734. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  3735. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  3736. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  3737. /* .. .. .. .. DATA_1_LSW = 0x4000 */
  3738. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
  3739. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
  3740. /* .. .. .. .. */
  3741. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
  3742. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3743. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3744. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3745. /* .. .. .. FINISH: USB0 RESET */
  3746. /* .. .. .. START: USB1 RESET */
  3747. /* .. .. .. .. START: DIR MODE BANK 0 */
  3748. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  3749. /* .. .. .. .. START: DIR MODE BANK 1 */
  3750. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  3751. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3752. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3753. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3754. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3755. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3756. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3757. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3758. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3759. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  3760. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  3761. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  3762. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  3763. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  3764. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  3765. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  3766. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  3767. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  3768. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  3769. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  3770. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  3771. /* .. .. .. .. START: ADD 1 MS DELAY */
  3772. /* .. .. .. .. */
  3773. EMIT_MASKDELAY(0XF8F00200, 1),
  3774. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  3775. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3776. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3777. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3778. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3779. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3780. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3781. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3782. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3783. /* .. .. .. FINISH: USB1 RESET */
  3784. /* .. .. FINISH: USB RESET */
  3785. /* .. .. START: ENET RESET */
  3786. /* .. .. .. START: ENET0 RESET */
  3787. /* .. .. .. .. START: DIR MODE BANK 0 */
  3788. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  3789. /* .. .. .. .. START: DIR MODE BANK 1 */
  3790. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  3791. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3792. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3793. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3794. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3795. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3796. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3797. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3798. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3799. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  3800. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  3801. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  3802. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  3803. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  3804. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  3805. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  3806. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  3807. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  3808. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  3809. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  3810. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  3811. /* .. .. .. .. START: ADD 1 MS DELAY */
  3812. /* .. .. .. .. */
  3813. EMIT_MASKDELAY(0XF8F00200, 1),
  3814. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  3815. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3816. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3817. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3818. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3819. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3820. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3821. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3822. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3823. /* .. .. .. FINISH: ENET0 RESET */
  3824. /* .. .. .. START: ENET1 RESET */
  3825. /* .. .. .. .. START: DIR MODE BANK 0 */
  3826. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  3827. /* .. .. .. .. START: DIR MODE BANK 1 */
  3828. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  3829. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3830. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3831. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3832. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3833. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3834. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3835. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3836. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3837. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  3838. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  3839. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  3840. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  3841. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  3842. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  3843. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  3844. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  3845. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  3846. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  3847. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  3848. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  3849. /* .. .. .. .. START: ADD 1 MS DELAY */
  3850. /* .. .. .. .. */
  3851. EMIT_MASKDELAY(0XF8F00200, 1),
  3852. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  3853. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3854. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3855. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3856. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3857. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3858. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3859. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3860. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3861. /* .. .. .. FINISH: ENET1 RESET */
  3862. /* .. .. FINISH: ENET RESET */
  3863. /* .. .. START: I2C RESET */
  3864. /* .. .. .. START: I2C0 RESET */
  3865. /* .. .. .. .. START: DIR MODE GPIO BANK0 */
  3866. /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
  3867. /* .. .. .. .. START: DIR MODE GPIO BANK1 */
  3868. /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
  3869. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3870. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3871. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3872. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3873. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3874. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3875. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3876. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3877. /* .. .. .. .. START: OUTPUT ENABLE */
  3878. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  3879. /* .. .. .. .. START: OUTPUT ENABLE */
  3880. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  3881. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  3882. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  3883. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  3884. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  3885. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  3886. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  3887. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  3888. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  3889. /* .. .. .. .. START: ADD 1 MS DELAY */
  3890. /* .. .. .. .. */
  3891. EMIT_MASKDELAY(0XF8F00200, 1),
  3892. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  3893. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3894. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3895. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3896. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3897. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3898. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3899. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3900. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3901. /* .. .. .. FINISH: I2C0 RESET */
  3902. /* .. .. .. START: I2C1 RESET */
  3903. /* .. .. .. .. START: DIR MODE GPIO BANK0 */
  3904. /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
  3905. /* .. .. .. .. START: DIR MODE GPIO BANK1 */
  3906. /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
  3907. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3908. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3909. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3910. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3911. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3912. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3913. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3914. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3915. /* .. .. .. .. START: OUTPUT ENABLE */
  3916. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  3917. /* .. .. .. .. START: OUTPUT ENABLE */
  3918. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  3919. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  3920. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  3921. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  3922. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  3923. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  3924. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  3925. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  3926. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  3927. /* .. .. .. .. START: ADD 1 MS DELAY */
  3928. /* .. .. .. .. */
  3929. EMIT_MASKDELAY(0XF8F00200, 1),
  3930. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  3931. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3932. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3933. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3934. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  3935. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3936. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  3937. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3938. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  3939. /* .. .. .. FINISH: I2C1 RESET */
  3940. /* .. .. FINISH: I2C RESET */
  3941. /* .. .. START: NOR CHIP SELECT */
  3942. /* .. .. .. START: DIR MODE BANK 0 */
  3943. /* .. .. .. FINISH: DIR MODE BANK 0 */
  3944. /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3945. /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  3946. /* .. .. .. START: OUTPUT ENABLE BANK 0 */
  3947. /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  3948. /* .. .. FINISH: NOR CHIP SELECT */
  3949. /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
  3950. /* FINISH: top */
  3951. /* */
  3952. EMIT_EXIT(),
  3953. /* */
  3954. };
  3955. unsigned long ps7_post_config_3_0[] = {
  3956. /* START: top */
  3957. /* .. START: SLCR SETTINGS */
  3958. /* .. UNLOCK_KEY = 0XDF0D */
  3959. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  3960. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  3961. /* .. */
  3962. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  3963. /* .. FINISH: SLCR SETTINGS */
  3964. /* .. START: ENABLING LEVEL SHIFTER */
  3965. /* .. USER_LVL_INP_EN_0 = 1 */
  3966. /* .. ==> 0XF8000900[3:3] = 0x00000001U */
  3967. /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */
  3968. /* .. USER_LVL_OUT_EN_0 = 1 */
  3969. /* .. ==> 0XF8000900[2:2] = 0x00000001U */
  3970. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  3971. /* .. USER_LVL_INP_EN_1 = 1 */
  3972. /* .. ==> 0XF8000900[1:1] = 0x00000001U */
  3973. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  3974. /* .. USER_LVL_OUT_EN_1 = 1 */
  3975. /* .. ==> 0XF8000900[0:0] = 0x00000001U */
  3976. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  3977. /* .. */
  3978. EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
  3979. /* .. FINISH: ENABLING LEVEL SHIFTER */
  3980. /* .. START: FPGA RESETS TO 0 */
  3981. /* .. reserved_3 = 0 */
  3982. /* .. ==> 0XF8000240[31:25] = 0x00000000U */
  3983. /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
  3984. /* .. reserved_FPGA_ACP_RST = 0 */
  3985. /* .. ==> 0XF8000240[24:24] = 0x00000000U */
  3986. /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  3987. /* .. reserved_FPGA_AXDS3_RST = 0 */
  3988. /* .. ==> 0XF8000240[23:23] = 0x00000000U */
  3989. /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  3990. /* .. reserved_FPGA_AXDS2_RST = 0 */
  3991. /* .. ==> 0XF8000240[22:22] = 0x00000000U */
  3992. /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  3993. /* .. reserved_FPGA_AXDS1_RST = 0 */
  3994. /* .. ==> 0XF8000240[21:21] = 0x00000000U */
  3995. /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  3996. /* .. reserved_FPGA_AXDS0_RST = 0 */
  3997. /* .. ==> 0XF8000240[20:20] = 0x00000000U */
  3998. /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  3999. /* .. reserved_2 = 0 */
  4000. /* .. ==> 0XF8000240[19:18] = 0x00000000U */
  4001. /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
  4002. /* .. reserved_FSSW1_FPGA_RST = 0 */
  4003. /* .. ==> 0XF8000240[17:17] = 0x00000000U */
  4004. /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  4005. /* .. reserved_FSSW0_FPGA_RST = 0 */
  4006. /* .. ==> 0XF8000240[16:16] = 0x00000000U */
  4007. /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  4008. /* .. reserved_1 = 0 */
  4009. /* .. ==> 0XF8000240[15:14] = 0x00000000U */
  4010. /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
  4011. /* .. reserved_FPGA_FMSW1_RST = 0 */
  4012. /* .. ==> 0XF8000240[13:13] = 0x00000000U */
  4013. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  4014. /* .. reserved_FPGA_FMSW0_RST = 0 */
  4015. /* .. ==> 0XF8000240[12:12] = 0x00000000U */
  4016. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  4017. /* .. reserved_FPGA_DMA3_RST = 0 */
  4018. /* .. ==> 0XF8000240[11:11] = 0x00000000U */
  4019. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  4020. /* .. reserved_FPGA_DMA2_RST = 0 */
  4021. /* .. ==> 0XF8000240[10:10] = 0x00000000U */
  4022. /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  4023. /* .. reserved_FPGA_DMA1_RST = 0 */
  4024. /* .. ==> 0XF8000240[9:9] = 0x00000000U */
  4025. /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  4026. /* .. reserved_FPGA_DMA0_RST = 0 */
  4027. /* .. ==> 0XF8000240[8:8] = 0x00000000U */
  4028. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  4029. /* .. reserved = 0 */
  4030. /* .. ==> 0XF8000240[7:4] = 0x00000000U */
  4031. /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  4032. /* .. FPGA3_OUT_RST = 0 */
  4033. /* .. ==> 0XF8000240[3:3] = 0x00000000U */
  4034. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  4035. /* .. FPGA2_OUT_RST = 0 */
  4036. /* .. ==> 0XF8000240[2:2] = 0x00000000U */
  4037. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  4038. /* .. FPGA1_OUT_RST = 0 */
  4039. /* .. ==> 0XF8000240[1:1] = 0x00000000U */
  4040. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  4041. /* .. FPGA0_OUT_RST = 0 */
  4042. /* .. ==> 0XF8000240[0:0] = 0x00000000U */
  4043. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4044. /* .. */
  4045. EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
  4046. /* .. FINISH: FPGA RESETS TO 0 */
  4047. /* .. START: AFI REGISTERS */
  4048. /* .. .. START: AFI0 REGISTERS */
  4049. /* .. .. FINISH: AFI0 REGISTERS */
  4050. /* .. .. START: AFI1 REGISTERS */
  4051. /* .. .. FINISH: AFI1 REGISTERS */
  4052. /* .. .. START: AFI2 REGISTERS */
  4053. /* .. .. FINISH: AFI2 REGISTERS */
  4054. /* .. .. START: AFI3 REGISTERS */
  4055. /* .. .. FINISH: AFI3 REGISTERS */
  4056. /* .. .. START: AFI2 SECURE REGISTER */
  4057. /* .. .. FINISH: AFI2 SECURE REGISTER */
  4058. /* .. FINISH: AFI REGISTERS */
  4059. /* .. START: LOCK IT BACK */
  4060. /* .. LOCK_KEY = 0X767B */
  4061. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  4062. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  4063. /* .. */
  4064. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  4065. /* .. FINISH: LOCK IT BACK */
  4066. /* FINISH: top */
  4067. /* */
  4068. EMIT_EXIT(),
  4069. /* */
  4070. };
  4071. unsigned long ps7_pll_init_data_2_0[] = {
  4072. /* START: top */
  4073. /* .. START: SLCR SETTINGS */
  4074. /* .. UNLOCK_KEY = 0XDF0D */
  4075. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  4076. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  4077. /* .. */
  4078. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  4079. /* .. FINISH: SLCR SETTINGS */
  4080. /* .. START: PLL SLCR REGISTERS */
  4081. /* .. .. START: ARM PLL INIT */
  4082. /* .. .. PLL_RES = 0xc */
  4083. /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
  4084. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  4085. /* .. .. PLL_CP = 0x2 */
  4086. /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
  4087. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  4088. /* .. .. LOCK_CNT = 0x177 */
  4089. /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
  4090. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
  4091. /* .. .. */
  4092. EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
  4093. /* .. .. .. START: UPDATE FB_DIV */
  4094. /* .. .. .. PLL_FDIV = 0x1a */
  4095. /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
  4096. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
  4097. /* .. .. .. */
  4098. EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
  4099. /* .. .. .. FINISH: UPDATE FB_DIV */
  4100. /* .. .. .. START: BY PASS PLL */
  4101. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  4102. /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
  4103. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  4104. /* .. .. .. */
  4105. EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
  4106. /* .. .. .. FINISH: BY PASS PLL */
  4107. /* .. .. .. START: ASSERT RESET */
  4108. /* .. .. .. PLL_RESET = 1 */
  4109. /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
  4110. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4111. /* .. .. .. */
  4112. EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
  4113. /* .. .. .. FINISH: ASSERT RESET */
  4114. /* .. .. .. START: DEASSERT RESET */
  4115. /* .. .. .. PLL_RESET = 0 */
  4116. /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
  4117. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4118. /* .. .. .. */
  4119. EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
  4120. /* .. .. .. FINISH: DEASSERT RESET */
  4121. /* .. .. .. START: CHECK PLL STATUS */
  4122. /* .. .. .. ARM_PLL_LOCK = 1 */
  4123. /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
  4124. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4125. /* .. .. .. */
  4126. EMIT_MASKPOLL(0XF800010C, 0x00000001U),
  4127. /* .. .. .. FINISH: CHECK PLL STATUS */
  4128. /* .. .. .. START: REMOVE PLL BY PASS */
  4129. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  4130. /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
  4131. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  4132. /* .. .. .. */
  4133. EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
  4134. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  4135. /* .. .. .. SRCSEL = 0x0 */
  4136. /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
  4137. /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4138. /* .. .. .. DIVISOR = 0x2 */
  4139. /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
  4140. /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
  4141. /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
  4142. /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
  4143. /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
  4144. /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
  4145. /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
  4146. /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
  4147. /* .. .. .. CPU_2XCLKACT = 0x1 */
  4148. /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
  4149. /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
  4150. /* .. .. .. CPU_1XCLKACT = 0x1 */
  4151. /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
  4152. /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
  4153. /* .. .. .. CPU_PERI_CLKACT = 0x1 */
  4154. /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
  4155. /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  4156. /* .. .. .. */
  4157. EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
  4158. /* .. .. FINISH: ARM PLL INIT */
  4159. /* .. .. START: DDR PLL INIT */
  4160. /* .. .. PLL_RES = 0xc */
  4161. /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
  4162. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  4163. /* .. .. PLL_CP = 0x2 */
  4164. /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
  4165. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  4166. /* .. .. LOCK_CNT = 0x1db */
  4167. /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
  4168. /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
  4169. /* .. .. */
  4170. EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
  4171. /* .. .. .. START: UPDATE FB_DIV */
  4172. /* .. .. .. PLL_FDIV = 0x15 */
  4173. /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
  4174. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
  4175. /* .. .. .. */
  4176. EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
  4177. /* .. .. .. FINISH: UPDATE FB_DIV */
  4178. /* .. .. .. START: BY PASS PLL */
  4179. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  4180. /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
  4181. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  4182. /* .. .. .. */
  4183. EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
  4184. /* .. .. .. FINISH: BY PASS PLL */
  4185. /* .. .. .. START: ASSERT RESET */
  4186. /* .. .. .. PLL_RESET = 1 */
  4187. /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
  4188. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4189. /* .. .. .. */
  4190. EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
  4191. /* .. .. .. FINISH: ASSERT RESET */
  4192. /* .. .. .. START: DEASSERT RESET */
  4193. /* .. .. .. PLL_RESET = 0 */
  4194. /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
  4195. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4196. /* .. .. .. */
  4197. EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
  4198. /* .. .. .. FINISH: DEASSERT RESET */
  4199. /* .. .. .. START: CHECK PLL STATUS */
  4200. /* .. .. .. DDR_PLL_LOCK = 1 */
  4201. /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
  4202. /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  4203. /* .. .. .. */
  4204. EMIT_MASKPOLL(0XF800010C, 0x00000002U),
  4205. /* .. .. .. FINISH: CHECK PLL STATUS */
  4206. /* .. .. .. START: REMOVE PLL BY PASS */
  4207. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  4208. /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
  4209. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  4210. /* .. .. .. */
  4211. EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
  4212. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  4213. /* .. .. .. DDR_3XCLKACT = 0x1 */
  4214. /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
  4215. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4216. /* .. .. .. DDR_2XCLKACT = 0x1 */
  4217. /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
  4218. /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  4219. /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
  4220. /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
  4221. /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
  4222. /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
  4223. /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
  4224. /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
  4225. /* .. .. .. */
  4226. EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
  4227. /* .. .. FINISH: DDR PLL INIT */
  4228. /* .. .. START: IO PLL INIT */
  4229. /* .. .. PLL_RES = 0xc */
  4230. /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
  4231. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  4232. /* .. .. PLL_CP = 0x2 */
  4233. /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
  4234. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  4235. /* .. .. LOCK_CNT = 0x1f4 */
  4236. /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
  4237. /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
  4238. /* .. .. */
  4239. EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
  4240. /* .. .. .. START: UPDATE FB_DIV */
  4241. /* .. .. .. PLL_FDIV = 0x14 */
  4242. /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
  4243. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
  4244. /* .. .. .. */
  4245. EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
  4246. /* .. .. .. FINISH: UPDATE FB_DIV */
  4247. /* .. .. .. START: BY PASS PLL */
  4248. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  4249. /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
  4250. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  4251. /* .. .. .. */
  4252. EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
  4253. /* .. .. .. FINISH: BY PASS PLL */
  4254. /* .. .. .. START: ASSERT RESET */
  4255. /* .. .. .. PLL_RESET = 1 */
  4256. /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
  4257. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4258. /* .. .. .. */
  4259. EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
  4260. /* .. .. .. FINISH: ASSERT RESET */
  4261. /* .. .. .. START: DEASSERT RESET */
  4262. /* .. .. .. PLL_RESET = 0 */
  4263. /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
  4264. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4265. /* .. .. .. */
  4266. EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
  4267. /* .. .. .. FINISH: DEASSERT RESET */
  4268. /* .. .. .. START: CHECK PLL STATUS */
  4269. /* .. .. .. IO_PLL_LOCK = 1 */
  4270. /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
  4271. /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  4272. /* .. .. .. */
  4273. EMIT_MASKPOLL(0XF800010C, 0x00000004U),
  4274. /* .. .. .. FINISH: CHECK PLL STATUS */
  4275. /* .. .. .. START: REMOVE PLL BY PASS */
  4276. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  4277. /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
  4278. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  4279. /* .. .. .. */
  4280. EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
  4281. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  4282. /* .. .. FINISH: IO PLL INIT */
  4283. /* .. FINISH: PLL SLCR REGISTERS */
  4284. /* .. START: LOCK IT BACK */
  4285. /* .. LOCK_KEY = 0X767B */
  4286. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  4287. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  4288. /* .. */
  4289. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  4290. /* .. FINISH: LOCK IT BACK */
  4291. /* FINISH: top */
  4292. /* */
  4293. EMIT_EXIT(),
  4294. /* */
  4295. };
  4296. unsigned long ps7_clock_init_data_2_0[] = {
  4297. /* START: top */
  4298. /* .. START: SLCR SETTINGS */
  4299. /* .. UNLOCK_KEY = 0XDF0D */
  4300. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  4301. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  4302. /* .. */
  4303. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  4304. /* .. FINISH: SLCR SETTINGS */
  4305. /* .. START: CLOCK CONTROL SLCR REGISTERS */
  4306. /* .. CLKACT = 0x1 */
  4307. /* .. ==> 0XF8000128[0:0] = 0x00000001U */
  4308. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4309. /* .. DIVISOR0 = 0x34 */
  4310. /* .. ==> 0XF8000128[13:8] = 0x00000034U */
  4311. /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
  4312. /* .. DIVISOR1 = 0x2 */
  4313. /* .. ==> 0XF8000128[25:20] = 0x00000002U */
  4314. /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
  4315. /* .. */
  4316. EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
  4317. /* .. CLKACT = 0x1 */
  4318. /* .. ==> 0XF8000138[0:0] = 0x00000001U */
  4319. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4320. /* .. SRCSEL = 0x0 */
  4321. /* .. ==> 0XF8000138[4:4] = 0x00000000U */
  4322. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  4323. /* .. */
  4324. EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
  4325. /* .. CLKACT = 0x1 */
  4326. /* .. ==> 0XF8000140[0:0] = 0x00000001U */
  4327. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4328. /* .. SRCSEL = 0x0 */
  4329. /* .. ==> 0XF8000140[6:4] = 0x00000000U */
  4330. /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  4331. /* .. DIVISOR = 0x8 */
  4332. /* .. ==> 0XF8000140[13:8] = 0x00000008U */
  4333. /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
  4334. /* .. DIVISOR1 = 0x1 */
  4335. /* .. ==> 0XF8000140[25:20] = 0x00000001U */
  4336. /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  4337. /* .. */
  4338. EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
  4339. /* .. CLKACT = 0x1 */
  4340. /* .. ==> 0XF800014C[0:0] = 0x00000001U */
  4341. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4342. /* .. SRCSEL = 0x0 */
  4343. /* .. ==> 0XF800014C[5:4] = 0x00000000U */
  4344. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4345. /* .. DIVISOR = 0x5 */
  4346. /* .. ==> 0XF800014C[13:8] = 0x00000005U */
  4347. /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  4348. /* .. */
  4349. EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
  4350. /* .. CLKACT0 = 0x1 */
  4351. /* .. ==> 0XF8000150[0:0] = 0x00000001U */
  4352. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4353. /* .. CLKACT1 = 0x0 */
  4354. /* .. ==> 0XF8000150[1:1] = 0x00000000U */
  4355. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  4356. /* .. SRCSEL = 0x0 */
  4357. /* .. ==> 0XF8000150[5:4] = 0x00000000U */
  4358. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4359. /* .. DIVISOR = 0x14 */
  4360. /* .. ==> 0XF8000150[13:8] = 0x00000014U */
  4361. /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
  4362. /* .. */
  4363. EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
  4364. /* .. CLKACT0 = 0x0 */
  4365. /* .. ==> 0XF8000154[0:0] = 0x00000000U */
  4366. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4367. /* .. CLKACT1 = 0x1 */
  4368. /* .. ==> 0XF8000154[1:1] = 0x00000001U */
  4369. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  4370. /* .. SRCSEL = 0x0 */
  4371. /* .. ==> 0XF8000154[5:4] = 0x00000000U */
  4372. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4373. /* .. DIVISOR = 0xa */
  4374. /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
  4375. /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
  4376. /* .. */
  4377. EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
  4378. /* .. .. START: TRACE CLOCK */
  4379. /* .. .. FINISH: TRACE CLOCK */
  4380. /* .. .. CLKACT = 0x1 */
  4381. /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
  4382. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4383. /* .. .. SRCSEL = 0x0 */
  4384. /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
  4385. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4386. /* .. .. DIVISOR = 0x5 */
  4387. /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
  4388. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  4389. /* .. .. */
  4390. EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
  4391. /* .. .. SRCSEL = 0x0 */
  4392. /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
  4393. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4394. /* .. .. DIVISOR0 = 0xa */
  4395. /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
  4396. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
  4397. /* .. .. DIVISOR1 = 0x1 */
  4398. /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
  4399. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  4400. /* .. .. */
  4401. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
  4402. /* .. .. SRCSEL = 0x0 */
  4403. /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
  4404. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4405. /* .. .. DIVISOR0 = 0x7 */
  4406. /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
  4407. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
  4408. /* .. .. DIVISOR1 = 0x1 */
  4409. /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
  4410. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  4411. /* .. .. */
  4412. EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
  4413. /* .. .. SRCSEL = 0x0 */
  4414. /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
  4415. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4416. /* .. .. DIVISOR0 = 0x5 */
  4417. /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
  4418. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  4419. /* .. .. DIVISOR1 = 0x1 */
  4420. /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
  4421. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  4422. /* .. .. */
  4423. EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
  4424. /* .. .. SRCSEL = 0x0 */
  4425. /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
  4426. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  4427. /* .. .. DIVISOR0 = 0x14 */
  4428. /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
  4429. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
  4430. /* .. .. DIVISOR1 = 0x1 */
  4431. /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
  4432. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  4433. /* .. .. */
  4434. EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
  4435. /* .. .. CLK_621_TRUE = 0x1 */
  4436. /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
  4437. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4438. /* .. .. */
  4439. EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
  4440. /* .. .. DMA_CPU_2XCLKACT = 0x1 */
  4441. /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
  4442. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  4443. /* .. .. USB0_CPU_1XCLKACT = 0x1 */
  4444. /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
  4445. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  4446. /* .. .. USB1_CPU_1XCLKACT = 0x1 */
  4447. /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
  4448. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
  4449. /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
  4450. /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
  4451. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
  4452. /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
  4453. /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
  4454. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  4455. /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
  4456. /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
  4457. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
  4458. /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
  4459. /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
  4460. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  4461. /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
  4462. /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
  4463. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  4464. /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
  4465. /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
  4466. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  4467. /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
  4468. /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
  4469. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  4470. /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
  4471. /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
  4472. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  4473. /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
  4474. /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
  4475. /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
  4476. /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
  4477. /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
  4478. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  4479. /* .. .. UART0_CPU_1XCLKACT = 0x0 */
  4480. /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
  4481. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  4482. /* .. .. UART1_CPU_1XCLKACT = 0x1 */
  4483. /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
  4484. /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
  4485. /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
  4486. /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
  4487. /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
  4488. /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
  4489. /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
  4490. /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
  4491. /* .. .. SMC_CPU_1XCLKACT = 0x1 */
  4492. /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
  4493. /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
  4494. /* .. .. */
  4495. EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
  4496. /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
  4497. /* .. START: THIS SHOULD BE BLANK */
  4498. /* .. FINISH: THIS SHOULD BE BLANK */
  4499. /* .. START: LOCK IT BACK */
  4500. /* .. LOCK_KEY = 0X767B */
  4501. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  4502. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  4503. /* .. */
  4504. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  4505. /* .. FINISH: LOCK IT BACK */
  4506. /* FINISH: top */
  4507. /* */
  4508. EMIT_EXIT(),
  4509. /* */
  4510. };
  4511. unsigned long ps7_ddr_init_data_2_0[] = {
  4512. /* START: top */
  4513. /* .. START: DDR INITIALIZATION */
  4514. /* .. .. START: LOCK DDR */
  4515. /* .. .. reg_ddrc_soft_rstb = 0 */
  4516. /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
  4517. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4518. /* .. .. reg_ddrc_powerdown_en = 0x0 */
  4519. /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
  4520. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  4521. /* .. .. reg_ddrc_data_bus_width = 0x0 */
  4522. /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
  4523. /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
  4524. /* .. .. reg_ddrc_burst8_refresh = 0x0 */
  4525. /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
  4526. /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  4527. /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
  4528. /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
  4529. /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
  4530. /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
  4531. /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
  4532. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  4533. /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
  4534. /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
  4535. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  4536. /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
  4537. /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
  4538. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  4539. /* .. .. */
  4540. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
  4541. /* .. .. FINISH: LOCK DDR */
  4542. /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
  4543. /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
  4544. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
  4545. /* .. .. reg_ddrc_active_ranks = 0x1 */
  4546. /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
  4547. /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
  4548. /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
  4549. /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
  4550. /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
  4551. /* .. .. reg_ddrc_wr_odt_block = 0x1 */
  4552. /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
  4553. /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
  4554. /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
  4555. /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
  4556. /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  4557. /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
  4558. /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
  4559. /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
  4560. /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
  4561. /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
  4562. /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
  4563. /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
  4564. /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
  4565. /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
  4566. /* .. .. */
  4567. EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
  4568. /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
  4569. /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
  4570. /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
  4571. /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
  4572. /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
  4573. /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
  4574. /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
  4575. /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
  4576. /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
  4577. /* .. .. */
  4578. EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
  4579. /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
  4580. /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
  4581. /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
  4582. /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
  4583. /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
  4584. /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
  4585. /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
  4586. /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
  4587. /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
  4588. /* .. .. */
  4589. EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
  4590. /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
  4591. /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
  4592. /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
  4593. /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
  4594. /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
  4595. /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
  4596. /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
  4597. /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
  4598. /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
  4599. /* .. .. */
  4600. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
  4601. /* .. .. reg_ddrc_t_rc = 0x1a */
  4602. /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
  4603. /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
  4604. /* .. .. reg_ddrc_t_rfc_min = 0x54 */
  4605. /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
  4606. /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
  4607. /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
  4608. /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
  4609. /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
  4610. /* .. .. */
  4611. EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
  4612. /* .. .. reg_ddrc_wr2pre = 0x12 */
  4613. /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
  4614. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
  4615. /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
  4616. /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
  4617. /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
  4618. /* .. .. reg_ddrc_t_faw = 0x15 */
  4619. /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
  4620. /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
  4621. /* .. .. reg_ddrc_t_ras_max = 0x23 */
  4622. /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
  4623. /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
  4624. /* .. .. reg_ddrc_t_ras_min = 0x13 */
  4625. /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
  4626. /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
  4627. /* .. .. reg_ddrc_t_cke = 0x4 */
  4628. /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
  4629. /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
  4630. /* .. .. */
  4631. EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
  4632. /* .. .. reg_ddrc_write_latency = 0x5 */
  4633. /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
  4634. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
  4635. /* .. .. reg_ddrc_rd2wr = 0x7 */
  4636. /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
  4637. /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
  4638. /* .. .. reg_ddrc_wr2rd = 0xe */
  4639. /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
  4640. /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
  4641. /* .. .. reg_ddrc_t_xp = 0x4 */
  4642. /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
  4643. /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
  4644. /* .. .. reg_ddrc_pad_pd = 0x0 */
  4645. /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
  4646. /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
  4647. /* .. .. reg_ddrc_rd2pre = 0x4 */
  4648. /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
  4649. /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
  4650. /* .. .. reg_ddrc_t_rcd = 0x7 */
  4651. /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
  4652. /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
  4653. /* .. .. */
  4654. EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
  4655. /* .. .. reg_ddrc_t_ccd = 0x4 */
  4656. /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
  4657. /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
  4658. /* .. .. reg_ddrc_t_rrd = 0x6 */
  4659. /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
  4660. /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
  4661. /* .. .. reg_ddrc_refresh_margin = 0x2 */
  4662. /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
  4663. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  4664. /* .. .. reg_ddrc_t_rp = 0x7 */
  4665. /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
  4666. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
  4667. /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
  4668. /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
  4669. /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
  4670. /* .. .. reg_ddrc_sdram = 0x1 */
  4671. /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
  4672. /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
  4673. /* .. .. reg_ddrc_mobile = 0x0 */
  4674. /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
  4675. /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  4676. /* .. .. reg_ddrc_clock_stop_en = 0x0 */
  4677. /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
  4678. /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  4679. /* .. .. reg_ddrc_read_latency = 0x7 */
  4680. /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
  4681. /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
  4682. /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
  4683. /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
  4684. /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
  4685. /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
  4686. /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
  4687. /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
  4688. /* .. .. reg_ddrc_loopback = 0x0 */
  4689. /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
  4690. /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
  4691. /* .. .. */
  4692. EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
  4693. /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
  4694. /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
  4695. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4696. /* .. .. reg_ddrc_prefer_write = 0x0 */
  4697. /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
  4698. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  4699. /* .. .. reg_ddrc_max_rank_rd = 0xf */
  4700. /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
  4701. /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
  4702. /* .. .. reg_ddrc_mr_wr = 0x0 */
  4703. /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
  4704. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
  4705. /* .. .. reg_ddrc_mr_addr = 0x0 */
  4706. /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
  4707. /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
  4708. /* .. .. reg_ddrc_mr_data = 0x0 */
  4709. /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
  4710. /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
  4711. /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
  4712. /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
  4713. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  4714. /* .. .. reg_ddrc_mr_type = 0x0 */
  4715. /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
  4716. /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
  4717. /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
  4718. /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
  4719. /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
  4720. /* .. .. */
  4721. EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
  4722. /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
  4723. /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
  4724. /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
  4725. /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
  4726. /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
  4727. /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
  4728. /* .. .. reg_ddrc_t_mrd = 0x4 */
  4729. /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
  4730. /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
  4731. /* .. .. */
  4732. EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
  4733. /* .. .. reg_ddrc_emr2 = 0x8 */
  4734. /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
  4735. /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
  4736. /* .. .. reg_ddrc_emr3 = 0x0 */
  4737. /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
  4738. /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
  4739. /* .. .. */
  4740. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
  4741. /* .. .. reg_ddrc_mr = 0x930 */
  4742. /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
  4743. /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
  4744. /* .. .. reg_ddrc_emr = 0x4 */
  4745. /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
  4746. /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
  4747. /* .. .. */
  4748. EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
  4749. /* .. .. reg_ddrc_burst_rdwr = 0x4 */
  4750. /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
  4751. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
  4752. /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
  4753. /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
  4754. /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
  4755. /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
  4756. /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
  4757. /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
  4758. /* .. .. reg_ddrc_burstchop = 0x0 */
  4759. /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
  4760. /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
  4761. /* .. .. */
  4762. EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
  4763. /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
  4764. /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
  4765. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4766. /* .. .. reg_ddrc_dis_dq = 0x0 */
  4767. /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
  4768. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  4769. /* .. .. reg_phy_debug_mode = 0x0 */
  4770. /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
  4771. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
  4772. /* .. .. reg_phy_wr_level_start = 0x0 */
  4773. /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
  4774. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  4775. /* .. .. reg_phy_rd_level_start = 0x0 */
  4776. /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
  4777. /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  4778. /* .. .. reg_phy_dq0_wait_t = 0x0 */
  4779. /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
  4780. /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
  4781. /* .. .. */
  4782. EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
  4783. /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
  4784. /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
  4785. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
  4786. /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
  4787. /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
  4788. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
  4789. /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
  4790. /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
  4791. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
  4792. /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
  4793. /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
  4794. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
  4795. /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
  4796. /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
  4797. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
  4798. /* .. .. */
  4799. EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
  4800. /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
  4801. /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
  4802. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  4803. /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
  4804. /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
  4805. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  4806. /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
  4807. /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
  4808. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
  4809. /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
  4810. /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
  4811. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
  4812. /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
  4813. /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
  4814. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
  4815. /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
  4816. /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
  4817. /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
  4818. /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
  4819. /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
  4820. /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
  4821. /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
  4822. /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
  4823. /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
  4824. /* .. .. */
  4825. EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
  4826. /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
  4827. /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
  4828. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
  4829. /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
  4830. /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
  4831. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
  4832. /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
  4833. /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
  4834. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
  4835. /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
  4836. /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
  4837. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
  4838. /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
  4839. /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
  4840. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
  4841. /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
  4842. /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
  4843. /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
  4844. /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
  4845. /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
  4846. /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
  4847. /* .. .. */
  4848. EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
  4849. /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
  4850. /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
  4851. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
  4852. /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
  4853. /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
  4854. /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
  4855. /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
  4856. /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
  4857. /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
  4858. /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
  4859. /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
  4860. /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  4861. /* .. .. reg_phy_rd_local_odt = 0x0 */
  4862. /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
  4863. /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
  4864. /* .. .. reg_phy_wr_local_odt = 0x3 */
  4865. /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
  4866. /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
  4867. /* .. .. reg_phy_idle_local_odt = 0x3 */
  4868. /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
  4869. /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
  4870. /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
  4871. /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
  4872. /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
  4873. /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
  4874. /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
  4875. /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
  4876. /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
  4877. /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
  4878. /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  4879. /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
  4880. /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
  4881. /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
  4882. /* .. .. */
  4883. EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
  4884. /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
  4885. /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
  4886. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  4887. /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
  4888. /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
  4889. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  4890. /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
  4891. /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
  4892. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
  4893. /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
  4894. /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
  4895. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  4896. /* .. .. reg_phy_use_fixed_re = 0x1 */
  4897. /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
  4898. /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
  4899. /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
  4900. /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
  4901. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  4902. /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
  4903. /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
  4904. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  4905. /* .. .. reg_phy_clk_stall_level = 0x0 */
  4906. /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
  4907. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  4908. /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
  4909. /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
  4910. /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
  4911. /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
  4912. /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
  4913. /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
  4914. /* .. .. */
  4915. EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
  4916. /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
  4917. /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
  4918. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
  4919. /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
  4920. /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
  4921. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
  4922. /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
  4923. /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
  4924. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  4925. /* .. .. */
  4926. EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
  4927. /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
  4928. /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
  4929. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
  4930. /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
  4931. /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
  4932. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  4933. /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
  4934. /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
  4935. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
  4936. /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
  4937. /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
  4938. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
  4939. /* .. .. */
  4940. EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
  4941. /* .. .. reg_ddrc_pageclose = 0x0 */
  4942. /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
  4943. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  4944. /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
  4945. /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
  4946. /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
  4947. /* .. .. reg_ddrc_auto_pre_en = 0x0 */
  4948. /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
  4949. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  4950. /* .. .. reg_ddrc_refresh_update_level = 0x0 */
  4951. /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
  4952. /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  4953. /* .. .. reg_ddrc_dis_wc = 0x0 */
  4954. /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
  4955. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  4956. /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
  4957. /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
  4958. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  4959. /* .. .. reg_ddrc_selfref_en = 0x0 */
  4960. /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
  4961. /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  4962. /* .. .. */
  4963. EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
  4964. /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
  4965. /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
  4966. /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
  4967. /* .. .. reg_arb_go2critical_en = 0x1 */
  4968. /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
  4969. /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
  4970. /* .. .. */
  4971. EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
  4972. /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
  4973. /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
  4974. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
  4975. /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
  4976. /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
  4977. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
  4978. /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
  4979. /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
  4980. /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
  4981. /* .. .. */
  4982. EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
  4983. /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
  4984. /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
  4985. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
  4986. /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
  4987. /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
  4988. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
  4989. /* .. .. */
  4990. EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
  4991. /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
  4992. /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
  4993. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
  4994. /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
  4995. /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
  4996. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
  4997. /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
  4998. /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
  4999. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
  5000. /* .. .. reg_ddrc_t_cksre = 0x6 */
  5001. /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
  5002. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
  5003. /* .. .. reg_ddrc_t_cksrx = 0x6 */
  5004. /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
  5005. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
  5006. /* .. .. reg_ddrc_t_ckesr = 0x4 */
  5007. /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
  5008. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
  5009. /* .. .. */
  5010. EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
  5011. /* .. .. reg_ddrc_t_ckpde = 0x2 */
  5012. /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
  5013. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
  5014. /* .. .. reg_ddrc_t_ckpdx = 0x2 */
  5015. /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
  5016. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
  5017. /* .. .. reg_ddrc_t_ckdpde = 0x2 */
  5018. /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
  5019. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  5020. /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
  5021. /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
  5022. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
  5023. /* .. .. reg_ddrc_t_ckcsx = 0x3 */
  5024. /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
  5025. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
  5026. /* .. .. */
  5027. EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
  5028. /* .. .. refresh_timer0_start_value_x32 = 0x0 */
  5029. /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
  5030. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
  5031. /* .. .. refresh_timer1_start_value_x32 = 0x8 */
  5032. /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
  5033. /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
  5034. /* .. .. */
  5035. EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
  5036. /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
  5037. /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
  5038. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5039. /* .. .. reg_ddrc_ddr3 = 0x1 */
  5040. /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
  5041. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  5042. /* .. .. reg_ddrc_t_mod = 0x200 */
  5043. /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
  5044. /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
  5045. /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
  5046. /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
  5047. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
  5048. /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
  5049. /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
  5050. /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
  5051. /* .. .. */
  5052. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
  5053. /* .. .. t_zq_short_interval_x1024 = 0xc845 */
  5054. /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
  5055. /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
  5056. /* .. .. dram_rstn_x1024 = 0x67 */
  5057. /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
  5058. /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
  5059. /* .. .. */
  5060. EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
  5061. /* .. .. deeppowerdown_en = 0x0 */
  5062. /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
  5063. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5064. /* .. .. deeppowerdown_to_x1024 = 0xff */
  5065. /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
  5066. /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
  5067. /* .. .. */
  5068. EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
  5069. /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
  5070. /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
  5071. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
  5072. /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
  5073. /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
  5074. /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
  5075. /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
  5076. /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
  5077. /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  5078. /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
  5079. /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
  5080. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  5081. /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
  5082. /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
  5083. /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
  5084. /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
  5085. /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
  5086. /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
  5087. /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
  5088. /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
  5089. /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  5090. /* .. .. */
  5091. EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
  5092. /* .. .. reg_ddrc_2t_delay = 0x0 */
  5093. /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
  5094. /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
  5095. /* .. .. reg_ddrc_skip_ocd = 0x1 */
  5096. /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
  5097. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
  5098. /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
  5099. /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
  5100. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5101. /* .. .. */
  5102. EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
  5103. /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
  5104. /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
  5105. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
  5106. /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
  5107. /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
  5108. /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
  5109. /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
  5110. /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
  5111. /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
  5112. /* .. .. */
  5113. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
  5114. /* .. .. START: RESET ECC ERROR */
  5115. /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
  5116. /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
  5117. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5118. /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
  5119. /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
  5120. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  5121. /* .. .. */
  5122. EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
  5123. /* .. .. FINISH: RESET ECC ERROR */
  5124. /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
  5125. /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
  5126. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5127. /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
  5128. /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
  5129. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5130. /* .. .. */
  5131. EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
  5132. /* .. .. CORR_ECC_LOG_VALID = 0x0 */
  5133. /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
  5134. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5135. /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
  5136. /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
  5137. /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
  5138. /* .. .. */
  5139. EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
  5140. /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
  5141. /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
  5142. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5143. /* .. .. */
  5144. EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
  5145. /* .. .. STAT_NUM_CORR_ERR = 0x0 */
  5146. /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
  5147. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
  5148. /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
  5149. /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
  5150. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
  5151. /* .. .. */
  5152. EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
  5153. /* .. .. reg_ddrc_ecc_mode = 0x0 */
  5154. /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
  5155. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
  5156. /* .. .. reg_ddrc_dis_scrub = 0x1 */
  5157. /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
  5158. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
  5159. /* .. .. */
  5160. EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
  5161. /* .. .. reg_phy_dif_on = 0x0 */
  5162. /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
  5163. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  5164. /* .. .. reg_phy_dif_off = 0x0 */
  5165. /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
  5166. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  5167. /* .. .. */
  5168. EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
  5169. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  5170. /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
  5171. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5172. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  5173. /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
  5174. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5175. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  5176. /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
  5177. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  5178. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  5179. /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
  5180. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5181. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  5182. /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
  5183. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5184. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  5185. /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
  5186. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  5187. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  5188. /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
  5189. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  5190. /* .. .. reg_phy_bist_err_clr = 0x0 */
  5191. /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
  5192. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  5193. /* .. .. reg_phy_dq_offset = 0x40 */
  5194. /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
  5195. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  5196. /* .. .. */
  5197. EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
  5198. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  5199. /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
  5200. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5201. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  5202. /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
  5203. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5204. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  5205. /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
  5206. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  5207. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  5208. /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
  5209. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5210. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  5211. /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
  5212. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5213. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  5214. /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
  5215. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  5216. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  5217. /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
  5218. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  5219. /* .. .. reg_phy_bist_err_clr = 0x0 */
  5220. /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
  5221. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  5222. /* .. .. reg_phy_dq_offset = 0x40 */
  5223. /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
  5224. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  5225. /* .. .. */
  5226. EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
  5227. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  5228. /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
  5229. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5230. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  5231. /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
  5232. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5233. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  5234. /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
  5235. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  5236. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  5237. /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
  5238. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5239. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  5240. /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
  5241. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5242. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  5243. /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
  5244. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  5245. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  5246. /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
  5247. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  5248. /* .. .. reg_phy_bist_err_clr = 0x0 */
  5249. /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
  5250. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  5251. /* .. .. reg_phy_dq_offset = 0x40 */
  5252. /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
  5253. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  5254. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  5255. /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
  5256. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5257. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  5258. /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
  5259. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5260. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  5261. /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
  5262. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  5263. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  5264. /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
  5265. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5266. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  5267. /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
  5268. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5269. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  5270. /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
  5271. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  5272. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  5273. /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
  5274. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  5275. /* .. .. reg_phy_bist_err_clr = 0x0 */
  5276. /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
  5277. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  5278. /* .. .. reg_phy_dq_offset = 0x40 */
  5279. /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
  5280. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  5281. /* .. .. */
  5282. EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
  5283. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  5284. /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
  5285. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5286. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  5287. /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
  5288. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5289. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  5290. /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
  5291. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  5292. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  5293. /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
  5294. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5295. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  5296. /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
  5297. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5298. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  5299. /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
  5300. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  5301. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  5302. /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
  5303. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  5304. /* .. .. reg_phy_bist_err_clr = 0x0 */
  5305. /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
  5306. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  5307. /* .. .. reg_phy_dq_offset = 0x40 */
  5308. /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
  5309. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  5310. /* .. .. */
  5311. EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
  5312. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  5313. /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
  5314. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  5315. /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
  5316. /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
  5317. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
  5318. /* .. .. */
  5319. EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
  5320. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  5321. /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
  5322. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  5323. /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
  5324. /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
  5325. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
  5326. /* .. .. */
  5327. EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
  5328. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  5329. /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
  5330. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  5331. /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
  5332. /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
  5333. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
  5334. /* .. .. */
  5335. EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
  5336. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  5337. /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
  5338. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  5339. /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
  5340. /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
  5341. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
  5342. /* .. .. */
  5343. EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
  5344. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  5345. /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
  5346. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  5347. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  5348. /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
  5349. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5350. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  5351. /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
  5352. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5353. /* .. .. */
  5354. EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
  5355. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  5356. /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
  5357. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  5358. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  5359. /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
  5360. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5361. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  5362. /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
  5363. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5364. /* .. .. */
  5365. EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
  5366. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  5367. /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
  5368. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  5369. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  5370. /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
  5371. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5372. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  5373. /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
  5374. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5375. /* .. .. */
  5376. EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
  5377. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  5378. /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
  5379. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  5380. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  5381. /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
  5382. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5383. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  5384. /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
  5385. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5386. /* .. .. */
  5387. EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
  5388. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
  5389. /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
  5390. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
  5391. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  5392. /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
  5393. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5394. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  5395. /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
  5396. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5397. /* .. .. */
  5398. EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
  5399. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
  5400. /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
  5401. /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
  5402. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  5403. /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
  5404. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5405. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  5406. /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
  5407. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5408. /* .. .. */
  5409. EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
  5410. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
  5411. /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
  5412. /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
  5413. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  5414. /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
  5415. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5416. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  5417. /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
  5418. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5419. /* .. .. */
  5420. EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
  5421. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
  5422. /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
  5423. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
  5424. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  5425. /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
  5426. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5427. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  5428. /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
  5429. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5430. /* .. .. */
  5431. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
  5432. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
  5433. /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
  5434. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
  5435. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  5436. /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
  5437. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5438. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  5439. /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
  5440. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  5441. /* .. .. */
  5442. EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
  5443. /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
  5444. /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
  5445. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
  5446. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  5447. /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
  5448. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5449. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  5450. /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
  5451. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  5452. /* .. .. */
  5453. EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
  5454. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
  5455. /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
  5456. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
  5457. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  5458. /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
  5459. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5460. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  5461. /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
  5462. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  5463. /* .. .. */
  5464. EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
  5465. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
  5466. /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
  5467. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
  5468. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  5469. /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
  5470. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5471. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  5472. /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
  5473. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  5474. /* .. .. */
  5475. EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
  5476. /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
  5477. /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
  5478. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
  5479. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  5480. /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
  5481. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5482. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  5483. /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
  5484. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5485. /* .. .. */
  5486. EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
  5487. /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
  5488. /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
  5489. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
  5490. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  5491. /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
  5492. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5493. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  5494. /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
  5495. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5496. /* .. .. */
  5497. EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
  5498. /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
  5499. /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
  5500. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
  5501. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  5502. /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
  5503. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5504. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  5505. /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
  5506. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5507. /* .. .. */
  5508. EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
  5509. /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
  5510. /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
  5511. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
  5512. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  5513. /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
  5514. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  5515. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  5516. /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
  5517. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  5518. /* .. .. */
  5519. EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
  5520. /* .. .. reg_phy_loopback = 0x0 */
  5521. /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
  5522. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5523. /* .. .. reg_phy_bl2 = 0x0 */
  5524. /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
  5525. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5526. /* .. .. reg_phy_at_spd_atpg = 0x0 */
  5527. /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
  5528. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  5529. /* .. .. reg_phy_bist_enable = 0x0 */
  5530. /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
  5531. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5532. /* .. .. reg_phy_bist_force_err = 0x0 */
  5533. /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
  5534. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5535. /* .. .. reg_phy_bist_mode = 0x0 */
  5536. /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
  5537. /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  5538. /* .. .. reg_phy_invert_clkout = 0x1 */
  5539. /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
  5540. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  5541. /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
  5542. /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
  5543. /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  5544. /* .. .. reg_phy_sel_logic = 0x0 */
  5545. /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
  5546. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  5547. /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
  5548. /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
  5549. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
  5550. /* .. .. reg_phy_ctrl_slave_force = 0x0 */
  5551. /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
  5552. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  5553. /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
  5554. /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
  5555. /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
  5556. /* .. .. reg_phy_use_rank0_delays = 0x1 */
  5557. /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
  5558. /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  5559. /* .. .. reg_phy_lpddr = 0x0 */
  5560. /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
  5561. /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
  5562. /* .. .. reg_phy_cmd_latency = 0x0 */
  5563. /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
  5564. /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
  5565. /* .. .. reg_phy_int_lpbk = 0x0 */
  5566. /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
  5567. /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
  5568. /* .. .. */
  5569. EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
  5570. /* .. .. reg_phy_wr_rl_delay = 0x2 */
  5571. /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
  5572. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
  5573. /* .. .. reg_phy_rd_rl_delay = 0x4 */
  5574. /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
  5575. /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
  5576. /* .. .. reg_phy_dll_lock_diff = 0xf */
  5577. /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
  5578. /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
  5579. /* .. .. reg_phy_use_wr_level = 0x1 */
  5580. /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
  5581. /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
  5582. /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
  5583. /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
  5584. /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
  5585. /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
  5586. /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
  5587. /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
  5588. /* .. .. reg_phy_dis_calib_rst = 0x0 */
  5589. /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
  5590. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5591. /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
  5592. /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
  5593. /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
  5594. /* .. .. */
  5595. EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
  5596. /* .. .. reg_arb_page_addr_mask = 0x0 */
  5597. /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
  5598. /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
  5599. /* .. .. */
  5600. EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
  5601. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  5602. /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
  5603. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5604. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  5605. /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
  5606. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5607. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  5608. /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
  5609. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5610. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  5611. /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
  5612. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5613. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  5614. /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
  5615. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  5616. /* .. .. */
  5617. EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
  5618. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  5619. /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
  5620. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5621. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  5622. /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
  5623. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5624. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  5625. /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
  5626. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5627. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  5628. /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
  5629. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5630. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  5631. /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
  5632. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  5633. /* .. .. */
  5634. EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
  5635. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  5636. /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
  5637. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5638. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  5639. /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
  5640. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5641. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  5642. /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
  5643. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5644. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  5645. /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
  5646. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5647. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  5648. /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
  5649. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  5650. /* .. .. */
  5651. EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
  5652. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  5653. /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
  5654. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5655. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  5656. /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
  5657. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5658. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  5659. /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
  5660. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5661. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  5662. /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
  5663. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5664. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  5665. /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
  5666. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  5667. /* .. .. */
  5668. EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
  5669. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  5670. /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
  5671. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5672. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  5673. /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
  5674. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5675. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  5676. /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
  5677. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5678. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  5679. /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
  5680. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5681. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  5682. /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
  5683. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  5684. /* .. .. */
  5685. EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
  5686. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  5687. /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
  5688. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5689. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  5690. /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
  5691. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5692. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  5693. /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
  5694. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5695. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  5696. /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
  5697. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5698. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  5699. /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
  5700. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  5701. /* .. .. */
  5702. EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
  5703. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  5704. /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
  5705. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5706. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  5707. /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
  5708. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5709. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  5710. /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
  5711. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5712. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  5713. /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
  5714. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5715. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  5716. /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
  5717. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  5718. /* .. .. */
  5719. EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
  5720. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  5721. /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
  5722. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  5723. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  5724. /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
  5725. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5726. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  5727. /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
  5728. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  5729. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  5730. /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
  5731. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  5732. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  5733. /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
  5734. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  5735. /* .. .. */
  5736. EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
  5737. /* .. .. reg_ddrc_lpddr2 = 0x0 */
  5738. /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
  5739. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5740. /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
  5741. /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
  5742. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5743. /* .. .. reg_ddrc_derate_enable = 0x0 */
  5744. /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
  5745. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  5746. /* .. .. reg_ddrc_mr4_margin = 0x0 */
  5747. /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
  5748. /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
  5749. /* .. .. */
  5750. EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
  5751. /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
  5752. /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
  5753. /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
  5754. /* .. .. */
  5755. EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
  5756. /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
  5757. /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
  5758. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
  5759. /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
  5760. /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
  5761. /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
  5762. /* .. .. reg_ddrc_t_mrw = 0x5 */
  5763. /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
  5764. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
  5765. /* .. .. */
  5766. EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
  5767. /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
  5768. /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
  5769. /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
  5770. /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
  5771. /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
  5772. /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
  5773. /* .. .. */
  5774. EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
  5775. /* .. .. START: POLL ON DCI STATUS */
  5776. /* .. .. DONE = 1 */
  5777. /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
  5778. /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  5779. /* .. .. */
  5780. EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
  5781. /* .. .. FINISH: POLL ON DCI STATUS */
  5782. /* .. .. START: UNLOCK DDR */
  5783. /* .. .. reg_ddrc_soft_rstb = 0x1 */
  5784. /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
  5785. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5786. /* .. .. reg_ddrc_powerdown_en = 0x0 */
  5787. /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
  5788. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5789. /* .. .. reg_ddrc_data_bus_width = 0x0 */
  5790. /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
  5791. /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
  5792. /* .. .. reg_ddrc_burst8_refresh = 0x0 */
  5793. /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
  5794. /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  5795. /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
  5796. /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
  5797. /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
  5798. /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
  5799. /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
  5800. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  5801. /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
  5802. /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
  5803. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  5804. /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
  5805. /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
  5806. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  5807. /* .. .. */
  5808. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
  5809. /* .. .. FINISH: UNLOCK DDR */
  5810. /* .. .. START: CHECK DDR STATUS */
  5811. /* .. .. ddrc_reg_operating_mode = 1 */
  5812. /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
  5813. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
  5814. /* .. .. */
  5815. EMIT_MASKPOLL(0XF8006054, 0x00000007U),
  5816. /* .. .. FINISH: CHECK DDR STATUS */
  5817. /* .. FINISH: DDR INITIALIZATION */
  5818. /* FINISH: top */
  5819. /* */
  5820. EMIT_EXIT(),
  5821. /* */
  5822. };
  5823. unsigned long ps7_mio_init_data_2_0[] = {
  5824. /* START: top */
  5825. /* .. START: SLCR SETTINGS */
  5826. /* .. UNLOCK_KEY = 0XDF0D */
  5827. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  5828. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  5829. /* .. */
  5830. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  5831. /* .. FINISH: SLCR SETTINGS */
  5832. /* .. START: OCM REMAPPING */
  5833. /* .. VREF_EN = 0x1 */
  5834. /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
  5835. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  5836. /* .. VREF_PULLUP_EN = 0x0 */
  5837. /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
  5838. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  5839. /* .. CLK_PULLUP_EN = 0x0 */
  5840. /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
  5841. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  5842. /* .. SRSTN_PULLUP_EN = 0x0 */
  5843. /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
  5844. /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  5845. /* .. */
  5846. EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
  5847. /* .. FINISH: OCM REMAPPING */
  5848. /* .. START: DDRIOB SETTINGS */
  5849. /* .. INP_POWER = 0x0 */
  5850. /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
  5851. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5852. /* .. INP_TYPE = 0x0 */
  5853. /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
  5854. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  5855. /* .. DCI_UPDATE = 0x0 */
  5856. /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
  5857. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5858. /* .. TERM_EN = 0x0 */
  5859. /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
  5860. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5861. /* .. DCR_TYPE = 0x0 */
  5862. /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
  5863. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  5864. /* .. IBUF_DISABLE_MODE = 0x0 */
  5865. /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
  5866. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  5867. /* .. TERM_DISABLE_MODE = 0x0 */
  5868. /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
  5869. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  5870. /* .. OUTPUT_EN = 0x3 */
  5871. /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
  5872. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  5873. /* .. PULLUP_EN = 0x0 */
  5874. /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
  5875. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5876. /* .. */
  5877. EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
  5878. /* .. INP_POWER = 0x0 */
  5879. /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
  5880. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5881. /* .. INP_TYPE = 0x0 */
  5882. /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
  5883. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  5884. /* .. DCI_UPDATE = 0x0 */
  5885. /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
  5886. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5887. /* .. TERM_EN = 0x0 */
  5888. /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
  5889. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  5890. /* .. DCR_TYPE = 0x0 */
  5891. /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
  5892. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  5893. /* .. IBUF_DISABLE_MODE = 0x0 */
  5894. /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
  5895. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  5896. /* .. TERM_DISABLE_MODE = 0x0 */
  5897. /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
  5898. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  5899. /* .. OUTPUT_EN = 0x3 */
  5900. /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
  5901. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  5902. /* .. PULLUP_EN = 0x0 */
  5903. /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
  5904. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5905. /* .. */
  5906. EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
  5907. /* .. INP_POWER = 0x0 */
  5908. /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
  5909. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5910. /* .. INP_TYPE = 0x1 */
  5911. /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
  5912. /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
  5913. /* .. DCI_UPDATE = 0x0 */
  5914. /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
  5915. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5916. /* .. TERM_EN = 0x1 */
  5917. /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
  5918. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  5919. /* .. DCR_TYPE = 0x3 */
  5920. /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
  5921. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  5922. /* .. IBUF_DISABLE_MODE = 0 */
  5923. /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
  5924. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  5925. /* .. TERM_DISABLE_MODE = 0 */
  5926. /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
  5927. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  5928. /* .. OUTPUT_EN = 0x3 */
  5929. /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
  5930. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  5931. /* .. PULLUP_EN = 0x0 */
  5932. /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
  5933. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5934. /* .. */
  5935. EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
  5936. /* .. INP_POWER = 0x0 */
  5937. /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
  5938. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5939. /* .. INP_TYPE = 0x1 */
  5940. /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
  5941. /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
  5942. /* .. DCI_UPDATE = 0x0 */
  5943. /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
  5944. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5945. /* .. TERM_EN = 0x1 */
  5946. /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
  5947. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  5948. /* .. DCR_TYPE = 0x3 */
  5949. /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
  5950. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  5951. /* .. IBUF_DISABLE_MODE = 0 */
  5952. /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
  5953. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  5954. /* .. TERM_DISABLE_MODE = 0 */
  5955. /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
  5956. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  5957. /* .. OUTPUT_EN = 0x3 */
  5958. /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
  5959. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  5960. /* .. PULLUP_EN = 0x0 */
  5961. /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
  5962. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5963. /* .. */
  5964. EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
  5965. /* .. INP_POWER = 0x0 */
  5966. /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
  5967. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5968. /* .. INP_TYPE = 0x2 */
  5969. /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
  5970. /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
  5971. /* .. DCI_UPDATE = 0x0 */
  5972. /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
  5973. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  5974. /* .. TERM_EN = 0x1 */
  5975. /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
  5976. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  5977. /* .. DCR_TYPE = 0x3 */
  5978. /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
  5979. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  5980. /* .. IBUF_DISABLE_MODE = 0 */
  5981. /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
  5982. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  5983. /* .. TERM_DISABLE_MODE = 0 */
  5984. /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
  5985. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  5986. /* .. OUTPUT_EN = 0x3 */
  5987. /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
  5988. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  5989. /* .. PULLUP_EN = 0x0 */
  5990. /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
  5991. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  5992. /* .. */
  5993. EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
  5994. /* .. INP_POWER = 0x0 */
  5995. /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
  5996. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  5997. /* .. INP_TYPE = 0x2 */
  5998. /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
  5999. /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
  6000. /* .. DCI_UPDATE = 0x0 */
  6001. /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
  6002. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  6003. /* .. TERM_EN = 0x1 */
  6004. /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
  6005. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  6006. /* .. DCR_TYPE = 0x3 */
  6007. /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
  6008. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  6009. /* .. IBUF_DISABLE_MODE = 0 */
  6010. /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
  6011. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  6012. /* .. TERM_DISABLE_MODE = 0 */
  6013. /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
  6014. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6015. /* .. OUTPUT_EN = 0x3 */
  6016. /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
  6017. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  6018. /* .. PULLUP_EN = 0x0 */
  6019. /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
  6020. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  6021. /* .. */
  6022. EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
  6023. /* .. INP_POWER = 0x0 */
  6024. /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
  6025. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6026. /* .. INP_TYPE = 0x0 */
  6027. /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
  6028. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  6029. /* .. DCI_UPDATE = 0x0 */
  6030. /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
  6031. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  6032. /* .. TERM_EN = 0x0 */
  6033. /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
  6034. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  6035. /* .. DCR_TYPE = 0x0 */
  6036. /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
  6037. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  6038. /* .. IBUF_DISABLE_MODE = 0x0 */
  6039. /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
  6040. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  6041. /* .. TERM_DISABLE_MODE = 0x0 */
  6042. /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
  6043. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6044. /* .. OUTPUT_EN = 0x3 */
  6045. /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
  6046. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  6047. /* .. PULLUP_EN = 0x0 */
  6048. /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
  6049. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  6050. /* .. */
  6051. EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
  6052. /* .. DRIVE_P = 0x1c */
  6053. /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
  6054. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  6055. /* .. DRIVE_N = 0xc */
  6056. /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
  6057. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  6058. /* .. SLEW_P = 0x3 */
  6059. /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
  6060. /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
  6061. /* .. SLEW_N = 0x3 */
  6062. /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
  6063. /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
  6064. /* .. GTL = 0x0 */
  6065. /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
  6066. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  6067. /* .. RTERM = 0x0 */
  6068. /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
  6069. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  6070. /* .. */
  6071. EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
  6072. /* .. DRIVE_P = 0x1c */
  6073. /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
  6074. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  6075. /* .. DRIVE_N = 0xc */
  6076. /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
  6077. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  6078. /* .. SLEW_P = 0x6 */
  6079. /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
  6080. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  6081. /* .. SLEW_N = 0x1f */
  6082. /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
  6083. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  6084. /* .. GTL = 0x0 */
  6085. /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
  6086. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  6087. /* .. RTERM = 0x0 */
  6088. /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
  6089. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  6090. /* .. */
  6091. EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
  6092. /* .. DRIVE_P = 0x1c */
  6093. /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
  6094. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  6095. /* .. DRIVE_N = 0xc */
  6096. /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
  6097. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  6098. /* .. SLEW_P = 0x6 */
  6099. /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
  6100. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  6101. /* .. SLEW_N = 0x1f */
  6102. /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
  6103. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  6104. /* .. GTL = 0x0 */
  6105. /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
  6106. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  6107. /* .. RTERM = 0x0 */
  6108. /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
  6109. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  6110. /* .. */
  6111. EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
  6112. /* .. DRIVE_P = 0x1c */
  6113. /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
  6114. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  6115. /* .. DRIVE_N = 0xc */
  6116. /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
  6117. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  6118. /* .. SLEW_P = 0x6 */
  6119. /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
  6120. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  6121. /* .. SLEW_N = 0x1f */
  6122. /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
  6123. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  6124. /* .. GTL = 0x0 */
  6125. /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
  6126. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  6127. /* .. RTERM = 0x0 */
  6128. /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
  6129. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  6130. /* .. */
  6131. EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
  6132. /* .. VREF_INT_EN = 0x0 */
  6133. /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
  6134. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6135. /* .. VREF_SEL = 0x0 */
  6136. /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
  6137. /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
  6138. /* .. VREF_EXT_EN = 0x3 */
  6139. /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
  6140. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  6141. /* .. VREF_PULLUP_EN = 0x0 */
  6142. /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
  6143. /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
  6144. /* .. REFIO_EN = 0x1 */
  6145. /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
  6146. /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
  6147. /* .. REFIO_TEST = 0x0 */
  6148. /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
  6149. /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
  6150. /* .. REFIO_PULLUP_EN = 0x0 */
  6151. /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
  6152. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6153. /* .. DRST_B_PULLUP_EN = 0x0 */
  6154. /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
  6155. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6156. /* .. CKE_PULLUP_EN = 0x0 */
  6157. /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
  6158. /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  6159. /* .. */
  6160. EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
  6161. /* .. .. START: ASSERT RESET */
  6162. /* .. .. RESET = 1 */
  6163. /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
  6164. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  6165. /* .. .. VRN_OUT = 0x1 */
  6166. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  6167. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  6168. /* .. .. */
  6169. EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
  6170. /* .. .. FINISH: ASSERT RESET */
  6171. /* .. .. START: DEASSERT RESET */
  6172. /* .. .. RESET = 0 */
  6173. /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
  6174. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6175. /* .. .. VRN_OUT = 0x1 */
  6176. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  6177. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  6178. /* .. .. */
  6179. EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
  6180. /* .. .. FINISH: DEASSERT RESET */
  6181. /* .. .. RESET = 0x1 */
  6182. /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
  6183. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  6184. /* .. .. ENABLE = 0x1 */
  6185. /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
  6186. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6187. /* .. .. VRP_TRI = 0x0 */
  6188. /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
  6189. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6190. /* .. .. VRN_TRI = 0x0 */
  6191. /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
  6192. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  6193. /* .. .. VRP_OUT = 0x0 */
  6194. /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
  6195. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  6196. /* .. .. VRN_OUT = 0x1 */
  6197. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  6198. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  6199. /* .. .. NREF_OPT1 = 0x0 */
  6200. /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
  6201. /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
  6202. /* .. .. NREF_OPT2 = 0x0 */
  6203. /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
  6204. /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
  6205. /* .. .. NREF_OPT4 = 0x1 */
  6206. /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
  6207. /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
  6208. /* .. .. PREF_OPT1 = 0x0 */
  6209. /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
  6210. /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
  6211. /* .. .. PREF_OPT2 = 0x0 */
  6212. /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
  6213. /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
  6214. /* .. .. UPDATE_CONTROL = 0x0 */
  6215. /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
  6216. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  6217. /* .. .. INIT_COMPLETE = 0x0 */
  6218. /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
  6219. /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  6220. /* .. .. TST_CLK = 0x0 */
  6221. /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
  6222. /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  6223. /* .. .. TST_HLN = 0x0 */
  6224. /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
  6225. /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  6226. /* .. .. TST_HLP = 0x0 */
  6227. /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
  6228. /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  6229. /* .. .. TST_RST = 0x0 */
  6230. /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
  6231. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  6232. /* .. .. INT_DCI_EN = 0x0 */
  6233. /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
  6234. /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
  6235. /* .. .. */
  6236. EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
  6237. /* .. FINISH: DDRIOB SETTINGS */
  6238. /* .. START: MIO PROGRAMMING */
  6239. /* .. TRI_ENABLE = 0 */
  6240. /* .. ==> 0XF8000700[0:0] = 0x00000000U */
  6241. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6242. /* .. L0_SEL = 0 */
  6243. /* .. ==> 0XF8000700[1:1] = 0x00000000U */
  6244. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6245. /* .. L1_SEL = 0 */
  6246. /* .. ==> 0XF8000700[2:2] = 0x00000000U */
  6247. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6248. /* .. L2_SEL = 0 */
  6249. /* .. ==> 0XF8000700[4:3] = 0x00000000U */
  6250. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6251. /* .. L3_SEL = 0 */
  6252. /* .. ==> 0XF8000700[7:5] = 0x00000000U */
  6253. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6254. /* .. Speed = 0 */
  6255. /* .. ==> 0XF8000700[8:8] = 0x00000000U */
  6256. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6257. /* .. IO_Type = 3 */
  6258. /* .. ==> 0XF8000700[11:9] = 0x00000003U */
  6259. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6260. /* .. PULLUP = 1 */
  6261. /* .. ==> 0XF8000700[12:12] = 0x00000001U */
  6262. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6263. /* .. DisableRcvr = 0 */
  6264. /* .. ==> 0XF8000700[13:13] = 0x00000000U */
  6265. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6266. /* .. */
  6267. EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
  6268. /* .. TRI_ENABLE = 0 */
  6269. /* .. ==> 0XF8000704[0:0] = 0x00000000U */
  6270. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6271. /* .. L0_SEL = 1 */
  6272. /* .. ==> 0XF8000704[1:1] = 0x00000001U */
  6273. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6274. /* .. L1_SEL = 0 */
  6275. /* .. ==> 0XF8000704[2:2] = 0x00000000U */
  6276. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6277. /* .. L2_SEL = 0 */
  6278. /* .. ==> 0XF8000704[4:3] = 0x00000000U */
  6279. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6280. /* .. L3_SEL = 0 */
  6281. /* .. ==> 0XF8000704[7:5] = 0x00000000U */
  6282. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6283. /* .. Speed = 1 */
  6284. /* .. ==> 0XF8000704[8:8] = 0x00000001U */
  6285. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6286. /* .. IO_Type = 3 */
  6287. /* .. ==> 0XF8000704[11:9] = 0x00000003U */
  6288. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6289. /* .. PULLUP = 0 */
  6290. /* .. ==> 0XF8000704[12:12] = 0x00000000U */
  6291. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6292. /* .. DisableRcvr = 0 */
  6293. /* .. ==> 0XF8000704[13:13] = 0x00000000U */
  6294. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6295. /* .. */
  6296. EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
  6297. /* .. TRI_ENABLE = 0 */
  6298. /* .. ==> 0XF8000708[0:0] = 0x00000000U */
  6299. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6300. /* .. L0_SEL = 1 */
  6301. /* .. ==> 0XF8000708[1:1] = 0x00000001U */
  6302. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6303. /* .. L1_SEL = 0 */
  6304. /* .. ==> 0XF8000708[2:2] = 0x00000000U */
  6305. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6306. /* .. L2_SEL = 0 */
  6307. /* .. ==> 0XF8000708[4:3] = 0x00000000U */
  6308. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6309. /* .. L3_SEL = 0 */
  6310. /* .. ==> 0XF8000708[7:5] = 0x00000000U */
  6311. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6312. /* .. Speed = 1 */
  6313. /* .. ==> 0XF8000708[8:8] = 0x00000001U */
  6314. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6315. /* .. IO_Type = 3 */
  6316. /* .. ==> 0XF8000708[11:9] = 0x00000003U */
  6317. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6318. /* .. PULLUP = 0 */
  6319. /* .. ==> 0XF8000708[12:12] = 0x00000000U */
  6320. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6321. /* .. DisableRcvr = 0 */
  6322. /* .. ==> 0XF8000708[13:13] = 0x00000000U */
  6323. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6324. /* .. */
  6325. EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
  6326. /* .. TRI_ENABLE = 0 */
  6327. /* .. ==> 0XF800070C[0:0] = 0x00000000U */
  6328. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6329. /* .. L0_SEL = 1 */
  6330. /* .. ==> 0XF800070C[1:1] = 0x00000001U */
  6331. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6332. /* .. L1_SEL = 0 */
  6333. /* .. ==> 0XF800070C[2:2] = 0x00000000U */
  6334. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6335. /* .. L2_SEL = 0 */
  6336. /* .. ==> 0XF800070C[4:3] = 0x00000000U */
  6337. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6338. /* .. L3_SEL = 0 */
  6339. /* .. ==> 0XF800070C[7:5] = 0x00000000U */
  6340. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6341. /* .. Speed = 1 */
  6342. /* .. ==> 0XF800070C[8:8] = 0x00000001U */
  6343. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6344. /* .. IO_Type = 3 */
  6345. /* .. ==> 0XF800070C[11:9] = 0x00000003U */
  6346. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6347. /* .. PULLUP = 0 */
  6348. /* .. ==> 0XF800070C[12:12] = 0x00000000U */
  6349. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6350. /* .. DisableRcvr = 0 */
  6351. /* .. ==> 0XF800070C[13:13] = 0x00000000U */
  6352. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6353. /* .. */
  6354. EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
  6355. /* .. TRI_ENABLE = 0 */
  6356. /* .. ==> 0XF8000710[0:0] = 0x00000000U */
  6357. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6358. /* .. L0_SEL = 1 */
  6359. /* .. ==> 0XF8000710[1:1] = 0x00000001U */
  6360. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6361. /* .. L1_SEL = 0 */
  6362. /* .. ==> 0XF8000710[2:2] = 0x00000000U */
  6363. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6364. /* .. L2_SEL = 0 */
  6365. /* .. ==> 0XF8000710[4:3] = 0x00000000U */
  6366. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6367. /* .. L3_SEL = 0 */
  6368. /* .. ==> 0XF8000710[7:5] = 0x00000000U */
  6369. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6370. /* .. Speed = 1 */
  6371. /* .. ==> 0XF8000710[8:8] = 0x00000001U */
  6372. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6373. /* .. IO_Type = 3 */
  6374. /* .. ==> 0XF8000710[11:9] = 0x00000003U */
  6375. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6376. /* .. PULLUP = 0 */
  6377. /* .. ==> 0XF8000710[12:12] = 0x00000000U */
  6378. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6379. /* .. DisableRcvr = 0 */
  6380. /* .. ==> 0XF8000710[13:13] = 0x00000000U */
  6381. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6382. /* .. */
  6383. EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
  6384. /* .. TRI_ENABLE = 0 */
  6385. /* .. ==> 0XF8000714[0:0] = 0x00000000U */
  6386. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6387. /* .. L0_SEL = 1 */
  6388. /* .. ==> 0XF8000714[1:1] = 0x00000001U */
  6389. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6390. /* .. L1_SEL = 0 */
  6391. /* .. ==> 0XF8000714[2:2] = 0x00000000U */
  6392. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6393. /* .. L2_SEL = 0 */
  6394. /* .. ==> 0XF8000714[4:3] = 0x00000000U */
  6395. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6396. /* .. L3_SEL = 0 */
  6397. /* .. ==> 0XF8000714[7:5] = 0x00000000U */
  6398. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6399. /* .. Speed = 1 */
  6400. /* .. ==> 0XF8000714[8:8] = 0x00000001U */
  6401. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6402. /* .. IO_Type = 3 */
  6403. /* .. ==> 0XF8000714[11:9] = 0x00000003U */
  6404. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6405. /* .. PULLUP = 0 */
  6406. /* .. ==> 0XF8000714[12:12] = 0x00000000U */
  6407. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6408. /* .. DisableRcvr = 0 */
  6409. /* .. ==> 0XF8000714[13:13] = 0x00000000U */
  6410. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6411. /* .. */
  6412. EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
  6413. /* .. TRI_ENABLE = 0 */
  6414. /* .. ==> 0XF8000718[0:0] = 0x00000000U */
  6415. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6416. /* .. L0_SEL = 1 */
  6417. /* .. ==> 0XF8000718[1:1] = 0x00000001U */
  6418. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6419. /* .. L1_SEL = 0 */
  6420. /* .. ==> 0XF8000718[2:2] = 0x00000000U */
  6421. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6422. /* .. L2_SEL = 0 */
  6423. /* .. ==> 0XF8000718[4:3] = 0x00000000U */
  6424. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6425. /* .. L3_SEL = 0 */
  6426. /* .. ==> 0XF8000718[7:5] = 0x00000000U */
  6427. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6428. /* .. Speed = 1 */
  6429. /* .. ==> 0XF8000718[8:8] = 0x00000001U */
  6430. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6431. /* .. IO_Type = 3 */
  6432. /* .. ==> 0XF8000718[11:9] = 0x00000003U */
  6433. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6434. /* .. PULLUP = 0 */
  6435. /* .. ==> 0XF8000718[12:12] = 0x00000000U */
  6436. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6437. /* .. DisableRcvr = 0 */
  6438. /* .. ==> 0XF8000718[13:13] = 0x00000000U */
  6439. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6440. /* .. */
  6441. EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
  6442. /* .. TRI_ENABLE = 0 */
  6443. /* .. ==> 0XF800071C[0:0] = 0x00000000U */
  6444. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6445. /* .. L0_SEL = 0 */
  6446. /* .. ==> 0XF800071C[1:1] = 0x00000000U */
  6447. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6448. /* .. L1_SEL = 0 */
  6449. /* .. ==> 0XF800071C[2:2] = 0x00000000U */
  6450. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6451. /* .. L2_SEL = 0 */
  6452. /* .. ==> 0XF800071C[4:3] = 0x00000000U */
  6453. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6454. /* .. L3_SEL = 0 */
  6455. /* .. ==> 0XF800071C[7:5] = 0x00000000U */
  6456. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6457. /* .. Speed = 0 */
  6458. /* .. ==> 0XF800071C[8:8] = 0x00000000U */
  6459. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6460. /* .. IO_Type = 3 */
  6461. /* .. ==> 0XF800071C[11:9] = 0x00000003U */
  6462. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6463. /* .. PULLUP = 0 */
  6464. /* .. ==> 0XF800071C[12:12] = 0x00000000U */
  6465. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6466. /* .. DisableRcvr = 0 */
  6467. /* .. ==> 0XF800071C[13:13] = 0x00000000U */
  6468. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6469. /* .. */
  6470. EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
  6471. /* .. TRI_ENABLE = 0 */
  6472. /* .. ==> 0XF8000720[0:0] = 0x00000000U */
  6473. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6474. /* .. L0_SEL = 1 */
  6475. /* .. ==> 0XF8000720[1:1] = 0x00000001U */
  6476. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6477. /* .. L1_SEL = 0 */
  6478. /* .. ==> 0XF8000720[2:2] = 0x00000000U */
  6479. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6480. /* .. L2_SEL = 0 */
  6481. /* .. ==> 0XF8000720[4:3] = 0x00000000U */
  6482. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6483. /* .. L3_SEL = 0 */
  6484. /* .. ==> 0XF8000720[7:5] = 0x00000000U */
  6485. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6486. /* .. Speed = 1 */
  6487. /* .. ==> 0XF8000720[8:8] = 0x00000001U */
  6488. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6489. /* .. IO_Type = 3 */
  6490. /* .. ==> 0XF8000720[11:9] = 0x00000003U */
  6491. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6492. /* .. PULLUP = 0 */
  6493. /* .. ==> 0XF8000720[12:12] = 0x00000000U */
  6494. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6495. /* .. DisableRcvr = 0 */
  6496. /* .. ==> 0XF8000720[13:13] = 0x00000000U */
  6497. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6498. /* .. */
  6499. EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
  6500. /* .. TRI_ENABLE = 0 */
  6501. /* .. ==> 0XF8000724[0:0] = 0x00000000U */
  6502. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6503. /* .. L0_SEL = 0 */
  6504. /* .. ==> 0XF8000724[1:1] = 0x00000000U */
  6505. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6506. /* .. L1_SEL = 0 */
  6507. /* .. ==> 0XF8000724[2:2] = 0x00000000U */
  6508. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6509. /* .. L2_SEL = 0 */
  6510. /* .. ==> 0XF8000724[4:3] = 0x00000000U */
  6511. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6512. /* .. L3_SEL = 0 */
  6513. /* .. ==> 0XF8000724[7:5] = 0x00000000U */
  6514. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6515. /* .. Speed = 0 */
  6516. /* .. ==> 0XF8000724[8:8] = 0x00000000U */
  6517. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6518. /* .. IO_Type = 3 */
  6519. /* .. ==> 0XF8000724[11:9] = 0x00000003U */
  6520. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6521. /* .. PULLUP = 1 */
  6522. /* .. ==> 0XF8000724[12:12] = 0x00000001U */
  6523. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6524. /* .. DisableRcvr = 0 */
  6525. /* .. ==> 0XF8000724[13:13] = 0x00000000U */
  6526. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6527. /* .. */
  6528. EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
  6529. /* .. TRI_ENABLE = 0 */
  6530. /* .. ==> 0XF8000728[0:0] = 0x00000000U */
  6531. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6532. /* .. L0_SEL = 0 */
  6533. /* .. ==> 0XF8000728[1:1] = 0x00000000U */
  6534. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6535. /* .. L1_SEL = 0 */
  6536. /* .. ==> 0XF8000728[2:2] = 0x00000000U */
  6537. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6538. /* .. L2_SEL = 0 */
  6539. /* .. ==> 0XF8000728[4:3] = 0x00000000U */
  6540. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6541. /* .. L3_SEL = 0 */
  6542. /* .. ==> 0XF8000728[7:5] = 0x00000000U */
  6543. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6544. /* .. Speed = 0 */
  6545. /* .. ==> 0XF8000728[8:8] = 0x00000000U */
  6546. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6547. /* .. IO_Type = 3 */
  6548. /* .. ==> 0XF8000728[11:9] = 0x00000003U */
  6549. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6550. /* .. PULLUP = 1 */
  6551. /* .. ==> 0XF8000728[12:12] = 0x00000001U */
  6552. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6553. /* .. DisableRcvr = 0 */
  6554. /* .. ==> 0XF8000728[13:13] = 0x00000000U */
  6555. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6556. /* .. */
  6557. EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
  6558. /* .. TRI_ENABLE = 0 */
  6559. /* .. ==> 0XF800072C[0:0] = 0x00000000U */
  6560. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6561. /* .. L0_SEL = 0 */
  6562. /* .. ==> 0XF800072C[1:1] = 0x00000000U */
  6563. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6564. /* .. L1_SEL = 0 */
  6565. /* .. ==> 0XF800072C[2:2] = 0x00000000U */
  6566. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6567. /* .. L2_SEL = 0 */
  6568. /* .. ==> 0XF800072C[4:3] = 0x00000000U */
  6569. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6570. /* .. L3_SEL = 0 */
  6571. /* .. ==> 0XF800072C[7:5] = 0x00000000U */
  6572. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6573. /* .. Speed = 0 */
  6574. /* .. ==> 0XF800072C[8:8] = 0x00000000U */
  6575. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6576. /* .. IO_Type = 3 */
  6577. /* .. ==> 0XF800072C[11:9] = 0x00000003U */
  6578. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6579. /* .. PULLUP = 1 */
  6580. /* .. ==> 0XF800072C[12:12] = 0x00000001U */
  6581. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6582. /* .. DisableRcvr = 0 */
  6583. /* .. ==> 0XF800072C[13:13] = 0x00000000U */
  6584. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6585. /* .. */
  6586. EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
  6587. /* .. TRI_ENABLE = 0 */
  6588. /* .. ==> 0XF8000730[0:0] = 0x00000000U */
  6589. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6590. /* .. L0_SEL = 0 */
  6591. /* .. ==> 0XF8000730[1:1] = 0x00000000U */
  6592. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6593. /* .. L1_SEL = 0 */
  6594. /* .. ==> 0XF8000730[2:2] = 0x00000000U */
  6595. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6596. /* .. L2_SEL = 0 */
  6597. /* .. ==> 0XF8000730[4:3] = 0x00000000U */
  6598. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6599. /* .. L3_SEL = 0 */
  6600. /* .. ==> 0XF8000730[7:5] = 0x00000000U */
  6601. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6602. /* .. Speed = 0 */
  6603. /* .. ==> 0XF8000730[8:8] = 0x00000000U */
  6604. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6605. /* .. IO_Type = 3 */
  6606. /* .. ==> 0XF8000730[11:9] = 0x00000003U */
  6607. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6608. /* .. PULLUP = 1 */
  6609. /* .. ==> 0XF8000730[12:12] = 0x00000001U */
  6610. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6611. /* .. DisableRcvr = 0 */
  6612. /* .. ==> 0XF8000730[13:13] = 0x00000000U */
  6613. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6614. /* .. */
  6615. EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
  6616. /* .. TRI_ENABLE = 0 */
  6617. /* .. ==> 0XF8000734[0:0] = 0x00000000U */
  6618. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6619. /* .. L0_SEL = 0 */
  6620. /* .. ==> 0XF8000734[1:1] = 0x00000000U */
  6621. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6622. /* .. L1_SEL = 0 */
  6623. /* .. ==> 0XF8000734[2:2] = 0x00000000U */
  6624. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6625. /* .. L2_SEL = 0 */
  6626. /* .. ==> 0XF8000734[4:3] = 0x00000000U */
  6627. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6628. /* .. L3_SEL = 0 */
  6629. /* .. ==> 0XF8000734[7:5] = 0x00000000U */
  6630. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6631. /* .. Speed = 0 */
  6632. /* .. ==> 0XF8000734[8:8] = 0x00000000U */
  6633. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6634. /* .. IO_Type = 3 */
  6635. /* .. ==> 0XF8000734[11:9] = 0x00000003U */
  6636. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6637. /* .. PULLUP = 1 */
  6638. /* .. ==> 0XF8000734[12:12] = 0x00000001U */
  6639. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6640. /* .. DisableRcvr = 0 */
  6641. /* .. ==> 0XF8000734[13:13] = 0x00000000U */
  6642. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6643. /* .. */
  6644. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
  6645. /* .. TRI_ENABLE = 0 */
  6646. /* .. ==> 0XF8000738[0:0] = 0x00000000U */
  6647. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6648. /* .. L0_SEL = 0 */
  6649. /* .. ==> 0XF8000738[1:1] = 0x00000000U */
  6650. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6651. /* .. L1_SEL = 0 */
  6652. /* .. ==> 0XF8000738[2:2] = 0x00000000U */
  6653. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6654. /* .. L2_SEL = 0 */
  6655. /* .. ==> 0XF8000738[4:3] = 0x00000000U */
  6656. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6657. /* .. L3_SEL = 0 */
  6658. /* .. ==> 0XF8000738[7:5] = 0x00000000U */
  6659. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6660. /* .. Speed = 0 */
  6661. /* .. ==> 0XF8000738[8:8] = 0x00000000U */
  6662. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6663. /* .. IO_Type = 3 */
  6664. /* .. ==> 0XF8000738[11:9] = 0x00000003U */
  6665. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6666. /* .. PULLUP = 1 */
  6667. /* .. ==> 0XF8000738[12:12] = 0x00000001U */
  6668. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6669. /* .. DisableRcvr = 0 */
  6670. /* .. ==> 0XF8000738[13:13] = 0x00000000U */
  6671. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6672. /* .. */
  6673. EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
  6674. /* .. TRI_ENABLE = 0 */
  6675. /* .. ==> 0XF800073C[0:0] = 0x00000000U */
  6676. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6677. /* .. L0_SEL = 0 */
  6678. /* .. ==> 0XF800073C[1:1] = 0x00000000U */
  6679. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  6680. /* .. L1_SEL = 0 */
  6681. /* .. ==> 0XF800073C[2:2] = 0x00000000U */
  6682. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6683. /* .. L2_SEL = 0 */
  6684. /* .. ==> 0XF800073C[4:3] = 0x00000000U */
  6685. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6686. /* .. L3_SEL = 0 */
  6687. /* .. ==> 0XF800073C[7:5] = 0x00000000U */
  6688. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6689. /* .. Speed = 0 */
  6690. /* .. ==> 0XF800073C[8:8] = 0x00000000U */
  6691. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  6692. /* .. IO_Type = 3 */
  6693. /* .. ==> 0XF800073C[11:9] = 0x00000003U */
  6694. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  6695. /* .. PULLUP = 1 */
  6696. /* .. ==> 0XF800073C[12:12] = 0x00000001U */
  6697. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  6698. /* .. DisableRcvr = 0 */
  6699. /* .. ==> 0XF800073C[13:13] = 0x00000000U */
  6700. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6701. /* .. */
  6702. EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
  6703. /* .. TRI_ENABLE = 0 */
  6704. /* .. ==> 0XF8000740[0:0] = 0x00000000U */
  6705. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6706. /* .. L0_SEL = 1 */
  6707. /* .. ==> 0XF8000740[1:1] = 0x00000001U */
  6708. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6709. /* .. L1_SEL = 0 */
  6710. /* .. ==> 0XF8000740[2:2] = 0x00000000U */
  6711. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6712. /* .. L2_SEL = 0 */
  6713. /* .. ==> 0XF8000740[4:3] = 0x00000000U */
  6714. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6715. /* .. L3_SEL = 0 */
  6716. /* .. ==> 0XF8000740[7:5] = 0x00000000U */
  6717. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6718. /* .. Speed = 1 */
  6719. /* .. ==> 0XF8000740[8:8] = 0x00000001U */
  6720. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6721. /* .. IO_Type = 4 */
  6722. /* .. ==> 0XF8000740[11:9] = 0x00000004U */
  6723. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6724. /* .. PULLUP = 0 */
  6725. /* .. ==> 0XF8000740[12:12] = 0x00000000U */
  6726. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6727. /* .. DisableRcvr = 1 */
  6728. /* .. ==> 0XF8000740[13:13] = 0x00000001U */
  6729. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  6730. /* .. */
  6731. EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
  6732. /* .. TRI_ENABLE = 0 */
  6733. /* .. ==> 0XF8000744[0:0] = 0x00000000U */
  6734. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6735. /* .. L0_SEL = 1 */
  6736. /* .. ==> 0XF8000744[1:1] = 0x00000001U */
  6737. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6738. /* .. L1_SEL = 0 */
  6739. /* .. ==> 0XF8000744[2:2] = 0x00000000U */
  6740. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6741. /* .. L2_SEL = 0 */
  6742. /* .. ==> 0XF8000744[4:3] = 0x00000000U */
  6743. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6744. /* .. L3_SEL = 0 */
  6745. /* .. ==> 0XF8000744[7:5] = 0x00000000U */
  6746. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6747. /* .. Speed = 1 */
  6748. /* .. ==> 0XF8000744[8:8] = 0x00000001U */
  6749. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6750. /* .. IO_Type = 4 */
  6751. /* .. ==> 0XF8000744[11:9] = 0x00000004U */
  6752. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6753. /* .. PULLUP = 0 */
  6754. /* .. ==> 0XF8000744[12:12] = 0x00000000U */
  6755. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6756. /* .. DisableRcvr = 1 */
  6757. /* .. ==> 0XF8000744[13:13] = 0x00000001U */
  6758. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  6759. /* .. */
  6760. EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
  6761. /* .. TRI_ENABLE = 0 */
  6762. /* .. ==> 0XF8000748[0:0] = 0x00000000U */
  6763. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6764. /* .. L0_SEL = 1 */
  6765. /* .. ==> 0XF8000748[1:1] = 0x00000001U */
  6766. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6767. /* .. L1_SEL = 0 */
  6768. /* .. ==> 0XF8000748[2:2] = 0x00000000U */
  6769. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6770. /* .. L2_SEL = 0 */
  6771. /* .. ==> 0XF8000748[4:3] = 0x00000000U */
  6772. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6773. /* .. L3_SEL = 0 */
  6774. /* .. ==> 0XF8000748[7:5] = 0x00000000U */
  6775. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6776. /* .. Speed = 1 */
  6777. /* .. ==> 0XF8000748[8:8] = 0x00000001U */
  6778. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6779. /* .. IO_Type = 4 */
  6780. /* .. ==> 0XF8000748[11:9] = 0x00000004U */
  6781. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6782. /* .. PULLUP = 0 */
  6783. /* .. ==> 0XF8000748[12:12] = 0x00000000U */
  6784. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6785. /* .. DisableRcvr = 1 */
  6786. /* .. ==> 0XF8000748[13:13] = 0x00000001U */
  6787. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  6788. /* .. */
  6789. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
  6790. /* .. TRI_ENABLE = 0 */
  6791. /* .. ==> 0XF800074C[0:0] = 0x00000000U */
  6792. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6793. /* .. L0_SEL = 1 */
  6794. /* .. ==> 0XF800074C[1:1] = 0x00000001U */
  6795. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6796. /* .. L1_SEL = 0 */
  6797. /* .. ==> 0XF800074C[2:2] = 0x00000000U */
  6798. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6799. /* .. L2_SEL = 0 */
  6800. /* .. ==> 0XF800074C[4:3] = 0x00000000U */
  6801. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6802. /* .. L3_SEL = 0 */
  6803. /* .. ==> 0XF800074C[7:5] = 0x00000000U */
  6804. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6805. /* .. Speed = 1 */
  6806. /* .. ==> 0XF800074C[8:8] = 0x00000001U */
  6807. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6808. /* .. IO_Type = 4 */
  6809. /* .. ==> 0XF800074C[11:9] = 0x00000004U */
  6810. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6811. /* .. PULLUP = 0 */
  6812. /* .. ==> 0XF800074C[12:12] = 0x00000000U */
  6813. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6814. /* .. DisableRcvr = 1 */
  6815. /* .. ==> 0XF800074C[13:13] = 0x00000001U */
  6816. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  6817. /* .. */
  6818. EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
  6819. /* .. TRI_ENABLE = 0 */
  6820. /* .. ==> 0XF8000750[0:0] = 0x00000000U */
  6821. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6822. /* .. L0_SEL = 1 */
  6823. /* .. ==> 0XF8000750[1:1] = 0x00000001U */
  6824. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6825. /* .. L1_SEL = 0 */
  6826. /* .. ==> 0XF8000750[2:2] = 0x00000000U */
  6827. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6828. /* .. L2_SEL = 0 */
  6829. /* .. ==> 0XF8000750[4:3] = 0x00000000U */
  6830. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6831. /* .. L3_SEL = 0 */
  6832. /* .. ==> 0XF8000750[7:5] = 0x00000000U */
  6833. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6834. /* .. Speed = 1 */
  6835. /* .. ==> 0XF8000750[8:8] = 0x00000001U */
  6836. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6837. /* .. IO_Type = 4 */
  6838. /* .. ==> 0XF8000750[11:9] = 0x00000004U */
  6839. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6840. /* .. PULLUP = 0 */
  6841. /* .. ==> 0XF8000750[12:12] = 0x00000000U */
  6842. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6843. /* .. DisableRcvr = 1 */
  6844. /* .. ==> 0XF8000750[13:13] = 0x00000001U */
  6845. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  6846. /* .. */
  6847. EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
  6848. /* .. TRI_ENABLE = 0 */
  6849. /* .. ==> 0XF8000754[0:0] = 0x00000000U */
  6850. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  6851. /* .. L0_SEL = 1 */
  6852. /* .. ==> 0XF8000754[1:1] = 0x00000001U */
  6853. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6854. /* .. L1_SEL = 0 */
  6855. /* .. ==> 0XF8000754[2:2] = 0x00000000U */
  6856. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6857. /* .. L2_SEL = 0 */
  6858. /* .. ==> 0XF8000754[4:3] = 0x00000000U */
  6859. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6860. /* .. L3_SEL = 0 */
  6861. /* .. ==> 0XF8000754[7:5] = 0x00000000U */
  6862. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6863. /* .. Speed = 1 */
  6864. /* .. ==> 0XF8000754[8:8] = 0x00000001U */
  6865. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6866. /* .. IO_Type = 4 */
  6867. /* .. ==> 0XF8000754[11:9] = 0x00000004U */
  6868. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6869. /* .. PULLUP = 0 */
  6870. /* .. ==> 0XF8000754[12:12] = 0x00000000U */
  6871. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6872. /* .. DisableRcvr = 1 */
  6873. /* .. ==> 0XF8000754[13:13] = 0x00000001U */
  6874. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  6875. /* .. */
  6876. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
  6877. /* .. TRI_ENABLE = 1 */
  6878. /* .. ==> 0XF8000758[0:0] = 0x00000001U */
  6879. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  6880. /* .. L0_SEL = 1 */
  6881. /* .. ==> 0XF8000758[1:1] = 0x00000001U */
  6882. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6883. /* .. L1_SEL = 0 */
  6884. /* .. ==> 0XF8000758[2:2] = 0x00000000U */
  6885. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6886. /* .. L2_SEL = 0 */
  6887. /* .. ==> 0XF8000758[4:3] = 0x00000000U */
  6888. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6889. /* .. L3_SEL = 0 */
  6890. /* .. ==> 0XF8000758[7:5] = 0x00000000U */
  6891. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6892. /* .. Speed = 1 */
  6893. /* .. ==> 0XF8000758[8:8] = 0x00000001U */
  6894. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6895. /* .. IO_Type = 4 */
  6896. /* .. ==> 0XF8000758[11:9] = 0x00000004U */
  6897. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6898. /* .. PULLUP = 0 */
  6899. /* .. ==> 0XF8000758[12:12] = 0x00000000U */
  6900. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6901. /* .. DisableRcvr = 0 */
  6902. /* .. ==> 0XF8000758[13:13] = 0x00000000U */
  6903. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6904. /* .. */
  6905. EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
  6906. /* .. TRI_ENABLE = 1 */
  6907. /* .. ==> 0XF800075C[0:0] = 0x00000001U */
  6908. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  6909. /* .. L0_SEL = 1 */
  6910. /* .. ==> 0XF800075C[1:1] = 0x00000001U */
  6911. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6912. /* .. L1_SEL = 0 */
  6913. /* .. ==> 0XF800075C[2:2] = 0x00000000U */
  6914. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6915. /* .. L2_SEL = 0 */
  6916. /* .. ==> 0XF800075C[4:3] = 0x00000000U */
  6917. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6918. /* .. L3_SEL = 0 */
  6919. /* .. ==> 0XF800075C[7:5] = 0x00000000U */
  6920. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6921. /* .. Speed = 1 */
  6922. /* .. ==> 0XF800075C[8:8] = 0x00000001U */
  6923. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6924. /* .. IO_Type = 4 */
  6925. /* .. ==> 0XF800075C[11:9] = 0x00000004U */
  6926. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6927. /* .. PULLUP = 0 */
  6928. /* .. ==> 0XF800075C[12:12] = 0x00000000U */
  6929. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6930. /* .. DisableRcvr = 0 */
  6931. /* .. ==> 0XF800075C[13:13] = 0x00000000U */
  6932. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6933. /* .. */
  6934. EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
  6935. /* .. TRI_ENABLE = 1 */
  6936. /* .. ==> 0XF8000760[0:0] = 0x00000001U */
  6937. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  6938. /* .. L0_SEL = 1 */
  6939. /* .. ==> 0XF8000760[1:1] = 0x00000001U */
  6940. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6941. /* .. L1_SEL = 0 */
  6942. /* .. ==> 0XF8000760[2:2] = 0x00000000U */
  6943. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6944. /* .. L2_SEL = 0 */
  6945. /* .. ==> 0XF8000760[4:3] = 0x00000000U */
  6946. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6947. /* .. L3_SEL = 0 */
  6948. /* .. ==> 0XF8000760[7:5] = 0x00000000U */
  6949. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6950. /* .. Speed = 1 */
  6951. /* .. ==> 0XF8000760[8:8] = 0x00000001U */
  6952. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6953. /* .. IO_Type = 4 */
  6954. /* .. ==> 0XF8000760[11:9] = 0x00000004U */
  6955. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6956. /* .. PULLUP = 0 */
  6957. /* .. ==> 0XF8000760[12:12] = 0x00000000U */
  6958. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6959. /* .. DisableRcvr = 0 */
  6960. /* .. ==> 0XF8000760[13:13] = 0x00000000U */
  6961. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6962. /* .. */
  6963. EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
  6964. /* .. TRI_ENABLE = 1 */
  6965. /* .. ==> 0XF8000764[0:0] = 0x00000001U */
  6966. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  6967. /* .. L0_SEL = 1 */
  6968. /* .. ==> 0XF8000764[1:1] = 0x00000001U */
  6969. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6970. /* .. L1_SEL = 0 */
  6971. /* .. ==> 0XF8000764[2:2] = 0x00000000U */
  6972. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  6973. /* .. L2_SEL = 0 */
  6974. /* .. ==> 0XF8000764[4:3] = 0x00000000U */
  6975. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  6976. /* .. L3_SEL = 0 */
  6977. /* .. ==> 0XF8000764[7:5] = 0x00000000U */
  6978. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  6979. /* .. Speed = 1 */
  6980. /* .. ==> 0XF8000764[8:8] = 0x00000001U */
  6981. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  6982. /* .. IO_Type = 4 */
  6983. /* .. ==> 0XF8000764[11:9] = 0x00000004U */
  6984. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  6985. /* .. PULLUP = 0 */
  6986. /* .. ==> 0XF8000764[12:12] = 0x00000000U */
  6987. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  6988. /* .. DisableRcvr = 0 */
  6989. /* .. ==> 0XF8000764[13:13] = 0x00000000U */
  6990. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  6991. /* .. */
  6992. EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
  6993. /* .. TRI_ENABLE = 1 */
  6994. /* .. ==> 0XF8000768[0:0] = 0x00000001U */
  6995. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  6996. /* .. L0_SEL = 1 */
  6997. /* .. ==> 0XF8000768[1:1] = 0x00000001U */
  6998. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  6999. /* .. L1_SEL = 0 */
  7000. /* .. ==> 0XF8000768[2:2] = 0x00000000U */
  7001. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7002. /* .. L2_SEL = 0 */
  7003. /* .. ==> 0XF8000768[4:3] = 0x00000000U */
  7004. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7005. /* .. L3_SEL = 0 */
  7006. /* .. ==> 0XF8000768[7:5] = 0x00000000U */
  7007. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7008. /* .. Speed = 1 */
  7009. /* .. ==> 0XF8000768[8:8] = 0x00000001U */
  7010. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7011. /* .. IO_Type = 4 */
  7012. /* .. ==> 0XF8000768[11:9] = 0x00000004U */
  7013. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  7014. /* .. PULLUP = 0 */
  7015. /* .. ==> 0XF8000768[12:12] = 0x00000000U */
  7016. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7017. /* .. DisableRcvr = 0 */
  7018. /* .. ==> 0XF8000768[13:13] = 0x00000000U */
  7019. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7020. /* .. */
  7021. EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
  7022. /* .. TRI_ENABLE = 1 */
  7023. /* .. ==> 0XF800076C[0:0] = 0x00000001U */
  7024. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  7025. /* .. L0_SEL = 1 */
  7026. /* .. ==> 0XF800076C[1:1] = 0x00000001U */
  7027. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  7028. /* .. L1_SEL = 0 */
  7029. /* .. ==> 0XF800076C[2:2] = 0x00000000U */
  7030. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7031. /* .. L2_SEL = 0 */
  7032. /* .. ==> 0XF800076C[4:3] = 0x00000000U */
  7033. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7034. /* .. L3_SEL = 0 */
  7035. /* .. ==> 0XF800076C[7:5] = 0x00000000U */
  7036. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7037. /* .. Speed = 1 */
  7038. /* .. ==> 0XF800076C[8:8] = 0x00000001U */
  7039. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7040. /* .. IO_Type = 4 */
  7041. /* .. ==> 0XF800076C[11:9] = 0x00000004U */
  7042. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  7043. /* .. PULLUP = 0 */
  7044. /* .. ==> 0XF800076C[12:12] = 0x00000000U */
  7045. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7046. /* .. DisableRcvr = 0 */
  7047. /* .. ==> 0XF800076C[13:13] = 0x00000000U */
  7048. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7049. /* .. */
  7050. EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
  7051. /* .. TRI_ENABLE = 0 */
  7052. /* .. ==> 0XF8000770[0:0] = 0x00000000U */
  7053. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7054. /* .. L0_SEL = 0 */
  7055. /* .. ==> 0XF8000770[1:1] = 0x00000000U */
  7056. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7057. /* .. L1_SEL = 1 */
  7058. /* .. ==> 0XF8000770[2:2] = 0x00000001U */
  7059. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7060. /* .. L2_SEL = 0 */
  7061. /* .. ==> 0XF8000770[4:3] = 0x00000000U */
  7062. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7063. /* .. L3_SEL = 0 */
  7064. /* .. ==> 0XF8000770[7:5] = 0x00000000U */
  7065. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7066. /* .. Speed = 1 */
  7067. /* .. ==> 0XF8000770[8:8] = 0x00000001U */
  7068. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7069. /* .. IO_Type = 1 */
  7070. /* .. ==> 0XF8000770[11:9] = 0x00000001U */
  7071. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7072. /* .. PULLUP = 0 */
  7073. /* .. ==> 0XF8000770[12:12] = 0x00000000U */
  7074. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7075. /* .. DisableRcvr = 0 */
  7076. /* .. ==> 0XF8000770[13:13] = 0x00000000U */
  7077. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7078. /* .. */
  7079. EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
  7080. /* .. TRI_ENABLE = 1 */
  7081. /* .. ==> 0XF8000774[0:0] = 0x00000001U */
  7082. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  7083. /* .. L0_SEL = 0 */
  7084. /* .. ==> 0XF8000774[1:1] = 0x00000000U */
  7085. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7086. /* .. L1_SEL = 1 */
  7087. /* .. ==> 0XF8000774[2:2] = 0x00000001U */
  7088. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7089. /* .. L2_SEL = 0 */
  7090. /* .. ==> 0XF8000774[4:3] = 0x00000000U */
  7091. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7092. /* .. L3_SEL = 0 */
  7093. /* .. ==> 0XF8000774[7:5] = 0x00000000U */
  7094. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7095. /* .. Speed = 1 */
  7096. /* .. ==> 0XF8000774[8:8] = 0x00000001U */
  7097. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7098. /* .. IO_Type = 1 */
  7099. /* .. ==> 0XF8000774[11:9] = 0x00000001U */
  7100. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7101. /* .. PULLUP = 0 */
  7102. /* .. ==> 0XF8000774[12:12] = 0x00000000U */
  7103. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7104. /* .. DisableRcvr = 0 */
  7105. /* .. ==> 0XF8000774[13:13] = 0x00000000U */
  7106. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7107. /* .. */
  7108. EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
  7109. /* .. TRI_ENABLE = 0 */
  7110. /* .. ==> 0XF8000778[0:0] = 0x00000000U */
  7111. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7112. /* .. L0_SEL = 0 */
  7113. /* .. ==> 0XF8000778[1:1] = 0x00000000U */
  7114. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7115. /* .. L1_SEL = 1 */
  7116. /* .. ==> 0XF8000778[2:2] = 0x00000001U */
  7117. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7118. /* .. L2_SEL = 0 */
  7119. /* .. ==> 0XF8000778[4:3] = 0x00000000U */
  7120. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7121. /* .. L3_SEL = 0 */
  7122. /* .. ==> 0XF8000778[7:5] = 0x00000000U */
  7123. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7124. /* .. Speed = 1 */
  7125. /* .. ==> 0XF8000778[8:8] = 0x00000001U */
  7126. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7127. /* .. IO_Type = 1 */
  7128. /* .. ==> 0XF8000778[11:9] = 0x00000001U */
  7129. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7130. /* .. PULLUP = 0 */
  7131. /* .. ==> 0XF8000778[12:12] = 0x00000000U */
  7132. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7133. /* .. DisableRcvr = 0 */
  7134. /* .. ==> 0XF8000778[13:13] = 0x00000000U */
  7135. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7136. /* .. */
  7137. EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
  7138. /* .. TRI_ENABLE = 1 */
  7139. /* .. ==> 0XF800077C[0:0] = 0x00000001U */
  7140. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  7141. /* .. L0_SEL = 0 */
  7142. /* .. ==> 0XF800077C[1:1] = 0x00000000U */
  7143. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7144. /* .. L1_SEL = 1 */
  7145. /* .. ==> 0XF800077C[2:2] = 0x00000001U */
  7146. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7147. /* .. L2_SEL = 0 */
  7148. /* .. ==> 0XF800077C[4:3] = 0x00000000U */
  7149. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7150. /* .. L3_SEL = 0 */
  7151. /* .. ==> 0XF800077C[7:5] = 0x00000000U */
  7152. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7153. /* .. Speed = 1 */
  7154. /* .. ==> 0XF800077C[8:8] = 0x00000001U */
  7155. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7156. /* .. IO_Type = 1 */
  7157. /* .. ==> 0XF800077C[11:9] = 0x00000001U */
  7158. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7159. /* .. PULLUP = 0 */
  7160. /* .. ==> 0XF800077C[12:12] = 0x00000000U */
  7161. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7162. /* .. DisableRcvr = 0 */
  7163. /* .. ==> 0XF800077C[13:13] = 0x00000000U */
  7164. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7165. /* .. */
  7166. EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
  7167. /* .. TRI_ENABLE = 0 */
  7168. /* .. ==> 0XF8000780[0:0] = 0x00000000U */
  7169. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7170. /* .. L0_SEL = 0 */
  7171. /* .. ==> 0XF8000780[1:1] = 0x00000000U */
  7172. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7173. /* .. L1_SEL = 1 */
  7174. /* .. ==> 0XF8000780[2:2] = 0x00000001U */
  7175. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7176. /* .. L2_SEL = 0 */
  7177. /* .. ==> 0XF8000780[4:3] = 0x00000000U */
  7178. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7179. /* .. L3_SEL = 0 */
  7180. /* .. ==> 0XF8000780[7:5] = 0x00000000U */
  7181. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7182. /* .. Speed = 1 */
  7183. /* .. ==> 0XF8000780[8:8] = 0x00000001U */
  7184. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7185. /* .. IO_Type = 1 */
  7186. /* .. ==> 0XF8000780[11:9] = 0x00000001U */
  7187. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7188. /* .. PULLUP = 0 */
  7189. /* .. ==> 0XF8000780[12:12] = 0x00000000U */
  7190. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7191. /* .. DisableRcvr = 0 */
  7192. /* .. ==> 0XF8000780[13:13] = 0x00000000U */
  7193. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7194. /* .. */
  7195. EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
  7196. /* .. TRI_ENABLE = 0 */
  7197. /* .. ==> 0XF8000784[0:0] = 0x00000000U */
  7198. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7199. /* .. L0_SEL = 0 */
  7200. /* .. ==> 0XF8000784[1:1] = 0x00000000U */
  7201. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7202. /* .. L1_SEL = 1 */
  7203. /* .. ==> 0XF8000784[2:2] = 0x00000001U */
  7204. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7205. /* .. L2_SEL = 0 */
  7206. /* .. ==> 0XF8000784[4:3] = 0x00000000U */
  7207. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7208. /* .. L3_SEL = 0 */
  7209. /* .. ==> 0XF8000784[7:5] = 0x00000000U */
  7210. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7211. /* .. Speed = 1 */
  7212. /* .. ==> 0XF8000784[8:8] = 0x00000001U */
  7213. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7214. /* .. IO_Type = 1 */
  7215. /* .. ==> 0XF8000784[11:9] = 0x00000001U */
  7216. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7217. /* .. PULLUP = 0 */
  7218. /* .. ==> 0XF8000784[12:12] = 0x00000000U */
  7219. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7220. /* .. DisableRcvr = 0 */
  7221. /* .. ==> 0XF8000784[13:13] = 0x00000000U */
  7222. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7223. /* .. */
  7224. EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
  7225. /* .. TRI_ENABLE = 0 */
  7226. /* .. ==> 0XF8000788[0:0] = 0x00000000U */
  7227. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7228. /* .. L0_SEL = 0 */
  7229. /* .. ==> 0XF8000788[1:1] = 0x00000000U */
  7230. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7231. /* .. L1_SEL = 1 */
  7232. /* .. ==> 0XF8000788[2:2] = 0x00000001U */
  7233. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7234. /* .. L2_SEL = 0 */
  7235. /* .. ==> 0XF8000788[4:3] = 0x00000000U */
  7236. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7237. /* .. L3_SEL = 0 */
  7238. /* .. ==> 0XF8000788[7:5] = 0x00000000U */
  7239. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7240. /* .. Speed = 1 */
  7241. /* .. ==> 0XF8000788[8:8] = 0x00000001U */
  7242. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7243. /* .. IO_Type = 1 */
  7244. /* .. ==> 0XF8000788[11:9] = 0x00000001U */
  7245. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7246. /* .. PULLUP = 0 */
  7247. /* .. ==> 0XF8000788[12:12] = 0x00000000U */
  7248. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7249. /* .. DisableRcvr = 0 */
  7250. /* .. ==> 0XF8000788[13:13] = 0x00000000U */
  7251. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7252. /* .. */
  7253. EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
  7254. /* .. TRI_ENABLE = 0 */
  7255. /* .. ==> 0XF800078C[0:0] = 0x00000000U */
  7256. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7257. /* .. L0_SEL = 0 */
  7258. /* .. ==> 0XF800078C[1:1] = 0x00000000U */
  7259. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7260. /* .. L1_SEL = 1 */
  7261. /* .. ==> 0XF800078C[2:2] = 0x00000001U */
  7262. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7263. /* .. L2_SEL = 0 */
  7264. /* .. ==> 0XF800078C[4:3] = 0x00000000U */
  7265. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7266. /* .. L3_SEL = 0 */
  7267. /* .. ==> 0XF800078C[7:5] = 0x00000000U */
  7268. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7269. /* .. Speed = 1 */
  7270. /* .. ==> 0XF800078C[8:8] = 0x00000001U */
  7271. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7272. /* .. IO_Type = 1 */
  7273. /* .. ==> 0XF800078C[11:9] = 0x00000001U */
  7274. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7275. /* .. PULLUP = 0 */
  7276. /* .. ==> 0XF800078C[12:12] = 0x00000000U */
  7277. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7278. /* .. DisableRcvr = 0 */
  7279. /* .. ==> 0XF800078C[13:13] = 0x00000000U */
  7280. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7281. /* .. */
  7282. EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
  7283. /* .. TRI_ENABLE = 1 */
  7284. /* .. ==> 0XF8000790[0:0] = 0x00000001U */
  7285. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  7286. /* .. L0_SEL = 0 */
  7287. /* .. ==> 0XF8000790[1:1] = 0x00000000U */
  7288. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7289. /* .. L1_SEL = 1 */
  7290. /* .. ==> 0XF8000790[2:2] = 0x00000001U */
  7291. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7292. /* .. L2_SEL = 0 */
  7293. /* .. ==> 0XF8000790[4:3] = 0x00000000U */
  7294. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7295. /* .. L3_SEL = 0 */
  7296. /* .. ==> 0XF8000790[7:5] = 0x00000000U */
  7297. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7298. /* .. Speed = 1 */
  7299. /* .. ==> 0XF8000790[8:8] = 0x00000001U */
  7300. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7301. /* .. IO_Type = 1 */
  7302. /* .. ==> 0XF8000790[11:9] = 0x00000001U */
  7303. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7304. /* .. PULLUP = 0 */
  7305. /* .. ==> 0XF8000790[12:12] = 0x00000000U */
  7306. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7307. /* .. DisableRcvr = 0 */
  7308. /* .. ==> 0XF8000790[13:13] = 0x00000000U */
  7309. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7310. /* .. */
  7311. EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
  7312. /* .. TRI_ENABLE = 0 */
  7313. /* .. ==> 0XF8000794[0:0] = 0x00000000U */
  7314. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7315. /* .. L0_SEL = 0 */
  7316. /* .. ==> 0XF8000794[1:1] = 0x00000000U */
  7317. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7318. /* .. L1_SEL = 1 */
  7319. /* .. ==> 0XF8000794[2:2] = 0x00000001U */
  7320. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7321. /* .. L2_SEL = 0 */
  7322. /* .. ==> 0XF8000794[4:3] = 0x00000000U */
  7323. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7324. /* .. L3_SEL = 0 */
  7325. /* .. ==> 0XF8000794[7:5] = 0x00000000U */
  7326. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7327. /* .. Speed = 1 */
  7328. /* .. ==> 0XF8000794[8:8] = 0x00000001U */
  7329. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7330. /* .. IO_Type = 1 */
  7331. /* .. ==> 0XF8000794[11:9] = 0x00000001U */
  7332. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7333. /* .. PULLUP = 0 */
  7334. /* .. ==> 0XF8000794[12:12] = 0x00000000U */
  7335. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7336. /* .. DisableRcvr = 0 */
  7337. /* .. ==> 0XF8000794[13:13] = 0x00000000U */
  7338. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7339. /* .. */
  7340. EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
  7341. /* .. TRI_ENABLE = 0 */
  7342. /* .. ==> 0XF8000798[0:0] = 0x00000000U */
  7343. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7344. /* .. L0_SEL = 0 */
  7345. /* .. ==> 0XF8000798[1:1] = 0x00000000U */
  7346. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7347. /* .. L1_SEL = 1 */
  7348. /* .. ==> 0XF8000798[2:2] = 0x00000001U */
  7349. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7350. /* .. L2_SEL = 0 */
  7351. /* .. ==> 0XF8000798[4:3] = 0x00000000U */
  7352. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7353. /* .. L3_SEL = 0 */
  7354. /* .. ==> 0XF8000798[7:5] = 0x00000000U */
  7355. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7356. /* .. Speed = 1 */
  7357. /* .. ==> 0XF8000798[8:8] = 0x00000001U */
  7358. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7359. /* .. IO_Type = 1 */
  7360. /* .. ==> 0XF8000798[11:9] = 0x00000001U */
  7361. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7362. /* .. PULLUP = 0 */
  7363. /* .. ==> 0XF8000798[12:12] = 0x00000000U */
  7364. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7365. /* .. DisableRcvr = 0 */
  7366. /* .. ==> 0XF8000798[13:13] = 0x00000000U */
  7367. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7368. /* .. */
  7369. EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
  7370. /* .. TRI_ENABLE = 0 */
  7371. /* .. ==> 0XF800079C[0:0] = 0x00000000U */
  7372. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7373. /* .. L0_SEL = 0 */
  7374. /* .. ==> 0XF800079C[1:1] = 0x00000000U */
  7375. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7376. /* .. L1_SEL = 1 */
  7377. /* .. ==> 0XF800079C[2:2] = 0x00000001U */
  7378. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  7379. /* .. L2_SEL = 0 */
  7380. /* .. ==> 0XF800079C[4:3] = 0x00000000U */
  7381. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7382. /* .. L3_SEL = 0 */
  7383. /* .. ==> 0XF800079C[7:5] = 0x00000000U */
  7384. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7385. /* .. Speed = 1 */
  7386. /* .. ==> 0XF800079C[8:8] = 0x00000001U */
  7387. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7388. /* .. IO_Type = 1 */
  7389. /* .. ==> 0XF800079C[11:9] = 0x00000001U */
  7390. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7391. /* .. PULLUP = 0 */
  7392. /* .. ==> 0XF800079C[12:12] = 0x00000000U */
  7393. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7394. /* .. DisableRcvr = 0 */
  7395. /* .. ==> 0XF800079C[13:13] = 0x00000000U */
  7396. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7397. /* .. */
  7398. EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
  7399. /* .. TRI_ENABLE = 0 */
  7400. /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
  7401. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7402. /* .. L0_SEL = 0 */
  7403. /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
  7404. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7405. /* .. L1_SEL = 0 */
  7406. /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
  7407. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7408. /* .. L2_SEL = 0 */
  7409. /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
  7410. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7411. /* .. L3_SEL = 4 */
  7412. /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
  7413. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7414. /* .. Speed = 1 */
  7415. /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
  7416. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7417. /* .. IO_Type = 1 */
  7418. /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
  7419. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7420. /* .. PULLUP = 0 */
  7421. /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
  7422. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7423. /* .. DisableRcvr = 0 */
  7424. /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
  7425. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7426. /* .. */
  7427. EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
  7428. /* .. TRI_ENABLE = 0 */
  7429. /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
  7430. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7431. /* .. L0_SEL = 0 */
  7432. /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
  7433. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7434. /* .. L1_SEL = 0 */
  7435. /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
  7436. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7437. /* .. L2_SEL = 0 */
  7438. /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
  7439. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7440. /* .. L3_SEL = 4 */
  7441. /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
  7442. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7443. /* .. Speed = 1 */
  7444. /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
  7445. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7446. /* .. IO_Type = 1 */
  7447. /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
  7448. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7449. /* .. PULLUP = 0 */
  7450. /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
  7451. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7452. /* .. DisableRcvr = 0 */
  7453. /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
  7454. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7455. /* .. */
  7456. EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
  7457. /* .. TRI_ENABLE = 0 */
  7458. /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
  7459. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7460. /* .. L0_SEL = 0 */
  7461. /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
  7462. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7463. /* .. L1_SEL = 0 */
  7464. /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
  7465. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7466. /* .. L2_SEL = 0 */
  7467. /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
  7468. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7469. /* .. L3_SEL = 4 */
  7470. /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
  7471. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7472. /* .. Speed = 1 */
  7473. /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
  7474. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7475. /* .. IO_Type = 1 */
  7476. /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
  7477. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7478. /* .. PULLUP = 0 */
  7479. /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
  7480. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7481. /* .. DisableRcvr = 0 */
  7482. /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
  7483. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7484. /* .. */
  7485. EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
  7486. /* .. TRI_ENABLE = 0 */
  7487. /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
  7488. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7489. /* .. L0_SEL = 0 */
  7490. /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
  7491. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7492. /* .. L1_SEL = 0 */
  7493. /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
  7494. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7495. /* .. L2_SEL = 0 */
  7496. /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
  7497. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7498. /* .. L3_SEL = 4 */
  7499. /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
  7500. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7501. /* .. Speed = 1 */
  7502. /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
  7503. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7504. /* .. IO_Type = 1 */
  7505. /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
  7506. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7507. /* .. PULLUP = 0 */
  7508. /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
  7509. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7510. /* .. DisableRcvr = 0 */
  7511. /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
  7512. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7513. /* .. */
  7514. EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
  7515. /* .. TRI_ENABLE = 0 */
  7516. /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
  7517. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7518. /* .. L0_SEL = 0 */
  7519. /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
  7520. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7521. /* .. L1_SEL = 0 */
  7522. /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
  7523. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7524. /* .. L2_SEL = 0 */
  7525. /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
  7526. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7527. /* .. L3_SEL = 4 */
  7528. /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
  7529. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7530. /* .. Speed = 1 */
  7531. /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
  7532. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7533. /* .. IO_Type = 1 */
  7534. /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
  7535. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7536. /* .. PULLUP = 0 */
  7537. /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
  7538. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7539. /* .. DisableRcvr = 0 */
  7540. /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
  7541. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7542. /* .. */
  7543. EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
  7544. /* .. TRI_ENABLE = 0 */
  7545. /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
  7546. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7547. /* .. L0_SEL = 0 */
  7548. /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
  7549. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7550. /* .. L1_SEL = 0 */
  7551. /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
  7552. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7553. /* .. L2_SEL = 0 */
  7554. /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
  7555. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7556. /* .. L3_SEL = 4 */
  7557. /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
  7558. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7559. /* .. Speed = 1 */
  7560. /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
  7561. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7562. /* .. IO_Type = 1 */
  7563. /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
  7564. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7565. /* .. PULLUP = 0 */
  7566. /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
  7567. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7568. /* .. DisableRcvr = 0 */
  7569. /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
  7570. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7571. /* .. */
  7572. EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
  7573. /* .. TRI_ENABLE = 0 */
  7574. /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
  7575. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7576. /* .. L0_SEL = 0 */
  7577. /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
  7578. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7579. /* .. L1_SEL = 0 */
  7580. /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
  7581. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7582. /* .. L2_SEL = 0 */
  7583. /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
  7584. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7585. /* .. L3_SEL = 0 */
  7586. /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
  7587. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7588. /* .. Speed = 0 */
  7589. /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
  7590. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7591. /* .. IO_Type = 1 */
  7592. /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
  7593. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7594. /* .. PULLUP = 1 */
  7595. /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
  7596. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  7597. /* .. DisableRcvr = 0 */
  7598. /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
  7599. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7600. /* .. */
  7601. EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
  7602. /* .. TRI_ENABLE = 1 */
  7603. /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
  7604. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  7605. /* .. Speed = 0 */
  7606. /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
  7607. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7608. /* .. IO_Type = 1 */
  7609. /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
  7610. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7611. /* .. PULLUP = 0 */
  7612. /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
  7613. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7614. /* .. DisableRcvr = 0 */
  7615. /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
  7616. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7617. /* .. */
  7618. EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
  7619. /* .. TRI_ENABLE = 0 */
  7620. /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
  7621. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7622. /* .. L0_SEL = 0 */
  7623. /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
  7624. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7625. /* .. L1_SEL = 0 */
  7626. /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
  7627. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7628. /* .. L2_SEL = 0 */
  7629. /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
  7630. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7631. /* .. L3_SEL = 7 */
  7632. /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
  7633. /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
  7634. /* .. Speed = 0 */
  7635. /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
  7636. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7637. /* .. IO_Type = 1 */
  7638. /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
  7639. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7640. /* .. PULLUP = 0 */
  7641. /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
  7642. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7643. /* .. DisableRcvr = 0 */
  7644. /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
  7645. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7646. /* .. */
  7647. EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
  7648. /* .. TRI_ENABLE = 1 */
  7649. /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
  7650. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  7651. /* .. L0_SEL = 0 */
  7652. /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
  7653. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7654. /* .. L1_SEL = 0 */
  7655. /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
  7656. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7657. /* .. L2_SEL = 0 */
  7658. /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
  7659. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7660. /* .. L3_SEL = 7 */
  7661. /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
  7662. /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
  7663. /* .. Speed = 0 */
  7664. /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
  7665. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7666. /* .. IO_Type = 1 */
  7667. /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
  7668. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7669. /* .. PULLUP = 0 */
  7670. /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
  7671. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7672. /* .. DisableRcvr = 0 */
  7673. /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
  7674. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7675. /* .. */
  7676. EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
  7677. /* .. TRI_ENABLE = 0 */
  7678. /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
  7679. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7680. /* .. L0_SEL = 0 */
  7681. /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
  7682. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7683. /* .. L1_SEL = 0 */
  7684. /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
  7685. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7686. /* .. L2_SEL = 0 */
  7687. /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
  7688. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7689. /* .. L3_SEL = 0 */
  7690. /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
  7691. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7692. /* .. Speed = 0 */
  7693. /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
  7694. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7695. /* .. IO_Type = 1 */
  7696. /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
  7697. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7698. /* .. PULLUP = 0 */
  7699. /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
  7700. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7701. /* .. DisableRcvr = 0 */
  7702. /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
  7703. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7704. /* .. */
  7705. EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
  7706. /* .. TRI_ENABLE = 0 */
  7707. /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
  7708. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7709. /* .. L0_SEL = 0 */
  7710. /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
  7711. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7712. /* .. L1_SEL = 0 */
  7713. /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
  7714. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7715. /* .. L2_SEL = 0 */
  7716. /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
  7717. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7718. /* .. L3_SEL = 0 */
  7719. /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
  7720. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  7721. /* .. Speed = 0 */
  7722. /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
  7723. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7724. /* .. IO_Type = 1 */
  7725. /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
  7726. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7727. /* .. PULLUP = 0 */
  7728. /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
  7729. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7730. /* .. DisableRcvr = 0 */
  7731. /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
  7732. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7733. /* .. */
  7734. EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
  7735. /* .. TRI_ENABLE = 0 */
  7736. /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
  7737. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7738. /* .. L0_SEL = 0 */
  7739. /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
  7740. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7741. /* .. L1_SEL = 0 */
  7742. /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
  7743. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7744. /* .. L2_SEL = 0 */
  7745. /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
  7746. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7747. /* .. L3_SEL = 4 */
  7748. /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
  7749. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7750. /* .. Speed = 0 */
  7751. /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
  7752. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7753. /* .. IO_Type = 1 */
  7754. /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
  7755. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7756. /* .. PULLUP = 0 */
  7757. /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
  7758. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7759. /* .. DisableRcvr = 0 */
  7760. /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
  7761. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7762. /* .. */
  7763. EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
  7764. /* .. TRI_ENABLE = 0 */
  7765. /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
  7766. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  7767. /* .. L0_SEL = 0 */
  7768. /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
  7769. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  7770. /* .. L1_SEL = 0 */
  7771. /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
  7772. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  7773. /* .. L2_SEL = 0 */
  7774. /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
  7775. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  7776. /* .. L3_SEL = 4 */
  7777. /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
  7778. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  7779. /* .. Speed = 0 */
  7780. /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
  7781. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  7782. /* .. IO_Type = 1 */
  7783. /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
  7784. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  7785. /* .. PULLUP = 0 */
  7786. /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
  7787. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  7788. /* .. DisableRcvr = 0 */
  7789. /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
  7790. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  7791. /* .. */
  7792. EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
  7793. /* .. SDIO0_WP_SEL = 55 */
  7794. /* .. ==> 0XF8000830[5:0] = 0x00000037U */
  7795. /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
  7796. /* .. SDIO0_CD_SEL = 47 */
  7797. /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
  7798. /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
  7799. /* .. */
  7800. EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
  7801. /* .. FINISH: MIO PROGRAMMING */
  7802. /* .. START: LOCK IT BACK */
  7803. /* .. LOCK_KEY = 0X767B */
  7804. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  7805. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  7806. /* .. */
  7807. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  7808. /* .. FINISH: LOCK IT BACK */
  7809. /* FINISH: top */
  7810. /* */
  7811. EMIT_EXIT(),
  7812. /* */
  7813. };
  7814. unsigned long ps7_peripherals_init_data_2_0[] = {
  7815. /* START: top */
  7816. /* .. START: SLCR SETTINGS */
  7817. /* .. UNLOCK_KEY = 0XDF0D */
  7818. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  7819. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  7820. /* .. */
  7821. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  7822. /* .. FINISH: SLCR SETTINGS */
  7823. /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
  7824. /* .. IBUF_DISABLE_MODE = 0x1 */
  7825. /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
  7826. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  7827. /* .. TERM_DISABLE_MODE = 0x1 */
  7828. /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
  7829. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7830. /* .. */
  7831. EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
  7832. /* .. IBUF_DISABLE_MODE = 0x1 */
  7833. /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
  7834. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  7835. /* .. TERM_DISABLE_MODE = 0x1 */
  7836. /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
  7837. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7838. /* .. */
  7839. EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
  7840. /* .. IBUF_DISABLE_MODE = 0x1 */
  7841. /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
  7842. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  7843. /* .. TERM_DISABLE_MODE = 0x1 */
  7844. /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
  7845. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7846. /* .. */
  7847. EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
  7848. /* .. IBUF_DISABLE_MODE = 0x1 */
  7849. /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
  7850. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  7851. /* .. TERM_DISABLE_MODE = 0x1 */
  7852. /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
  7853. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  7854. /* .. */
  7855. EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
  7856. /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
  7857. /* .. START: LOCK IT BACK */
  7858. /* .. LOCK_KEY = 0X767B */
  7859. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  7860. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  7861. /* .. */
  7862. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  7863. /* .. FINISH: LOCK IT BACK */
  7864. /* .. START: SRAM/NOR SET OPMODE */
  7865. /* .. FINISH: SRAM/NOR SET OPMODE */
  7866. /* .. START: QSPI REGISTERS */
  7867. /* .. Holdb_dr = 1 */
  7868. /* .. ==> 0XE000D000[19:19] = 0x00000001U */
  7869. /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  7870. /* .. */
  7871. EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
  7872. /* .. FINISH: QSPI REGISTERS */
  7873. /* .. START: PL POWER ON RESET REGISTERS */
  7874. /* .. PCFG_POR_CNT_4K = 0 */
  7875. /* .. ==> 0XF8007000[29:29] = 0x00000000U */
  7876. /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
  7877. /* .. */
  7878. EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
  7879. /* .. FINISH: PL POWER ON RESET REGISTERS */
  7880. /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
  7881. /* .. .. START: NAND SET CYCLE */
  7882. /* .. .. FINISH: NAND SET CYCLE */
  7883. /* .. .. START: OPMODE */
  7884. /* .. .. FINISH: OPMODE */
  7885. /* .. .. START: DIRECT COMMAND */
  7886. /* .. .. FINISH: DIRECT COMMAND */
  7887. /* .. .. START: SRAM/NOR CS0 SET CYCLE */
  7888. /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
  7889. /* .. .. START: DIRECT COMMAND */
  7890. /* .. .. FINISH: DIRECT COMMAND */
  7891. /* .. .. START: NOR CS0 BASE ADDRESS */
  7892. /* .. .. FINISH: NOR CS0 BASE ADDRESS */
  7893. /* .. .. START: SRAM/NOR CS1 SET CYCLE */
  7894. /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
  7895. /* .. .. START: DIRECT COMMAND */
  7896. /* .. .. FINISH: DIRECT COMMAND */
  7897. /* .. .. START: NOR CS1 BASE ADDRESS */
  7898. /* .. .. FINISH: NOR CS1 BASE ADDRESS */
  7899. /* .. .. START: USB RESET */
  7900. /* .. .. .. START: USB0 RESET */
  7901. /* .. .. .. .. START: DIR MODE BANK 0 */
  7902. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  7903. /* .. .. .. .. START: DIR MODE BANK 1 */
  7904. /* .. .. .. .. DIRECTION_1 = 0x4000 */
  7905. /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
  7906. /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
  7907. /* .. .. .. .. */
  7908. EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
  7909. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  7910. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  7911. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  7912. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  7913. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  7914. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  7915. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  7916. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  7917. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  7918. /* .. .. .. .. DATA_1_LSW = 0x4000 */
  7919. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
  7920. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
  7921. /* .. .. .. .. */
  7922. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
  7923. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  7924. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  7925. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  7926. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  7927. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  7928. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  7929. /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
  7930. /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
  7931. /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
  7932. /* .. .. .. .. */
  7933. EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
  7934. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  7935. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  7936. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  7937. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  7938. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  7939. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  7940. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  7941. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  7942. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  7943. /* .. .. .. .. DATA_1_LSW = 0x0 */
  7944. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
  7945. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
  7946. /* .. .. .. .. */
  7947. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
  7948. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  7949. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  7950. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  7951. /* .. .. .. .. START: ADD 1 MS DELAY */
  7952. /* .. .. .. .. */
  7953. EMIT_MASKDELAY(0XF8F00200, 1),
  7954. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  7955. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  7956. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  7957. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  7958. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  7959. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  7960. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  7961. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  7962. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  7963. /* .. .. .. .. DATA_1_LSW = 0x4000 */
  7964. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
  7965. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
  7966. /* .. .. .. .. */
  7967. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
  7968. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  7969. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  7970. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  7971. /* .. .. .. FINISH: USB0 RESET */
  7972. /* .. .. .. START: USB1 RESET */
  7973. /* .. .. .. .. START: DIR MODE BANK 0 */
  7974. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  7975. /* .. .. .. .. START: DIR MODE BANK 1 */
  7976. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  7977. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  7978. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  7979. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  7980. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  7981. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  7982. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  7983. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  7984. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  7985. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  7986. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  7987. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  7988. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  7989. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  7990. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  7991. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  7992. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  7993. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  7994. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  7995. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  7996. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  7997. /* .. .. .. .. START: ADD 1 MS DELAY */
  7998. /* .. .. .. .. */
  7999. EMIT_MASKDELAY(0XF8F00200, 1),
  8000. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  8001. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8002. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8003. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8004. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8005. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8006. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8007. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8008. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8009. /* .. .. .. FINISH: USB1 RESET */
  8010. /* .. .. FINISH: USB RESET */
  8011. /* .. .. START: ENET RESET */
  8012. /* .. .. .. START: ENET0 RESET */
  8013. /* .. .. .. .. START: DIR MODE BANK 0 */
  8014. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  8015. /* .. .. .. .. START: DIR MODE BANK 1 */
  8016. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  8017. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8018. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8019. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8020. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8021. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8022. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8023. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8024. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8025. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  8026. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  8027. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  8028. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  8029. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  8030. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  8031. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  8032. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  8033. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  8034. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  8035. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  8036. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  8037. /* .. .. .. .. START: ADD 1 MS DELAY */
  8038. /* .. .. .. .. */
  8039. EMIT_MASKDELAY(0XF8F00200, 1),
  8040. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  8041. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8042. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8043. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8044. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8045. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8046. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8047. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8048. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8049. /* .. .. .. FINISH: ENET0 RESET */
  8050. /* .. .. .. START: ENET1 RESET */
  8051. /* .. .. .. .. START: DIR MODE BANK 0 */
  8052. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  8053. /* .. .. .. .. START: DIR MODE BANK 1 */
  8054. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  8055. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8056. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8057. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8058. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8059. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8060. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8061. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8062. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8063. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  8064. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  8065. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  8066. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  8067. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  8068. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  8069. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  8070. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  8071. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  8072. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  8073. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  8074. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  8075. /* .. .. .. .. START: ADD 1 MS DELAY */
  8076. /* .. .. .. .. */
  8077. EMIT_MASKDELAY(0XF8F00200, 1),
  8078. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  8079. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8080. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8081. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8082. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8083. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8084. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8085. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8086. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8087. /* .. .. .. FINISH: ENET1 RESET */
  8088. /* .. .. FINISH: ENET RESET */
  8089. /* .. .. START: I2C RESET */
  8090. /* .. .. .. START: I2C0 RESET */
  8091. /* .. .. .. .. START: DIR MODE GPIO BANK0 */
  8092. /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
  8093. /* .. .. .. .. START: DIR MODE GPIO BANK1 */
  8094. /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
  8095. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8096. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8097. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8098. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8099. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8100. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8101. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8102. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8103. /* .. .. .. .. START: OUTPUT ENABLE */
  8104. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  8105. /* .. .. .. .. START: OUTPUT ENABLE */
  8106. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  8107. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  8108. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  8109. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  8110. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  8111. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  8112. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  8113. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  8114. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  8115. /* .. .. .. .. START: ADD 1 MS DELAY */
  8116. /* .. .. .. .. */
  8117. EMIT_MASKDELAY(0XF8F00200, 1),
  8118. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  8119. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8120. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8121. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8122. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8123. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8124. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8125. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8126. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8127. /* .. .. .. FINISH: I2C0 RESET */
  8128. /* .. .. .. START: I2C1 RESET */
  8129. /* .. .. .. .. START: DIR MODE GPIO BANK0 */
  8130. /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
  8131. /* .. .. .. .. START: DIR MODE GPIO BANK1 */
  8132. /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
  8133. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8134. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8135. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8136. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8137. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8138. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8139. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8140. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8141. /* .. .. .. .. START: OUTPUT ENABLE */
  8142. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  8143. /* .. .. .. .. START: OUTPUT ENABLE */
  8144. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  8145. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  8146. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  8147. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  8148. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  8149. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  8150. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  8151. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  8152. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  8153. /* .. .. .. .. START: ADD 1 MS DELAY */
  8154. /* .. .. .. .. */
  8155. EMIT_MASKDELAY(0XF8F00200, 1),
  8156. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  8157. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8158. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8159. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8160. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  8161. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8162. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  8163. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8164. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  8165. /* .. .. .. FINISH: I2C1 RESET */
  8166. /* .. .. FINISH: I2C RESET */
  8167. /* .. .. START: NOR CHIP SELECT */
  8168. /* .. .. .. START: DIR MODE BANK 0 */
  8169. /* .. .. .. FINISH: DIR MODE BANK 0 */
  8170. /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8171. /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  8172. /* .. .. .. START: OUTPUT ENABLE BANK 0 */
  8173. /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  8174. /* .. .. FINISH: NOR CHIP SELECT */
  8175. /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
  8176. /* FINISH: top */
  8177. /* */
  8178. EMIT_EXIT(),
  8179. /* */
  8180. };
  8181. unsigned long ps7_post_config_2_0[] = {
  8182. /* START: top */
  8183. /* .. START: SLCR SETTINGS */
  8184. /* .. UNLOCK_KEY = 0XDF0D */
  8185. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  8186. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  8187. /* .. */
  8188. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  8189. /* .. FINISH: SLCR SETTINGS */
  8190. /* .. START: ENABLING LEVEL SHIFTER */
  8191. /* .. USER_INP_ICT_EN_0 = 3 */
  8192. /* .. ==> 0XF8000900[1:0] = 0x00000003U */
  8193. /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
  8194. /* .. USER_INP_ICT_EN_1 = 3 */
  8195. /* .. ==> 0XF8000900[3:2] = 0x00000003U */
  8196. /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
  8197. /* .. */
  8198. EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
  8199. /* .. FINISH: ENABLING LEVEL SHIFTER */
  8200. /* .. START: FPGA RESETS TO 0 */
  8201. /* .. reserved_3 = 0 */
  8202. /* .. ==> 0XF8000240[31:25] = 0x00000000U */
  8203. /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
  8204. /* .. FPGA_ACP_RST = 0 */
  8205. /* .. ==> 0XF8000240[24:24] = 0x00000000U */
  8206. /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  8207. /* .. FPGA_AXDS3_RST = 0 */
  8208. /* .. ==> 0XF8000240[23:23] = 0x00000000U */
  8209. /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  8210. /* .. FPGA_AXDS2_RST = 0 */
  8211. /* .. ==> 0XF8000240[22:22] = 0x00000000U */
  8212. /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  8213. /* .. FPGA_AXDS1_RST = 0 */
  8214. /* .. ==> 0XF8000240[21:21] = 0x00000000U */
  8215. /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  8216. /* .. FPGA_AXDS0_RST = 0 */
  8217. /* .. ==> 0XF8000240[20:20] = 0x00000000U */
  8218. /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  8219. /* .. reserved_2 = 0 */
  8220. /* .. ==> 0XF8000240[19:18] = 0x00000000U */
  8221. /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
  8222. /* .. FSSW1_FPGA_RST = 0 */
  8223. /* .. ==> 0XF8000240[17:17] = 0x00000000U */
  8224. /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  8225. /* .. FSSW0_FPGA_RST = 0 */
  8226. /* .. ==> 0XF8000240[16:16] = 0x00000000U */
  8227. /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  8228. /* .. reserved_1 = 0 */
  8229. /* .. ==> 0XF8000240[15:14] = 0x00000000U */
  8230. /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
  8231. /* .. FPGA_FMSW1_RST = 0 */
  8232. /* .. ==> 0XF8000240[13:13] = 0x00000000U */
  8233. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  8234. /* .. FPGA_FMSW0_RST = 0 */
  8235. /* .. ==> 0XF8000240[12:12] = 0x00000000U */
  8236. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  8237. /* .. FPGA_DMA3_RST = 0 */
  8238. /* .. ==> 0XF8000240[11:11] = 0x00000000U */
  8239. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  8240. /* .. FPGA_DMA2_RST = 0 */
  8241. /* .. ==> 0XF8000240[10:10] = 0x00000000U */
  8242. /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  8243. /* .. FPGA_DMA1_RST = 0 */
  8244. /* .. ==> 0XF8000240[9:9] = 0x00000000U */
  8245. /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  8246. /* .. FPGA_DMA0_RST = 0 */
  8247. /* .. ==> 0XF8000240[8:8] = 0x00000000U */
  8248. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  8249. /* .. reserved = 0 */
  8250. /* .. ==> 0XF8000240[7:4] = 0x00000000U */
  8251. /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  8252. /* .. FPGA3_OUT_RST = 0 */
  8253. /* .. ==> 0XF8000240[3:3] = 0x00000000U */
  8254. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  8255. /* .. FPGA2_OUT_RST = 0 */
  8256. /* .. ==> 0XF8000240[2:2] = 0x00000000U */
  8257. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  8258. /* .. FPGA1_OUT_RST = 0 */
  8259. /* .. ==> 0XF8000240[1:1] = 0x00000000U */
  8260. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  8261. /* .. FPGA0_OUT_RST = 0 */
  8262. /* .. ==> 0XF8000240[0:0] = 0x00000000U */
  8263. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8264. /* .. */
  8265. EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
  8266. /* .. FINISH: FPGA RESETS TO 0 */
  8267. /* .. START: AFI REGISTERS */
  8268. /* .. .. START: AFI0 REGISTERS */
  8269. /* .. .. FINISH: AFI0 REGISTERS */
  8270. /* .. .. START: AFI1 REGISTERS */
  8271. /* .. .. FINISH: AFI1 REGISTERS */
  8272. /* .. .. START: AFI2 REGISTERS */
  8273. /* .. .. FINISH: AFI2 REGISTERS */
  8274. /* .. .. START: AFI3 REGISTERS */
  8275. /* .. .. FINISH: AFI3 REGISTERS */
  8276. /* .. FINISH: AFI REGISTERS */
  8277. /* .. START: LOCK IT BACK */
  8278. /* .. LOCK_KEY = 0X767B */
  8279. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  8280. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  8281. /* .. */
  8282. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  8283. /* .. FINISH: LOCK IT BACK */
  8284. /* FINISH: top */
  8285. /* */
  8286. EMIT_EXIT(),
  8287. /* */
  8288. };
  8289. unsigned long ps7_pll_init_data_1_0[] = {
  8290. /* START: top */
  8291. /* .. START: SLCR SETTINGS */
  8292. /* .. UNLOCK_KEY = 0XDF0D */
  8293. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  8294. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  8295. /* .. */
  8296. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  8297. /* .. FINISH: SLCR SETTINGS */
  8298. /* .. START: PLL SLCR REGISTERS */
  8299. /* .. .. START: ARM PLL INIT */
  8300. /* .. .. PLL_RES = 0xc */
  8301. /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
  8302. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  8303. /* .. .. PLL_CP = 0x2 */
  8304. /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
  8305. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  8306. /* .. .. LOCK_CNT = 0x177 */
  8307. /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
  8308. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
  8309. /* .. .. */
  8310. EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
  8311. /* .. .. .. START: UPDATE FB_DIV */
  8312. /* .. .. .. PLL_FDIV = 0x1a */
  8313. /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
  8314. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
  8315. /* .. .. .. */
  8316. EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
  8317. /* .. .. .. FINISH: UPDATE FB_DIV */
  8318. /* .. .. .. START: BY PASS PLL */
  8319. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  8320. /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
  8321. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  8322. /* .. .. .. */
  8323. EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
  8324. /* .. .. .. FINISH: BY PASS PLL */
  8325. /* .. .. .. START: ASSERT RESET */
  8326. /* .. .. .. PLL_RESET = 1 */
  8327. /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
  8328. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8329. /* .. .. .. */
  8330. EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
  8331. /* .. .. .. FINISH: ASSERT RESET */
  8332. /* .. .. .. START: DEASSERT RESET */
  8333. /* .. .. .. PLL_RESET = 0 */
  8334. /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
  8335. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8336. /* .. .. .. */
  8337. EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
  8338. /* .. .. .. FINISH: DEASSERT RESET */
  8339. /* .. .. .. START: CHECK PLL STATUS */
  8340. /* .. .. .. ARM_PLL_LOCK = 1 */
  8341. /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
  8342. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8343. /* .. .. .. */
  8344. EMIT_MASKPOLL(0XF800010C, 0x00000001U),
  8345. /* .. .. .. FINISH: CHECK PLL STATUS */
  8346. /* .. .. .. START: REMOVE PLL BY PASS */
  8347. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  8348. /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
  8349. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  8350. /* .. .. .. */
  8351. EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
  8352. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  8353. /* .. .. .. SRCSEL = 0x0 */
  8354. /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
  8355. /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8356. /* .. .. .. DIVISOR = 0x2 */
  8357. /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
  8358. /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
  8359. /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
  8360. /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
  8361. /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
  8362. /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
  8363. /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
  8364. /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
  8365. /* .. .. .. CPU_2XCLKACT = 0x1 */
  8366. /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
  8367. /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
  8368. /* .. .. .. CPU_1XCLKACT = 0x1 */
  8369. /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
  8370. /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
  8371. /* .. .. .. CPU_PERI_CLKACT = 0x1 */
  8372. /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
  8373. /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  8374. /* .. .. .. */
  8375. EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
  8376. /* .. .. FINISH: ARM PLL INIT */
  8377. /* .. .. START: DDR PLL INIT */
  8378. /* .. .. PLL_RES = 0xc */
  8379. /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
  8380. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  8381. /* .. .. PLL_CP = 0x2 */
  8382. /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
  8383. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  8384. /* .. .. LOCK_CNT = 0x1db */
  8385. /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
  8386. /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
  8387. /* .. .. */
  8388. EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
  8389. /* .. .. .. START: UPDATE FB_DIV */
  8390. /* .. .. .. PLL_FDIV = 0x15 */
  8391. /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
  8392. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
  8393. /* .. .. .. */
  8394. EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
  8395. /* .. .. .. FINISH: UPDATE FB_DIV */
  8396. /* .. .. .. START: BY PASS PLL */
  8397. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  8398. /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
  8399. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  8400. /* .. .. .. */
  8401. EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
  8402. /* .. .. .. FINISH: BY PASS PLL */
  8403. /* .. .. .. START: ASSERT RESET */
  8404. /* .. .. .. PLL_RESET = 1 */
  8405. /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
  8406. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8407. /* .. .. .. */
  8408. EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
  8409. /* .. .. .. FINISH: ASSERT RESET */
  8410. /* .. .. .. START: DEASSERT RESET */
  8411. /* .. .. .. PLL_RESET = 0 */
  8412. /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
  8413. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8414. /* .. .. .. */
  8415. EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
  8416. /* .. .. .. FINISH: DEASSERT RESET */
  8417. /* .. .. .. START: CHECK PLL STATUS */
  8418. /* .. .. .. DDR_PLL_LOCK = 1 */
  8419. /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
  8420. /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  8421. /* .. .. .. */
  8422. EMIT_MASKPOLL(0XF800010C, 0x00000002U),
  8423. /* .. .. .. FINISH: CHECK PLL STATUS */
  8424. /* .. .. .. START: REMOVE PLL BY PASS */
  8425. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  8426. /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
  8427. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  8428. /* .. .. .. */
  8429. EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
  8430. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  8431. /* .. .. .. DDR_3XCLKACT = 0x1 */
  8432. /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
  8433. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8434. /* .. .. .. DDR_2XCLKACT = 0x1 */
  8435. /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
  8436. /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  8437. /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
  8438. /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
  8439. /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
  8440. /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
  8441. /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
  8442. /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
  8443. /* .. .. .. */
  8444. EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
  8445. /* .. .. FINISH: DDR PLL INIT */
  8446. /* .. .. START: IO PLL INIT */
  8447. /* .. .. PLL_RES = 0xc */
  8448. /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
  8449. /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
  8450. /* .. .. PLL_CP = 0x2 */
  8451. /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
  8452. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  8453. /* .. .. LOCK_CNT = 0x1f4 */
  8454. /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
  8455. /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
  8456. /* .. .. */
  8457. EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
  8458. /* .. .. .. START: UPDATE FB_DIV */
  8459. /* .. .. .. PLL_FDIV = 0x14 */
  8460. /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
  8461. /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
  8462. /* .. .. .. */
  8463. EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
  8464. /* .. .. .. FINISH: UPDATE FB_DIV */
  8465. /* .. .. .. START: BY PASS PLL */
  8466. /* .. .. .. PLL_BYPASS_FORCE = 1 */
  8467. /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
  8468. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  8469. /* .. .. .. */
  8470. EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
  8471. /* .. .. .. FINISH: BY PASS PLL */
  8472. /* .. .. .. START: ASSERT RESET */
  8473. /* .. .. .. PLL_RESET = 1 */
  8474. /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
  8475. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8476. /* .. .. .. */
  8477. EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
  8478. /* .. .. .. FINISH: ASSERT RESET */
  8479. /* .. .. .. START: DEASSERT RESET */
  8480. /* .. .. .. PLL_RESET = 0 */
  8481. /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
  8482. /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8483. /* .. .. .. */
  8484. EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
  8485. /* .. .. .. FINISH: DEASSERT RESET */
  8486. /* .. .. .. START: CHECK PLL STATUS */
  8487. /* .. .. .. IO_PLL_LOCK = 1 */
  8488. /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
  8489. /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  8490. /* .. .. .. */
  8491. EMIT_MASKPOLL(0XF800010C, 0x00000004U),
  8492. /* .. .. .. FINISH: CHECK PLL STATUS */
  8493. /* .. .. .. START: REMOVE PLL BY PASS */
  8494. /* .. .. .. PLL_BYPASS_FORCE = 0 */
  8495. /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
  8496. /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  8497. /* .. .. .. */
  8498. EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
  8499. /* .. .. .. FINISH: REMOVE PLL BY PASS */
  8500. /* .. .. FINISH: IO PLL INIT */
  8501. /* .. FINISH: PLL SLCR REGISTERS */
  8502. /* .. START: LOCK IT BACK */
  8503. /* .. LOCK_KEY = 0X767B */
  8504. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  8505. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  8506. /* .. */
  8507. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  8508. /* .. FINISH: LOCK IT BACK */
  8509. /* FINISH: top */
  8510. /* */
  8511. EMIT_EXIT(),
  8512. /* */
  8513. };
  8514. unsigned long ps7_clock_init_data_1_0[] = {
  8515. /* START: top */
  8516. /* .. START: SLCR SETTINGS */
  8517. /* .. UNLOCK_KEY = 0XDF0D */
  8518. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  8519. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  8520. /* .. */
  8521. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  8522. /* .. FINISH: SLCR SETTINGS */
  8523. /* .. START: CLOCK CONTROL SLCR REGISTERS */
  8524. /* .. CLKACT = 0x1 */
  8525. /* .. ==> 0XF8000128[0:0] = 0x00000001U */
  8526. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8527. /* .. DIVISOR0 = 0x34 */
  8528. /* .. ==> 0XF8000128[13:8] = 0x00000034U */
  8529. /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
  8530. /* .. DIVISOR1 = 0x2 */
  8531. /* .. ==> 0XF8000128[25:20] = 0x00000002U */
  8532. /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
  8533. /* .. */
  8534. EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
  8535. /* .. CLKACT = 0x1 */
  8536. /* .. ==> 0XF8000138[0:0] = 0x00000001U */
  8537. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8538. /* .. SRCSEL = 0x0 */
  8539. /* .. ==> 0XF8000138[4:4] = 0x00000000U */
  8540. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  8541. /* .. */
  8542. EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
  8543. /* .. CLKACT = 0x1 */
  8544. /* .. ==> 0XF8000140[0:0] = 0x00000001U */
  8545. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8546. /* .. SRCSEL = 0x0 */
  8547. /* .. ==> 0XF8000140[6:4] = 0x00000000U */
  8548. /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  8549. /* .. DIVISOR = 0x8 */
  8550. /* .. ==> 0XF8000140[13:8] = 0x00000008U */
  8551. /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
  8552. /* .. DIVISOR1 = 0x1 */
  8553. /* .. ==> 0XF8000140[25:20] = 0x00000001U */
  8554. /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  8555. /* .. */
  8556. EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
  8557. /* .. CLKACT = 0x1 */
  8558. /* .. ==> 0XF800014C[0:0] = 0x00000001U */
  8559. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8560. /* .. SRCSEL = 0x0 */
  8561. /* .. ==> 0XF800014C[5:4] = 0x00000000U */
  8562. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8563. /* .. DIVISOR = 0x5 */
  8564. /* .. ==> 0XF800014C[13:8] = 0x00000005U */
  8565. /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  8566. /* .. */
  8567. EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
  8568. /* .. CLKACT0 = 0x1 */
  8569. /* .. ==> 0XF8000150[0:0] = 0x00000001U */
  8570. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8571. /* .. CLKACT1 = 0x0 */
  8572. /* .. ==> 0XF8000150[1:1] = 0x00000000U */
  8573. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  8574. /* .. SRCSEL = 0x0 */
  8575. /* .. ==> 0XF8000150[5:4] = 0x00000000U */
  8576. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8577. /* .. DIVISOR = 0x14 */
  8578. /* .. ==> 0XF8000150[13:8] = 0x00000014U */
  8579. /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
  8580. /* .. */
  8581. EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
  8582. /* .. CLKACT0 = 0x0 */
  8583. /* .. ==> 0XF8000154[0:0] = 0x00000000U */
  8584. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8585. /* .. CLKACT1 = 0x1 */
  8586. /* .. ==> 0XF8000154[1:1] = 0x00000001U */
  8587. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  8588. /* .. SRCSEL = 0x0 */
  8589. /* .. ==> 0XF8000154[5:4] = 0x00000000U */
  8590. /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8591. /* .. DIVISOR = 0xa */
  8592. /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
  8593. /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
  8594. /* .. */
  8595. EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
  8596. /* .. .. START: TRACE CLOCK */
  8597. /* .. .. FINISH: TRACE CLOCK */
  8598. /* .. .. CLKACT = 0x1 */
  8599. /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
  8600. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8601. /* .. .. SRCSEL = 0x0 */
  8602. /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
  8603. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8604. /* .. .. DIVISOR = 0x5 */
  8605. /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
  8606. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  8607. /* .. .. */
  8608. EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
  8609. /* .. .. SRCSEL = 0x0 */
  8610. /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
  8611. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8612. /* .. .. DIVISOR0 = 0xa */
  8613. /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
  8614. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
  8615. /* .. .. DIVISOR1 = 0x1 */
  8616. /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
  8617. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  8618. /* .. .. */
  8619. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
  8620. /* .. .. SRCSEL = 0x0 */
  8621. /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
  8622. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8623. /* .. .. DIVISOR0 = 0x7 */
  8624. /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
  8625. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
  8626. /* .. .. DIVISOR1 = 0x1 */
  8627. /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
  8628. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  8629. /* .. .. */
  8630. EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
  8631. /* .. .. SRCSEL = 0x0 */
  8632. /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
  8633. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8634. /* .. .. DIVISOR0 = 0x5 */
  8635. /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
  8636. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
  8637. /* .. .. DIVISOR1 = 0x1 */
  8638. /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
  8639. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  8640. /* .. .. */
  8641. EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
  8642. /* .. .. SRCSEL = 0x0 */
  8643. /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
  8644. /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
  8645. /* .. .. DIVISOR0 = 0x14 */
  8646. /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
  8647. /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
  8648. /* .. .. DIVISOR1 = 0x1 */
  8649. /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
  8650. /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
  8651. /* .. .. */
  8652. EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
  8653. /* .. .. CLK_621_TRUE = 0x1 */
  8654. /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
  8655. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8656. /* .. .. */
  8657. EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
  8658. /* .. .. DMA_CPU_2XCLKACT = 0x1 */
  8659. /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
  8660. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  8661. /* .. .. USB0_CPU_1XCLKACT = 0x1 */
  8662. /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
  8663. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  8664. /* .. .. USB1_CPU_1XCLKACT = 0x1 */
  8665. /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
  8666. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
  8667. /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
  8668. /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
  8669. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
  8670. /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
  8671. /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
  8672. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  8673. /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
  8674. /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
  8675. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
  8676. /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
  8677. /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
  8678. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  8679. /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
  8680. /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
  8681. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  8682. /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
  8683. /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
  8684. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  8685. /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
  8686. /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
  8687. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  8688. /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
  8689. /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
  8690. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  8691. /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
  8692. /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
  8693. /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
  8694. /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
  8695. /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
  8696. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  8697. /* .. .. UART0_CPU_1XCLKACT = 0x0 */
  8698. /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
  8699. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  8700. /* .. .. UART1_CPU_1XCLKACT = 0x1 */
  8701. /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
  8702. /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
  8703. /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
  8704. /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
  8705. /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
  8706. /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
  8707. /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
  8708. /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
  8709. /* .. .. SMC_CPU_1XCLKACT = 0x1 */
  8710. /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
  8711. /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
  8712. /* .. .. */
  8713. EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
  8714. /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
  8715. /* .. START: THIS SHOULD BE BLANK */
  8716. /* .. FINISH: THIS SHOULD BE BLANK */
  8717. /* .. START: LOCK IT BACK */
  8718. /* .. LOCK_KEY = 0X767B */
  8719. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  8720. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  8721. /* .. */
  8722. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  8723. /* .. FINISH: LOCK IT BACK */
  8724. /* FINISH: top */
  8725. /* */
  8726. EMIT_EXIT(),
  8727. /* */
  8728. };
  8729. unsigned long ps7_ddr_init_data_1_0[] = {
  8730. /* START: top */
  8731. /* .. START: DDR INITIALIZATION */
  8732. /* .. .. START: LOCK DDR */
  8733. /* .. .. reg_ddrc_soft_rstb = 0 */
  8734. /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
  8735. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8736. /* .. .. reg_ddrc_powerdown_en = 0x0 */
  8737. /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
  8738. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  8739. /* .. .. reg_ddrc_data_bus_width = 0x0 */
  8740. /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
  8741. /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
  8742. /* .. .. reg_ddrc_burst8_refresh = 0x0 */
  8743. /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
  8744. /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  8745. /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
  8746. /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
  8747. /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
  8748. /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
  8749. /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
  8750. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  8751. /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
  8752. /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
  8753. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  8754. /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
  8755. /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
  8756. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  8757. /* .. .. */
  8758. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
  8759. /* .. .. FINISH: LOCK DDR */
  8760. /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
  8761. /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
  8762. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
  8763. /* .. .. reg_ddrc_active_ranks = 0x1 */
  8764. /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
  8765. /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
  8766. /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
  8767. /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
  8768. /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
  8769. /* .. .. reg_ddrc_wr_odt_block = 0x1 */
  8770. /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
  8771. /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
  8772. /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
  8773. /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
  8774. /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  8775. /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
  8776. /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
  8777. /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
  8778. /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
  8779. /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
  8780. /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
  8781. /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
  8782. /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
  8783. /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
  8784. /* .. .. */
  8785. EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
  8786. /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
  8787. /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
  8788. /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
  8789. /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
  8790. /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
  8791. /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
  8792. /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
  8793. /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
  8794. /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
  8795. /* .. .. */
  8796. EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
  8797. /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
  8798. /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
  8799. /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
  8800. /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
  8801. /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
  8802. /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
  8803. /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
  8804. /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
  8805. /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
  8806. /* .. .. */
  8807. EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
  8808. /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
  8809. /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
  8810. /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
  8811. /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
  8812. /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
  8813. /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
  8814. /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
  8815. /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
  8816. /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
  8817. /* .. .. */
  8818. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
  8819. /* .. .. reg_ddrc_t_rc = 0x1a */
  8820. /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
  8821. /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
  8822. /* .. .. reg_ddrc_t_rfc_min = 0x54 */
  8823. /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
  8824. /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
  8825. /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
  8826. /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
  8827. /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
  8828. /* .. .. */
  8829. EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
  8830. /* .. .. reg_ddrc_wr2pre = 0x12 */
  8831. /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
  8832. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
  8833. /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
  8834. /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
  8835. /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
  8836. /* .. .. reg_ddrc_t_faw = 0x15 */
  8837. /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
  8838. /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
  8839. /* .. .. reg_ddrc_t_ras_max = 0x23 */
  8840. /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
  8841. /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
  8842. /* .. .. reg_ddrc_t_ras_min = 0x13 */
  8843. /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
  8844. /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
  8845. /* .. .. reg_ddrc_t_cke = 0x4 */
  8846. /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
  8847. /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
  8848. /* .. .. */
  8849. EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
  8850. /* .. .. reg_ddrc_write_latency = 0x5 */
  8851. /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
  8852. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
  8853. /* .. .. reg_ddrc_rd2wr = 0x7 */
  8854. /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
  8855. /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
  8856. /* .. .. reg_ddrc_wr2rd = 0xe */
  8857. /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
  8858. /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
  8859. /* .. .. reg_ddrc_t_xp = 0x4 */
  8860. /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
  8861. /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
  8862. /* .. .. reg_ddrc_pad_pd = 0x0 */
  8863. /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
  8864. /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
  8865. /* .. .. reg_ddrc_rd2pre = 0x4 */
  8866. /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
  8867. /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
  8868. /* .. .. reg_ddrc_t_rcd = 0x7 */
  8869. /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
  8870. /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
  8871. /* .. .. */
  8872. EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
  8873. /* .. .. reg_ddrc_t_ccd = 0x4 */
  8874. /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
  8875. /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
  8876. /* .. .. reg_ddrc_t_rrd = 0x6 */
  8877. /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
  8878. /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
  8879. /* .. .. reg_ddrc_refresh_margin = 0x2 */
  8880. /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
  8881. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
  8882. /* .. .. reg_ddrc_t_rp = 0x7 */
  8883. /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
  8884. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
  8885. /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
  8886. /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
  8887. /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
  8888. /* .. .. reg_ddrc_sdram = 0x1 */
  8889. /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
  8890. /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
  8891. /* .. .. reg_ddrc_mobile = 0x0 */
  8892. /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
  8893. /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  8894. /* .. .. reg_ddrc_clock_stop_en = 0x0 */
  8895. /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
  8896. /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  8897. /* .. .. reg_ddrc_read_latency = 0x7 */
  8898. /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
  8899. /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
  8900. /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
  8901. /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
  8902. /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
  8903. /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
  8904. /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
  8905. /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
  8906. /* .. .. reg_ddrc_loopback = 0x0 */
  8907. /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
  8908. /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
  8909. /* .. .. */
  8910. EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
  8911. /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
  8912. /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
  8913. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8914. /* .. .. reg_ddrc_prefer_write = 0x0 */
  8915. /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
  8916. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  8917. /* .. .. reg_ddrc_max_rank_rd = 0xf */
  8918. /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
  8919. /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
  8920. /* .. .. reg_ddrc_mr_wr = 0x0 */
  8921. /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
  8922. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
  8923. /* .. .. reg_ddrc_mr_addr = 0x0 */
  8924. /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
  8925. /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
  8926. /* .. .. reg_ddrc_mr_data = 0x0 */
  8927. /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
  8928. /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
  8929. /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
  8930. /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
  8931. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  8932. /* .. .. reg_ddrc_mr_type = 0x0 */
  8933. /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
  8934. /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
  8935. /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
  8936. /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
  8937. /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
  8938. /* .. .. */
  8939. EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
  8940. /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
  8941. /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
  8942. /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
  8943. /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
  8944. /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
  8945. /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
  8946. /* .. .. reg_ddrc_t_mrd = 0x4 */
  8947. /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
  8948. /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
  8949. /* .. .. */
  8950. EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
  8951. /* .. .. reg_ddrc_emr2 = 0x8 */
  8952. /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
  8953. /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
  8954. /* .. .. reg_ddrc_emr3 = 0x0 */
  8955. /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
  8956. /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
  8957. /* .. .. */
  8958. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
  8959. /* .. .. reg_ddrc_mr = 0x930 */
  8960. /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
  8961. /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
  8962. /* .. .. reg_ddrc_emr = 0x4 */
  8963. /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
  8964. /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
  8965. /* .. .. */
  8966. EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
  8967. /* .. .. reg_ddrc_burst_rdwr = 0x4 */
  8968. /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
  8969. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
  8970. /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
  8971. /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
  8972. /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
  8973. /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
  8974. /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
  8975. /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
  8976. /* .. .. reg_ddrc_burstchop = 0x0 */
  8977. /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
  8978. /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
  8979. /* .. .. */
  8980. EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
  8981. /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
  8982. /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
  8983. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  8984. /* .. .. reg_ddrc_dis_dq = 0x0 */
  8985. /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
  8986. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  8987. /* .. .. reg_phy_debug_mode = 0x0 */
  8988. /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
  8989. /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
  8990. /* .. .. reg_phy_wr_level_start = 0x0 */
  8991. /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
  8992. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  8993. /* .. .. reg_phy_rd_level_start = 0x0 */
  8994. /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
  8995. /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  8996. /* .. .. reg_phy_dq0_wait_t = 0x0 */
  8997. /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
  8998. /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
  8999. /* .. .. */
  9000. EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
  9001. /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
  9002. /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
  9003. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
  9004. /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
  9005. /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
  9006. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
  9007. /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
  9008. /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
  9009. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
  9010. /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
  9011. /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
  9012. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
  9013. /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
  9014. /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
  9015. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
  9016. /* .. .. */
  9017. EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
  9018. /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
  9019. /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
  9020. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  9021. /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
  9022. /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
  9023. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  9024. /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
  9025. /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
  9026. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
  9027. /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
  9028. /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
  9029. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
  9030. /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
  9031. /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
  9032. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
  9033. /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
  9034. /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
  9035. /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
  9036. /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
  9037. /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
  9038. /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
  9039. /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
  9040. /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
  9041. /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
  9042. /* .. .. */
  9043. EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
  9044. /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
  9045. /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
  9046. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
  9047. /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
  9048. /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
  9049. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
  9050. /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
  9051. /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
  9052. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
  9053. /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
  9054. /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
  9055. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
  9056. /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
  9057. /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
  9058. /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
  9059. /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
  9060. /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
  9061. /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
  9062. /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
  9063. /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
  9064. /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
  9065. /* .. .. */
  9066. EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
  9067. /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
  9068. /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
  9069. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
  9070. /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
  9071. /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
  9072. /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
  9073. /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
  9074. /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
  9075. /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
  9076. /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
  9077. /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
  9078. /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  9079. /* .. .. reg_phy_rd_local_odt = 0x0 */
  9080. /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
  9081. /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
  9082. /* .. .. reg_phy_wr_local_odt = 0x3 */
  9083. /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
  9084. /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
  9085. /* .. .. reg_phy_idle_local_odt = 0x3 */
  9086. /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
  9087. /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
  9088. /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
  9089. /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
  9090. /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
  9091. /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
  9092. /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
  9093. /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
  9094. /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
  9095. /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
  9096. /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  9097. /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
  9098. /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
  9099. /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
  9100. /* .. .. */
  9101. EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
  9102. /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
  9103. /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
  9104. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  9105. /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
  9106. /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
  9107. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  9108. /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
  9109. /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
  9110. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
  9111. /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
  9112. /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
  9113. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  9114. /* .. .. reg_phy_use_fixed_re = 0x1 */
  9115. /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
  9116. /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
  9117. /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
  9118. /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
  9119. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9120. /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
  9121. /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
  9122. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9123. /* .. .. reg_phy_clk_stall_level = 0x0 */
  9124. /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
  9125. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  9126. /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
  9127. /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
  9128. /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
  9129. /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
  9130. /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
  9131. /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
  9132. /* .. .. */
  9133. EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
  9134. /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
  9135. /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
  9136. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
  9137. /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
  9138. /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
  9139. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
  9140. /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
  9141. /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
  9142. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9143. /* .. .. */
  9144. EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
  9145. /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
  9146. /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
  9147. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
  9148. /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
  9149. /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
  9150. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  9151. /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
  9152. /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
  9153. /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
  9154. /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
  9155. /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
  9156. /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
  9157. /* .. .. */
  9158. EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
  9159. /* .. .. reg_ddrc_pageclose = 0x0 */
  9160. /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
  9161. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9162. /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
  9163. /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
  9164. /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
  9165. /* .. .. reg_ddrc_auto_pre_en = 0x0 */
  9166. /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
  9167. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  9168. /* .. .. reg_ddrc_refresh_update_level = 0x0 */
  9169. /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
  9170. /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  9171. /* .. .. reg_ddrc_dis_wc = 0x0 */
  9172. /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
  9173. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  9174. /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
  9175. /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
  9176. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9177. /* .. .. reg_ddrc_selfref_en = 0x0 */
  9178. /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
  9179. /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  9180. /* .. .. */
  9181. EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
  9182. /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
  9183. /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
  9184. /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
  9185. /* .. .. reg_arb_go2critical_en = 0x1 */
  9186. /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
  9187. /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
  9188. /* .. .. */
  9189. EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
  9190. /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
  9191. /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
  9192. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
  9193. /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
  9194. /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
  9195. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
  9196. /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
  9197. /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
  9198. /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
  9199. /* .. .. */
  9200. EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
  9201. /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
  9202. /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
  9203. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
  9204. /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
  9205. /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
  9206. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
  9207. /* .. .. */
  9208. EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
  9209. /* .. .. refresh_timer0_start_value_x32 = 0x0 */
  9210. /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
  9211. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
  9212. /* .. .. refresh_timer1_start_value_x32 = 0x8 */
  9213. /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
  9214. /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
  9215. /* .. .. */
  9216. EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
  9217. /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
  9218. /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
  9219. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9220. /* .. .. reg_ddrc_ddr3 = 0x1 */
  9221. /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
  9222. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  9223. /* .. .. reg_ddrc_t_mod = 0x200 */
  9224. /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
  9225. /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
  9226. /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
  9227. /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
  9228. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
  9229. /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
  9230. /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
  9231. /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
  9232. /* .. .. */
  9233. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
  9234. /* .. .. t_zq_short_interval_x1024 = 0xc845 */
  9235. /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
  9236. /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
  9237. /* .. .. dram_rstn_x1024 = 0x67 */
  9238. /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
  9239. /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
  9240. /* .. .. */
  9241. EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
  9242. /* .. .. deeppowerdown_en = 0x0 */
  9243. /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
  9244. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9245. /* .. .. deeppowerdown_to_x1024 = 0xff */
  9246. /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
  9247. /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
  9248. /* .. .. */
  9249. EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
  9250. /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
  9251. /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
  9252. /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
  9253. /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
  9254. /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
  9255. /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
  9256. /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
  9257. /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
  9258. /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  9259. /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
  9260. /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
  9261. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  9262. /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
  9263. /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
  9264. /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
  9265. /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
  9266. /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
  9267. /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
  9268. /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
  9269. /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
  9270. /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  9271. /* .. .. */
  9272. EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
  9273. /* .. .. reg_ddrc_2t_delay = 0x0 */
  9274. /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
  9275. /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
  9276. /* .. .. reg_ddrc_skip_ocd = 0x1 */
  9277. /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
  9278. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
  9279. /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
  9280. /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
  9281. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9282. /* .. .. */
  9283. EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
  9284. /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
  9285. /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
  9286. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
  9287. /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
  9288. /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
  9289. /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
  9290. /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
  9291. /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
  9292. /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
  9293. /* .. .. */
  9294. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
  9295. /* .. .. START: RESET ECC ERROR */
  9296. /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
  9297. /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
  9298. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  9299. /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
  9300. /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
  9301. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  9302. /* .. .. */
  9303. EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
  9304. /* .. .. FINISH: RESET ECC ERROR */
  9305. /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
  9306. /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
  9307. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9308. /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
  9309. /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
  9310. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9311. /* .. .. */
  9312. EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
  9313. /* .. .. CORR_ECC_LOG_VALID = 0x0 */
  9314. /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
  9315. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9316. /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
  9317. /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
  9318. /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
  9319. /* .. .. */
  9320. EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
  9321. /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
  9322. /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
  9323. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9324. /* .. .. */
  9325. EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
  9326. /* .. .. STAT_NUM_CORR_ERR = 0x0 */
  9327. /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
  9328. /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
  9329. /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
  9330. /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
  9331. /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
  9332. /* .. .. */
  9333. EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
  9334. /* .. .. reg_ddrc_ecc_mode = 0x0 */
  9335. /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
  9336. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
  9337. /* .. .. reg_ddrc_dis_scrub = 0x1 */
  9338. /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
  9339. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
  9340. /* .. .. */
  9341. EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
  9342. /* .. .. reg_phy_dif_on = 0x0 */
  9343. /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
  9344. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
  9345. /* .. .. reg_phy_dif_off = 0x0 */
  9346. /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
  9347. /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  9348. /* .. .. */
  9349. EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
  9350. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  9351. /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
  9352. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  9353. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  9354. /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
  9355. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9356. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  9357. /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
  9358. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  9359. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  9360. /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
  9361. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  9362. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  9363. /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
  9364. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  9365. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  9366. /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
  9367. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  9368. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  9369. /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
  9370. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  9371. /* .. .. reg_phy_bist_err_clr = 0x0 */
  9372. /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
  9373. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  9374. /* .. .. reg_phy_dq_offset = 0x40 */
  9375. /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
  9376. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  9377. /* .. .. */
  9378. EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
  9379. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  9380. /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
  9381. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  9382. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  9383. /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
  9384. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9385. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  9386. /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
  9387. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  9388. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  9389. /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
  9390. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  9391. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  9392. /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
  9393. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  9394. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  9395. /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
  9396. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  9397. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  9398. /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
  9399. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  9400. /* .. .. reg_phy_bist_err_clr = 0x0 */
  9401. /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
  9402. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  9403. /* .. .. reg_phy_dq_offset = 0x40 */
  9404. /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
  9405. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  9406. /* .. .. */
  9407. EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
  9408. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  9409. /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
  9410. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  9411. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  9412. /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
  9413. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9414. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  9415. /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
  9416. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  9417. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  9418. /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
  9419. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  9420. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  9421. /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
  9422. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  9423. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  9424. /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
  9425. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  9426. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  9427. /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
  9428. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  9429. /* .. .. reg_phy_bist_err_clr = 0x0 */
  9430. /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
  9431. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  9432. /* .. .. reg_phy_dq_offset = 0x40 */
  9433. /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
  9434. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  9435. /* .. .. */
  9436. EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
  9437. /* .. .. reg_phy_data_slice_in_use = 0x1 */
  9438. /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
  9439. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  9440. /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
  9441. /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
  9442. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9443. /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
  9444. /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
  9445. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  9446. /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
  9447. /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
  9448. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  9449. /* .. .. reg_phy_board_lpbk_tx = 0x0 */
  9450. /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
  9451. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  9452. /* .. .. reg_phy_board_lpbk_rx = 0x0 */
  9453. /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
  9454. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
  9455. /* .. .. reg_phy_bist_shift_dq = 0x0 */
  9456. /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
  9457. /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
  9458. /* .. .. reg_phy_bist_err_clr = 0x0 */
  9459. /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
  9460. /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
  9461. /* .. .. reg_phy_dq_offset = 0x40 */
  9462. /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
  9463. /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
  9464. /* .. .. */
  9465. EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
  9466. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  9467. /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
  9468. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  9469. /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
  9470. /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
  9471. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
  9472. /* .. .. */
  9473. EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
  9474. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  9475. /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
  9476. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  9477. /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
  9478. /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
  9479. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
  9480. /* .. .. */
  9481. EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
  9482. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  9483. /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
  9484. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  9485. /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
  9486. /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
  9487. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
  9488. /* .. .. */
  9489. EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
  9490. /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
  9491. /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
  9492. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
  9493. /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
  9494. /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
  9495. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
  9496. /* .. .. */
  9497. EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
  9498. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  9499. /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
  9500. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  9501. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  9502. /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
  9503. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9504. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  9505. /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
  9506. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9507. /* .. .. */
  9508. EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
  9509. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  9510. /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
  9511. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  9512. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  9513. /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
  9514. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9515. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  9516. /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
  9517. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9518. /* .. .. */
  9519. EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
  9520. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  9521. /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
  9522. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  9523. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  9524. /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
  9525. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9526. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  9527. /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
  9528. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9529. /* .. .. */
  9530. EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
  9531. /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
  9532. /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
  9533. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
  9534. /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
  9535. /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
  9536. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9537. /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
  9538. /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
  9539. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9540. /* .. .. */
  9541. EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
  9542. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
  9543. /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
  9544. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
  9545. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  9546. /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
  9547. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9548. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  9549. /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
  9550. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9551. /* .. .. */
  9552. EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
  9553. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
  9554. /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
  9555. /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
  9556. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  9557. /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
  9558. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9559. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  9560. /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
  9561. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9562. /* .. .. */
  9563. EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
  9564. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
  9565. /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
  9566. /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
  9567. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  9568. /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
  9569. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9570. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  9571. /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
  9572. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9573. /* .. .. */
  9574. EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
  9575. /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
  9576. /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
  9577. /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
  9578. /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
  9579. /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
  9580. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9581. /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
  9582. /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
  9583. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9584. /* .. .. */
  9585. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
  9586. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
  9587. /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
  9588. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
  9589. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  9590. /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
  9591. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  9592. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  9593. /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
  9594. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  9595. /* .. .. */
  9596. EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
  9597. /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
  9598. /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
  9599. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
  9600. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  9601. /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
  9602. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  9603. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  9604. /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
  9605. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  9606. /* .. .. */
  9607. EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
  9608. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
  9609. /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
  9610. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
  9611. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  9612. /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
  9613. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  9614. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  9615. /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
  9616. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  9617. /* .. .. */
  9618. EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
  9619. /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
  9620. /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
  9621. /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
  9622. /* .. .. reg_phy_fifo_we_in_force = 0x0 */
  9623. /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
  9624. /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  9625. /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
  9626. /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
  9627. /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
  9628. /* .. .. */
  9629. EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
  9630. /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
  9631. /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
  9632. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
  9633. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  9634. /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
  9635. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9636. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  9637. /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
  9638. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9639. /* .. .. */
  9640. EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
  9641. /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
  9642. /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
  9643. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
  9644. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  9645. /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
  9646. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9647. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  9648. /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
  9649. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9650. /* .. .. */
  9651. EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
  9652. /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
  9653. /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
  9654. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
  9655. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  9656. /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
  9657. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9658. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  9659. /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
  9660. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9661. /* .. .. */
  9662. EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
  9663. /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
  9664. /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
  9665. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
  9666. /* .. .. reg_phy_wr_data_slave_force = 0x0 */
  9667. /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
  9668. /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  9669. /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
  9670. /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
  9671. /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
  9672. /* .. .. */
  9673. EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
  9674. /* .. .. reg_phy_loopback = 0x0 */
  9675. /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
  9676. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9677. /* .. .. reg_phy_bl2 = 0x0 */
  9678. /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
  9679. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9680. /* .. .. reg_phy_at_spd_atpg = 0x0 */
  9681. /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
  9682. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  9683. /* .. .. reg_phy_bist_enable = 0x0 */
  9684. /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
  9685. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  9686. /* .. .. reg_phy_bist_force_err = 0x0 */
  9687. /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
  9688. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  9689. /* .. .. reg_phy_bist_mode = 0x0 */
  9690. /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
  9691. /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  9692. /* .. .. reg_phy_invert_clkout = 0x1 */
  9693. /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
  9694. /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  9695. /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
  9696. /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
  9697. /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  9698. /* .. .. reg_phy_sel_logic = 0x0 */
  9699. /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
  9700. /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  9701. /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
  9702. /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
  9703. /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
  9704. /* .. .. reg_phy_ctrl_slave_force = 0x0 */
  9705. /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
  9706. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  9707. /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
  9708. /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
  9709. /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
  9710. /* .. .. reg_phy_use_rank0_delays = 0x1 */
  9711. /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
  9712. /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
  9713. /* .. .. reg_phy_lpddr = 0x0 */
  9714. /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
  9715. /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
  9716. /* .. .. reg_phy_cmd_latency = 0x0 */
  9717. /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
  9718. /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
  9719. /* .. .. reg_phy_int_lpbk = 0x0 */
  9720. /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
  9721. /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
  9722. /* .. .. */
  9723. EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
  9724. /* .. .. reg_phy_wr_rl_delay = 0x2 */
  9725. /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
  9726. /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
  9727. /* .. .. reg_phy_rd_rl_delay = 0x4 */
  9728. /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
  9729. /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
  9730. /* .. .. reg_phy_dll_lock_diff = 0xf */
  9731. /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
  9732. /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
  9733. /* .. .. reg_phy_use_wr_level = 0x1 */
  9734. /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
  9735. /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
  9736. /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
  9737. /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
  9738. /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
  9739. /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
  9740. /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
  9741. /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
  9742. /* .. .. reg_phy_dis_calib_rst = 0x0 */
  9743. /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
  9744. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9745. /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
  9746. /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
  9747. /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
  9748. /* .. .. */
  9749. EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
  9750. /* .. .. reg_arb_page_addr_mask = 0x0 */
  9751. /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
  9752. /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
  9753. /* .. .. */
  9754. EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
  9755. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  9756. /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
  9757. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9758. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  9759. /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
  9760. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9761. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  9762. /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
  9763. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9764. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  9765. /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
  9766. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9767. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  9768. /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
  9769. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  9770. /* .. .. */
  9771. EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
  9772. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  9773. /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
  9774. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9775. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  9776. /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
  9777. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9778. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  9779. /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
  9780. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9781. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  9782. /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
  9783. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9784. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  9785. /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
  9786. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  9787. /* .. .. */
  9788. EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
  9789. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  9790. /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
  9791. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9792. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  9793. /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
  9794. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9795. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  9796. /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
  9797. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9798. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  9799. /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
  9800. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9801. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  9802. /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
  9803. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  9804. /* .. .. */
  9805. EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
  9806. /* .. .. reg_arb_pri_wr_portn = 0x3ff */
  9807. /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
  9808. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9809. /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
  9810. /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
  9811. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9812. /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
  9813. /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
  9814. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9815. /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
  9816. /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
  9817. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9818. /* .. .. reg_arb_dis_rmw_portn = 0x1 */
  9819. /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
  9820. /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  9821. /* .. .. */
  9822. EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
  9823. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  9824. /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
  9825. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9826. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  9827. /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
  9828. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9829. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  9830. /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
  9831. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9832. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  9833. /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
  9834. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9835. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  9836. /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
  9837. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  9838. /* .. .. */
  9839. EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
  9840. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  9841. /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
  9842. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9843. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  9844. /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
  9845. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9846. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  9847. /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
  9848. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9849. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  9850. /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
  9851. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9852. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  9853. /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
  9854. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  9855. /* .. .. */
  9856. EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
  9857. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  9858. /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
  9859. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9860. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  9861. /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
  9862. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9863. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  9864. /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
  9865. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9866. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  9867. /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
  9868. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9869. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  9870. /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
  9871. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  9872. /* .. .. */
  9873. EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
  9874. /* .. .. reg_arb_pri_rd_portn = 0x3ff */
  9875. /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
  9876. /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
  9877. /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
  9878. /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
  9879. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9880. /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
  9881. /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
  9882. /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  9883. /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
  9884. /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
  9885. /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
  9886. /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
  9887. /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
  9888. /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
  9889. /* .. .. */
  9890. EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
  9891. /* .. .. reg_ddrc_lpddr2 = 0x0 */
  9892. /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
  9893. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  9894. /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
  9895. /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
  9896. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9897. /* .. .. reg_ddrc_derate_enable = 0x0 */
  9898. /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
  9899. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  9900. /* .. .. reg_ddrc_mr4_margin = 0x0 */
  9901. /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
  9902. /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
  9903. /* .. .. */
  9904. EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
  9905. /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
  9906. /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
  9907. /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
  9908. /* .. .. */
  9909. EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
  9910. /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
  9911. /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
  9912. /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
  9913. /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
  9914. /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
  9915. /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
  9916. /* .. .. reg_ddrc_t_mrw = 0x5 */
  9917. /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
  9918. /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
  9919. /* .. .. */
  9920. EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
  9921. /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
  9922. /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
  9923. /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
  9924. /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
  9925. /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
  9926. /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
  9927. /* .. .. */
  9928. EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
  9929. /* .. .. START: POLL ON DCI STATUS */
  9930. /* .. .. DONE = 1 */
  9931. /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
  9932. /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  9933. /* .. .. */
  9934. EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
  9935. /* .. .. FINISH: POLL ON DCI STATUS */
  9936. /* .. .. START: UNLOCK DDR */
  9937. /* .. .. reg_ddrc_soft_rstb = 0x1 */
  9938. /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
  9939. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  9940. /* .. .. reg_ddrc_powerdown_en = 0x0 */
  9941. /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
  9942. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9943. /* .. .. reg_ddrc_data_bus_width = 0x0 */
  9944. /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
  9945. /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
  9946. /* .. .. reg_ddrc_burst8_refresh = 0x0 */
  9947. /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
  9948. /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
  9949. /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
  9950. /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
  9951. /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
  9952. /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
  9953. /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
  9954. /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  9955. /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
  9956. /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
  9957. /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
  9958. /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
  9959. /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
  9960. /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  9961. /* .. .. */
  9962. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
  9963. /* .. .. FINISH: UNLOCK DDR */
  9964. /* .. .. START: CHECK DDR STATUS */
  9965. /* .. .. ddrc_reg_operating_mode = 1 */
  9966. /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
  9967. /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
  9968. /* .. .. */
  9969. EMIT_MASKPOLL(0XF8006054, 0x00000007U),
  9970. /* .. .. FINISH: CHECK DDR STATUS */
  9971. /* .. FINISH: DDR INITIALIZATION */
  9972. /* FINISH: top */
  9973. /* */
  9974. EMIT_EXIT(),
  9975. /* */
  9976. };
  9977. unsigned long ps7_mio_init_data_1_0[] = {
  9978. /* START: top */
  9979. /* .. START: SLCR SETTINGS */
  9980. /* .. UNLOCK_KEY = 0XDF0D */
  9981. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  9982. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  9983. /* .. */
  9984. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  9985. /* .. FINISH: SLCR SETTINGS */
  9986. /* .. START: OCM REMAPPING */
  9987. /* .. VREF_EN = 0x1 */
  9988. /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
  9989. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  9990. /* .. VREF_PULLUP_EN = 0x0 */
  9991. /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
  9992. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  9993. /* .. CLK_PULLUP_EN = 0x0 */
  9994. /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
  9995. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  9996. /* .. SRSTN_PULLUP_EN = 0x0 */
  9997. /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
  9998. /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  9999. /* .. */
  10000. EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
  10001. /* .. FINISH: OCM REMAPPING */
  10002. /* .. START: DDRIOB SETTINGS */
  10003. /* .. INP_POWER = 0x0 */
  10004. /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
  10005. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10006. /* .. INP_TYPE = 0x0 */
  10007. /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
  10008. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  10009. /* .. DCI_UPDATE = 0x0 */
  10010. /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
  10011. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10012. /* .. TERM_EN = 0x0 */
  10013. /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
  10014. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  10015. /* .. DCR_TYPE = 0x0 */
  10016. /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
  10017. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  10018. /* .. IBUF_DISABLE_MODE = 0x0 */
  10019. /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
  10020. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  10021. /* .. TERM_DISABLE_MODE = 0x0 */
  10022. /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
  10023. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10024. /* .. OUTPUT_EN = 0x3 */
  10025. /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
  10026. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  10027. /* .. PULLUP_EN = 0x0 */
  10028. /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
  10029. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  10030. /* .. */
  10031. EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
  10032. /* .. INP_POWER = 0x0 */
  10033. /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
  10034. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10035. /* .. INP_TYPE = 0x0 */
  10036. /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
  10037. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  10038. /* .. DCI_UPDATE = 0x0 */
  10039. /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
  10040. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10041. /* .. TERM_EN = 0x0 */
  10042. /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
  10043. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  10044. /* .. DCR_TYPE = 0x0 */
  10045. /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
  10046. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  10047. /* .. IBUF_DISABLE_MODE = 0x0 */
  10048. /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
  10049. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  10050. /* .. TERM_DISABLE_MODE = 0x0 */
  10051. /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
  10052. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10053. /* .. OUTPUT_EN = 0x3 */
  10054. /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
  10055. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  10056. /* .. PULLUP_EN = 0x0 */
  10057. /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
  10058. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  10059. /* .. */
  10060. EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
  10061. /* .. INP_POWER = 0x0 */
  10062. /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
  10063. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10064. /* .. INP_TYPE = 0x1 */
  10065. /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
  10066. /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
  10067. /* .. DCI_UPDATE = 0x0 */
  10068. /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
  10069. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10070. /* .. TERM_EN = 0x1 */
  10071. /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
  10072. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  10073. /* .. DCR_TYPE = 0x3 */
  10074. /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
  10075. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  10076. /* .. IBUF_DISABLE_MODE = 0 */
  10077. /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
  10078. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  10079. /* .. TERM_DISABLE_MODE = 0 */
  10080. /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
  10081. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10082. /* .. OUTPUT_EN = 0x3 */
  10083. /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
  10084. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  10085. /* .. PULLUP_EN = 0x0 */
  10086. /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
  10087. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  10088. /* .. */
  10089. EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
  10090. /* .. INP_POWER = 0x0 */
  10091. /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
  10092. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10093. /* .. INP_TYPE = 0x1 */
  10094. /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
  10095. /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
  10096. /* .. DCI_UPDATE = 0x0 */
  10097. /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
  10098. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10099. /* .. TERM_EN = 0x1 */
  10100. /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
  10101. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  10102. /* .. DCR_TYPE = 0x3 */
  10103. /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
  10104. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  10105. /* .. IBUF_DISABLE_MODE = 0 */
  10106. /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
  10107. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  10108. /* .. TERM_DISABLE_MODE = 0 */
  10109. /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
  10110. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10111. /* .. OUTPUT_EN = 0x3 */
  10112. /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
  10113. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  10114. /* .. PULLUP_EN = 0x0 */
  10115. /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
  10116. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  10117. /* .. */
  10118. EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
  10119. /* .. INP_POWER = 0x0 */
  10120. /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
  10121. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10122. /* .. INP_TYPE = 0x2 */
  10123. /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
  10124. /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
  10125. /* .. DCI_UPDATE = 0x0 */
  10126. /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
  10127. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10128. /* .. TERM_EN = 0x1 */
  10129. /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
  10130. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  10131. /* .. DCR_TYPE = 0x3 */
  10132. /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
  10133. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  10134. /* .. IBUF_DISABLE_MODE = 0 */
  10135. /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
  10136. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  10137. /* .. TERM_DISABLE_MODE = 0 */
  10138. /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
  10139. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10140. /* .. OUTPUT_EN = 0x3 */
  10141. /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
  10142. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  10143. /* .. PULLUP_EN = 0x0 */
  10144. /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
  10145. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  10146. /* .. */
  10147. EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
  10148. /* .. INP_POWER = 0x0 */
  10149. /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
  10150. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10151. /* .. INP_TYPE = 0x2 */
  10152. /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
  10153. /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
  10154. /* .. DCI_UPDATE = 0x0 */
  10155. /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
  10156. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10157. /* .. TERM_EN = 0x1 */
  10158. /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
  10159. /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
  10160. /* .. DCR_TYPE = 0x3 */
  10161. /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
  10162. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  10163. /* .. IBUF_DISABLE_MODE = 0 */
  10164. /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
  10165. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  10166. /* .. TERM_DISABLE_MODE = 0 */
  10167. /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
  10168. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10169. /* .. OUTPUT_EN = 0x3 */
  10170. /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
  10171. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  10172. /* .. PULLUP_EN = 0x0 */
  10173. /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
  10174. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  10175. /* .. */
  10176. EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
  10177. /* .. INP_POWER = 0x0 */
  10178. /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
  10179. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10180. /* .. INP_TYPE = 0x0 */
  10181. /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
  10182. /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
  10183. /* .. DCI_UPDATE = 0x0 */
  10184. /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
  10185. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10186. /* .. TERM_EN = 0x0 */
  10187. /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
  10188. /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  10189. /* .. DCR_TYPE = 0x0 */
  10190. /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
  10191. /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
  10192. /* .. IBUF_DISABLE_MODE = 0x0 */
  10193. /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
  10194. /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
  10195. /* .. TERM_DISABLE_MODE = 0x0 */
  10196. /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
  10197. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10198. /* .. OUTPUT_EN = 0x3 */
  10199. /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
  10200. /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
  10201. /* .. PULLUP_EN = 0x0 */
  10202. /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
  10203. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  10204. /* .. */
  10205. EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
  10206. /* .. DRIVE_P = 0x1c */
  10207. /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
  10208. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  10209. /* .. DRIVE_N = 0xc */
  10210. /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
  10211. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  10212. /* .. SLEW_P = 0x3 */
  10213. /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
  10214. /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
  10215. /* .. SLEW_N = 0x3 */
  10216. /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
  10217. /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
  10218. /* .. GTL = 0x0 */
  10219. /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
  10220. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  10221. /* .. RTERM = 0x0 */
  10222. /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
  10223. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  10224. /* .. */
  10225. EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
  10226. /* .. DRIVE_P = 0x1c */
  10227. /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
  10228. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  10229. /* .. DRIVE_N = 0xc */
  10230. /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
  10231. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  10232. /* .. SLEW_P = 0x6 */
  10233. /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
  10234. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  10235. /* .. SLEW_N = 0x1f */
  10236. /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
  10237. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  10238. /* .. GTL = 0x0 */
  10239. /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
  10240. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  10241. /* .. RTERM = 0x0 */
  10242. /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
  10243. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  10244. /* .. */
  10245. EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
  10246. /* .. DRIVE_P = 0x1c */
  10247. /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
  10248. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  10249. /* .. DRIVE_N = 0xc */
  10250. /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
  10251. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  10252. /* .. SLEW_P = 0x6 */
  10253. /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
  10254. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  10255. /* .. SLEW_N = 0x1f */
  10256. /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
  10257. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  10258. /* .. GTL = 0x0 */
  10259. /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
  10260. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  10261. /* .. RTERM = 0x0 */
  10262. /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
  10263. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  10264. /* .. */
  10265. EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
  10266. /* .. DRIVE_P = 0x1c */
  10267. /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
  10268. /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
  10269. /* .. DRIVE_N = 0xc */
  10270. /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
  10271. /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
  10272. /* .. SLEW_P = 0x6 */
  10273. /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
  10274. /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
  10275. /* .. SLEW_N = 0x1f */
  10276. /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
  10277. /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
  10278. /* .. GTL = 0x0 */
  10279. /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
  10280. /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
  10281. /* .. RTERM = 0x0 */
  10282. /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
  10283. /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
  10284. /* .. */
  10285. EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
  10286. /* .. VREF_INT_EN = 0x0 */
  10287. /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
  10288. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10289. /* .. VREF_SEL = 0x0 */
  10290. /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
  10291. /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
  10292. /* .. VREF_EXT_EN = 0x3 */
  10293. /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
  10294. /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
  10295. /* .. VREF_PULLUP_EN = 0x0 */
  10296. /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
  10297. /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
  10298. /* .. REFIO_EN = 0x1 */
  10299. /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
  10300. /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
  10301. /* .. REFIO_PULLUP_EN = 0x0 */
  10302. /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
  10303. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10304. /* .. DRST_B_PULLUP_EN = 0x0 */
  10305. /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
  10306. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10307. /* .. CKE_PULLUP_EN = 0x0 */
  10308. /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
  10309. /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
  10310. /* .. */
  10311. EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
  10312. /* .. .. START: ASSERT RESET */
  10313. /* .. .. RESET = 1 */
  10314. /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
  10315. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  10316. /* .. .. VRN_OUT = 0x1 */
  10317. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  10318. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  10319. /* .. .. */
  10320. EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
  10321. /* .. .. FINISH: ASSERT RESET */
  10322. /* .. .. START: DEASSERT RESET */
  10323. /* .. .. RESET = 0 */
  10324. /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
  10325. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10326. /* .. .. VRN_OUT = 0x1 */
  10327. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  10328. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  10329. /* .. .. */
  10330. EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
  10331. /* .. .. FINISH: DEASSERT RESET */
  10332. /* .. .. RESET = 0x1 */
  10333. /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
  10334. /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  10335. /* .. .. ENABLE = 0x1 */
  10336. /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
  10337. /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10338. /* .. .. VRP_TRI = 0x0 */
  10339. /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
  10340. /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10341. /* .. .. VRN_TRI = 0x0 */
  10342. /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
  10343. /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  10344. /* .. .. VRP_OUT = 0x0 */
  10345. /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
  10346. /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
  10347. /* .. .. VRN_OUT = 0x1 */
  10348. /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
  10349. /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
  10350. /* .. .. NREF_OPT1 = 0x0 */
  10351. /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
  10352. /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
  10353. /* .. .. NREF_OPT2 = 0x0 */
  10354. /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
  10355. /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
  10356. /* .. .. NREF_OPT4 = 0x1 */
  10357. /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
  10358. /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
  10359. /* .. .. PREF_OPT1 = 0x0 */
  10360. /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
  10361. /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
  10362. /* .. .. PREF_OPT2 = 0x0 */
  10363. /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
  10364. /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
  10365. /* .. .. UPDATE_CONTROL = 0x0 */
  10366. /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
  10367. /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  10368. /* .. .. INIT_COMPLETE = 0x0 */
  10369. /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
  10370. /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  10371. /* .. .. TST_CLK = 0x0 */
  10372. /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
  10373. /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  10374. /* .. .. TST_HLN = 0x0 */
  10375. /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
  10376. /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  10377. /* .. .. TST_HLP = 0x0 */
  10378. /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
  10379. /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  10380. /* .. .. TST_RST = 0x0 */
  10381. /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
  10382. /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
  10383. /* .. .. INT_DCI_EN = 0x0 */
  10384. /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
  10385. /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
  10386. /* .. .. */
  10387. EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
  10388. /* .. FINISH: DDRIOB SETTINGS */
  10389. /* .. START: MIO PROGRAMMING */
  10390. /* .. TRI_ENABLE = 0 */
  10391. /* .. ==> 0XF8000700[0:0] = 0x00000000U */
  10392. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10393. /* .. L0_SEL = 0 */
  10394. /* .. ==> 0XF8000700[1:1] = 0x00000000U */
  10395. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10396. /* .. L1_SEL = 0 */
  10397. /* .. ==> 0XF8000700[2:2] = 0x00000000U */
  10398. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10399. /* .. L2_SEL = 0 */
  10400. /* .. ==> 0XF8000700[4:3] = 0x00000000U */
  10401. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10402. /* .. L3_SEL = 0 */
  10403. /* .. ==> 0XF8000700[7:5] = 0x00000000U */
  10404. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10405. /* .. Speed = 0 */
  10406. /* .. ==> 0XF8000700[8:8] = 0x00000000U */
  10407. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10408. /* .. IO_Type = 3 */
  10409. /* .. ==> 0XF8000700[11:9] = 0x00000003U */
  10410. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10411. /* .. PULLUP = 1 */
  10412. /* .. ==> 0XF8000700[12:12] = 0x00000001U */
  10413. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10414. /* .. DisableRcvr = 0 */
  10415. /* .. ==> 0XF8000700[13:13] = 0x00000000U */
  10416. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10417. /* .. */
  10418. EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
  10419. /* .. TRI_ENABLE = 0 */
  10420. /* .. ==> 0XF8000704[0:0] = 0x00000000U */
  10421. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10422. /* .. L0_SEL = 1 */
  10423. /* .. ==> 0XF8000704[1:1] = 0x00000001U */
  10424. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10425. /* .. L1_SEL = 0 */
  10426. /* .. ==> 0XF8000704[2:2] = 0x00000000U */
  10427. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10428. /* .. L2_SEL = 0 */
  10429. /* .. ==> 0XF8000704[4:3] = 0x00000000U */
  10430. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10431. /* .. L3_SEL = 0 */
  10432. /* .. ==> 0XF8000704[7:5] = 0x00000000U */
  10433. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10434. /* .. Speed = 1 */
  10435. /* .. ==> 0XF8000704[8:8] = 0x00000001U */
  10436. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10437. /* .. IO_Type = 3 */
  10438. /* .. ==> 0XF8000704[11:9] = 0x00000003U */
  10439. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10440. /* .. PULLUP = 0 */
  10441. /* .. ==> 0XF8000704[12:12] = 0x00000000U */
  10442. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10443. /* .. DisableRcvr = 0 */
  10444. /* .. ==> 0XF8000704[13:13] = 0x00000000U */
  10445. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10446. /* .. */
  10447. EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
  10448. /* .. TRI_ENABLE = 0 */
  10449. /* .. ==> 0XF8000708[0:0] = 0x00000000U */
  10450. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10451. /* .. L0_SEL = 1 */
  10452. /* .. ==> 0XF8000708[1:1] = 0x00000001U */
  10453. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10454. /* .. L1_SEL = 0 */
  10455. /* .. ==> 0XF8000708[2:2] = 0x00000000U */
  10456. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10457. /* .. L2_SEL = 0 */
  10458. /* .. ==> 0XF8000708[4:3] = 0x00000000U */
  10459. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10460. /* .. L3_SEL = 0 */
  10461. /* .. ==> 0XF8000708[7:5] = 0x00000000U */
  10462. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10463. /* .. Speed = 1 */
  10464. /* .. ==> 0XF8000708[8:8] = 0x00000001U */
  10465. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10466. /* .. IO_Type = 3 */
  10467. /* .. ==> 0XF8000708[11:9] = 0x00000003U */
  10468. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10469. /* .. PULLUP = 0 */
  10470. /* .. ==> 0XF8000708[12:12] = 0x00000000U */
  10471. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10472. /* .. DisableRcvr = 0 */
  10473. /* .. ==> 0XF8000708[13:13] = 0x00000000U */
  10474. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10475. /* .. */
  10476. EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
  10477. /* .. TRI_ENABLE = 0 */
  10478. /* .. ==> 0XF800070C[0:0] = 0x00000000U */
  10479. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10480. /* .. L0_SEL = 1 */
  10481. /* .. ==> 0XF800070C[1:1] = 0x00000001U */
  10482. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10483. /* .. L1_SEL = 0 */
  10484. /* .. ==> 0XF800070C[2:2] = 0x00000000U */
  10485. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10486. /* .. L2_SEL = 0 */
  10487. /* .. ==> 0XF800070C[4:3] = 0x00000000U */
  10488. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10489. /* .. L3_SEL = 0 */
  10490. /* .. ==> 0XF800070C[7:5] = 0x00000000U */
  10491. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10492. /* .. Speed = 1 */
  10493. /* .. ==> 0XF800070C[8:8] = 0x00000001U */
  10494. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10495. /* .. IO_Type = 3 */
  10496. /* .. ==> 0XF800070C[11:9] = 0x00000003U */
  10497. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10498. /* .. PULLUP = 0 */
  10499. /* .. ==> 0XF800070C[12:12] = 0x00000000U */
  10500. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10501. /* .. DisableRcvr = 0 */
  10502. /* .. ==> 0XF800070C[13:13] = 0x00000000U */
  10503. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10504. /* .. */
  10505. EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
  10506. /* .. TRI_ENABLE = 0 */
  10507. /* .. ==> 0XF8000710[0:0] = 0x00000000U */
  10508. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10509. /* .. L0_SEL = 1 */
  10510. /* .. ==> 0XF8000710[1:1] = 0x00000001U */
  10511. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10512. /* .. L1_SEL = 0 */
  10513. /* .. ==> 0XF8000710[2:2] = 0x00000000U */
  10514. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10515. /* .. L2_SEL = 0 */
  10516. /* .. ==> 0XF8000710[4:3] = 0x00000000U */
  10517. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10518. /* .. L3_SEL = 0 */
  10519. /* .. ==> 0XF8000710[7:5] = 0x00000000U */
  10520. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10521. /* .. Speed = 1 */
  10522. /* .. ==> 0XF8000710[8:8] = 0x00000001U */
  10523. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10524. /* .. IO_Type = 3 */
  10525. /* .. ==> 0XF8000710[11:9] = 0x00000003U */
  10526. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10527. /* .. PULLUP = 0 */
  10528. /* .. ==> 0XF8000710[12:12] = 0x00000000U */
  10529. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10530. /* .. DisableRcvr = 0 */
  10531. /* .. ==> 0XF8000710[13:13] = 0x00000000U */
  10532. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10533. /* .. */
  10534. EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
  10535. /* .. TRI_ENABLE = 0 */
  10536. /* .. ==> 0XF8000714[0:0] = 0x00000000U */
  10537. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10538. /* .. L0_SEL = 1 */
  10539. /* .. ==> 0XF8000714[1:1] = 0x00000001U */
  10540. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10541. /* .. L1_SEL = 0 */
  10542. /* .. ==> 0XF8000714[2:2] = 0x00000000U */
  10543. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10544. /* .. L2_SEL = 0 */
  10545. /* .. ==> 0XF8000714[4:3] = 0x00000000U */
  10546. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10547. /* .. L3_SEL = 0 */
  10548. /* .. ==> 0XF8000714[7:5] = 0x00000000U */
  10549. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10550. /* .. Speed = 1 */
  10551. /* .. ==> 0XF8000714[8:8] = 0x00000001U */
  10552. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10553. /* .. IO_Type = 3 */
  10554. /* .. ==> 0XF8000714[11:9] = 0x00000003U */
  10555. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10556. /* .. PULLUP = 0 */
  10557. /* .. ==> 0XF8000714[12:12] = 0x00000000U */
  10558. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10559. /* .. DisableRcvr = 0 */
  10560. /* .. ==> 0XF8000714[13:13] = 0x00000000U */
  10561. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10562. /* .. */
  10563. EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
  10564. /* .. TRI_ENABLE = 0 */
  10565. /* .. ==> 0XF8000718[0:0] = 0x00000000U */
  10566. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10567. /* .. L0_SEL = 1 */
  10568. /* .. ==> 0XF8000718[1:1] = 0x00000001U */
  10569. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10570. /* .. L1_SEL = 0 */
  10571. /* .. ==> 0XF8000718[2:2] = 0x00000000U */
  10572. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10573. /* .. L2_SEL = 0 */
  10574. /* .. ==> 0XF8000718[4:3] = 0x00000000U */
  10575. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10576. /* .. L3_SEL = 0 */
  10577. /* .. ==> 0XF8000718[7:5] = 0x00000000U */
  10578. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10579. /* .. Speed = 1 */
  10580. /* .. ==> 0XF8000718[8:8] = 0x00000001U */
  10581. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10582. /* .. IO_Type = 3 */
  10583. /* .. ==> 0XF8000718[11:9] = 0x00000003U */
  10584. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10585. /* .. PULLUP = 0 */
  10586. /* .. ==> 0XF8000718[12:12] = 0x00000000U */
  10587. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10588. /* .. DisableRcvr = 0 */
  10589. /* .. ==> 0XF8000718[13:13] = 0x00000000U */
  10590. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10591. /* .. */
  10592. EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
  10593. /* .. TRI_ENABLE = 0 */
  10594. /* .. ==> 0XF800071C[0:0] = 0x00000000U */
  10595. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10596. /* .. L0_SEL = 0 */
  10597. /* .. ==> 0XF800071C[1:1] = 0x00000000U */
  10598. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10599. /* .. L1_SEL = 0 */
  10600. /* .. ==> 0XF800071C[2:2] = 0x00000000U */
  10601. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10602. /* .. L2_SEL = 0 */
  10603. /* .. ==> 0XF800071C[4:3] = 0x00000000U */
  10604. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10605. /* .. L3_SEL = 0 */
  10606. /* .. ==> 0XF800071C[7:5] = 0x00000000U */
  10607. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10608. /* .. Speed = 0 */
  10609. /* .. ==> 0XF800071C[8:8] = 0x00000000U */
  10610. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10611. /* .. IO_Type = 3 */
  10612. /* .. ==> 0XF800071C[11:9] = 0x00000003U */
  10613. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10614. /* .. PULLUP = 0 */
  10615. /* .. ==> 0XF800071C[12:12] = 0x00000000U */
  10616. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10617. /* .. DisableRcvr = 0 */
  10618. /* .. ==> 0XF800071C[13:13] = 0x00000000U */
  10619. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10620. /* .. */
  10621. EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
  10622. /* .. TRI_ENABLE = 0 */
  10623. /* .. ==> 0XF8000720[0:0] = 0x00000000U */
  10624. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10625. /* .. L0_SEL = 1 */
  10626. /* .. ==> 0XF8000720[1:1] = 0x00000001U */
  10627. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10628. /* .. L1_SEL = 0 */
  10629. /* .. ==> 0XF8000720[2:2] = 0x00000000U */
  10630. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10631. /* .. L2_SEL = 0 */
  10632. /* .. ==> 0XF8000720[4:3] = 0x00000000U */
  10633. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10634. /* .. L3_SEL = 0 */
  10635. /* .. ==> 0XF8000720[7:5] = 0x00000000U */
  10636. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10637. /* .. Speed = 1 */
  10638. /* .. ==> 0XF8000720[8:8] = 0x00000001U */
  10639. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10640. /* .. IO_Type = 3 */
  10641. /* .. ==> 0XF8000720[11:9] = 0x00000003U */
  10642. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10643. /* .. PULLUP = 0 */
  10644. /* .. ==> 0XF8000720[12:12] = 0x00000000U */
  10645. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10646. /* .. DisableRcvr = 0 */
  10647. /* .. ==> 0XF8000720[13:13] = 0x00000000U */
  10648. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10649. /* .. */
  10650. EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
  10651. /* .. TRI_ENABLE = 0 */
  10652. /* .. ==> 0XF8000724[0:0] = 0x00000000U */
  10653. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10654. /* .. L0_SEL = 0 */
  10655. /* .. ==> 0XF8000724[1:1] = 0x00000000U */
  10656. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10657. /* .. L1_SEL = 0 */
  10658. /* .. ==> 0XF8000724[2:2] = 0x00000000U */
  10659. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10660. /* .. L2_SEL = 0 */
  10661. /* .. ==> 0XF8000724[4:3] = 0x00000000U */
  10662. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10663. /* .. L3_SEL = 0 */
  10664. /* .. ==> 0XF8000724[7:5] = 0x00000000U */
  10665. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10666. /* .. Speed = 0 */
  10667. /* .. ==> 0XF8000724[8:8] = 0x00000000U */
  10668. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10669. /* .. IO_Type = 3 */
  10670. /* .. ==> 0XF8000724[11:9] = 0x00000003U */
  10671. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10672. /* .. PULLUP = 1 */
  10673. /* .. ==> 0XF8000724[12:12] = 0x00000001U */
  10674. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10675. /* .. DisableRcvr = 0 */
  10676. /* .. ==> 0XF8000724[13:13] = 0x00000000U */
  10677. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10678. /* .. */
  10679. EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
  10680. /* .. TRI_ENABLE = 0 */
  10681. /* .. ==> 0XF8000728[0:0] = 0x00000000U */
  10682. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10683. /* .. L0_SEL = 0 */
  10684. /* .. ==> 0XF8000728[1:1] = 0x00000000U */
  10685. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10686. /* .. L1_SEL = 0 */
  10687. /* .. ==> 0XF8000728[2:2] = 0x00000000U */
  10688. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10689. /* .. L2_SEL = 0 */
  10690. /* .. ==> 0XF8000728[4:3] = 0x00000000U */
  10691. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10692. /* .. L3_SEL = 0 */
  10693. /* .. ==> 0XF8000728[7:5] = 0x00000000U */
  10694. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10695. /* .. Speed = 0 */
  10696. /* .. ==> 0XF8000728[8:8] = 0x00000000U */
  10697. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10698. /* .. IO_Type = 3 */
  10699. /* .. ==> 0XF8000728[11:9] = 0x00000003U */
  10700. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10701. /* .. PULLUP = 1 */
  10702. /* .. ==> 0XF8000728[12:12] = 0x00000001U */
  10703. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10704. /* .. DisableRcvr = 0 */
  10705. /* .. ==> 0XF8000728[13:13] = 0x00000000U */
  10706. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10707. /* .. */
  10708. EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
  10709. /* .. TRI_ENABLE = 0 */
  10710. /* .. ==> 0XF800072C[0:0] = 0x00000000U */
  10711. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10712. /* .. L0_SEL = 0 */
  10713. /* .. ==> 0XF800072C[1:1] = 0x00000000U */
  10714. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10715. /* .. L1_SEL = 0 */
  10716. /* .. ==> 0XF800072C[2:2] = 0x00000000U */
  10717. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10718. /* .. L2_SEL = 0 */
  10719. /* .. ==> 0XF800072C[4:3] = 0x00000000U */
  10720. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10721. /* .. L3_SEL = 0 */
  10722. /* .. ==> 0XF800072C[7:5] = 0x00000000U */
  10723. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10724. /* .. Speed = 0 */
  10725. /* .. ==> 0XF800072C[8:8] = 0x00000000U */
  10726. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10727. /* .. IO_Type = 3 */
  10728. /* .. ==> 0XF800072C[11:9] = 0x00000003U */
  10729. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10730. /* .. PULLUP = 1 */
  10731. /* .. ==> 0XF800072C[12:12] = 0x00000001U */
  10732. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10733. /* .. DisableRcvr = 0 */
  10734. /* .. ==> 0XF800072C[13:13] = 0x00000000U */
  10735. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10736. /* .. */
  10737. EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
  10738. /* .. TRI_ENABLE = 0 */
  10739. /* .. ==> 0XF8000730[0:0] = 0x00000000U */
  10740. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10741. /* .. L0_SEL = 0 */
  10742. /* .. ==> 0XF8000730[1:1] = 0x00000000U */
  10743. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10744. /* .. L1_SEL = 0 */
  10745. /* .. ==> 0XF8000730[2:2] = 0x00000000U */
  10746. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10747. /* .. L2_SEL = 0 */
  10748. /* .. ==> 0XF8000730[4:3] = 0x00000000U */
  10749. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10750. /* .. L3_SEL = 0 */
  10751. /* .. ==> 0XF8000730[7:5] = 0x00000000U */
  10752. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10753. /* .. Speed = 0 */
  10754. /* .. ==> 0XF8000730[8:8] = 0x00000000U */
  10755. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10756. /* .. IO_Type = 3 */
  10757. /* .. ==> 0XF8000730[11:9] = 0x00000003U */
  10758. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10759. /* .. PULLUP = 1 */
  10760. /* .. ==> 0XF8000730[12:12] = 0x00000001U */
  10761. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10762. /* .. DisableRcvr = 0 */
  10763. /* .. ==> 0XF8000730[13:13] = 0x00000000U */
  10764. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10765. /* .. */
  10766. EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
  10767. /* .. TRI_ENABLE = 0 */
  10768. /* .. ==> 0XF8000734[0:0] = 0x00000000U */
  10769. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10770. /* .. L0_SEL = 0 */
  10771. /* .. ==> 0XF8000734[1:1] = 0x00000000U */
  10772. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10773. /* .. L1_SEL = 0 */
  10774. /* .. ==> 0XF8000734[2:2] = 0x00000000U */
  10775. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10776. /* .. L2_SEL = 0 */
  10777. /* .. ==> 0XF8000734[4:3] = 0x00000000U */
  10778. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10779. /* .. L3_SEL = 0 */
  10780. /* .. ==> 0XF8000734[7:5] = 0x00000000U */
  10781. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10782. /* .. Speed = 0 */
  10783. /* .. ==> 0XF8000734[8:8] = 0x00000000U */
  10784. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10785. /* .. IO_Type = 3 */
  10786. /* .. ==> 0XF8000734[11:9] = 0x00000003U */
  10787. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10788. /* .. PULLUP = 1 */
  10789. /* .. ==> 0XF8000734[12:12] = 0x00000001U */
  10790. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10791. /* .. DisableRcvr = 0 */
  10792. /* .. ==> 0XF8000734[13:13] = 0x00000000U */
  10793. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10794. /* .. */
  10795. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
  10796. /* .. TRI_ENABLE = 0 */
  10797. /* .. ==> 0XF8000738[0:0] = 0x00000000U */
  10798. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10799. /* .. L0_SEL = 0 */
  10800. /* .. ==> 0XF8000738[1:1] = 0x00000000U */
  10801. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10802. /* .. L1_SEL = 0 */
  10803. /* .. ==> 0XF8000738[2:2] = 0x00000000U */
  10804. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10805. /* .. L2_SEL = 0 */
  10806. /* .. ==> 0XF8000738[4:3] = 0x00000000U */
  10807. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10808. /* .. L3_SEL = 0 */
  10809. /* .. ==> 0XF8000738[7:5] = 0x00000000U */
  10810. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10811. /* .. Speed = 0 */
  10812. /* .. ==> 0XF8000738[8:8] = 0x00000000U */
  10813. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10814. /* .. IO_Type = 3 */
  10815. /* .. ==> 0XF8000738[11:9] = 0x00000003U */
  10816. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10817. /* .. PULLUP = 1 */
  10818. /* .. ==> 0XF8000738[12:12] = 0x00000001U */
  10819. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10820. /* .. DisableRcvr = 0 */
  10821. /* .. ==> 0XF8000738[13:13] = 0x00000000U */
  10822. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10823. /* .. */
  10824. EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
  10825. /* .. TRI_ENABLE = 0 */
  10826. /* .. ==> 0XF800073C[0:0] = 0x00000000U */
  10827. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10828. /* .. L0_SEL = 0 */
  10829. /* .. ==> 0XF800073C[1:1] = 0x00000000U */
  10830. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  10831. /* .. L1_SEL = 0 */
  10832. /* .. ==> 0XF800073C[2:2] = 0x00000000U */
  10833. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10834. /* .. L2_SEL = 0 */
  10835. /* .. ==> 0XF800073C[4:3] = 0x00000000U */
  10836. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10837. /* .. L3_SEL = 0 */
  10838. /* .. ==> 0XF800073C[7:5] = 0x00000000U */
  10839. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10840. /* .. Speed = 0 */
  10841. /* .. ==> 0XF800073C[8:8] = 0x00000000U */
  10842. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  10843. /* .. IO_Type = 3 */
  10844. /* .. ==> 0XF800073C[11:9] = 0x00000003U */
  10845. /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
  10846. /* .. PULLUP = 1 */
  10847. /* .. ==> 0XF800073C[12:12] = 0x00000001U */
  10848. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  10849. /* .. DisableRcvr = 0 */
  10850. /* .. ==> 0XF800073C[13:13] = 0x00000000U */
  10851. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  10852. /* .. */
  10853. EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
  10854. /* .. TRI_ENABLE = 0 */
  10855. /* .. ==> 0XF8000740[0:0] = 0x00000000U */
  10856. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10857. /* .. L0_SEL = 1 */
  10858. /* .. ==> 0XF8000740[1:1] = 0x00000001U */
  10859. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10860. /* .. L1_SEL = 0 */
  10861. /* .. ==> 0XF8000740[2:2] = 0x00000000U */
  10862. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10863. /* .. L2_SEL = 0 */
  10864. /* .. ==> 0XF8000740[4:3] = 0x00000000U */
  10865. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10866. /* .. L3_SEL = 0 */
  10867. /* .. ==> 0XF8000740[7:5] = 0x00000000U */
  10868. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10869. /* .. Speed = 1 */
  10870. /* .. ==> 0XF8000740[8:8] = 0x00000001U */
  10871. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10872. /* .. IO_Type = 4 */
  10873. /* .. ==> 0XF8000740[11:9] = 0x00000004U */
  10874. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  10875. /* .. PULLUP = 0 */
  10876. /* .. ==> 0XF8000740[12:12] = 0x00000000U */
  10877. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10878. /* .. DisableRcvr = 1 */
  10879. /* .. ==> 0XF8000740[13:13] = 0x00000001U */
  10880. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  10881. /* .. */
  10882. EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
  10883. /* .. TRI_ENABLE = 0 */
  10884. /* .. ==> 0XF8000744[0:0] = 0x00000000U */
  10885. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10886. /* .. L0_SEL = 1 */
  10887. /* .. ==> 0XF8000744[1:1] = 0x00000001U */
  10888. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10889. /* .. L1_SEL = 0 */
  10890. /* .. ==> 0XF8000744[2:2] = 0x00000000U */
  10891. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10892. /* .. L2_SEL = 0 */
  10893. /* .. ==> 0XF8000744[4:3] = 0x00000000U */
  10894. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10895. /* .. L3_SEL = 0 */
  10896. /* .. ==> 0XF8000744[7:5] = 0x00000000U */
  10897. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10898. /* .. Speed = 1 */
  10899. /* .. ==> 0XF8000744[8:8] = 0x00000001U */
  10900. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10901. /* .. IO_Type = 4 */
  10902. /* .. ==> 0XF8000744[11:9] = 0x00000004U */
  10903. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  10904. /* .. PULLUP = 0 */
  10905. /* .. ==> 0XF8000744[12:12] = 0x00000000U */
  10906. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10907. /* .. DisableRcvr = 1 */
  10908. /* .. ==> 0XF8000744[13:13] = 0x00000001U */
  10909. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  10910. /* .. */
  10911. EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
  10912. /* .. TRI_ENABLE = 0 */
  10913. /* .. ==> 0XF8000748[0:0] = 0x00000000U */
  10914. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10915. /* .. L0_SEL = 1 */
  10916. /* .. ==> 0XF8000748[1:1] = 0x00000001U */
  10917. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10918. /* .. L1_SEL = 0 */
  10919. /* .. ==> 0XF8000748[2:2] = 0x00000000U */
  10920. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10921. /* .. L2_SEL = 0 */
  10922. /* .. ==> 0XF8000748[4:3] = 0x00000000U */
  10923. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10924. /* .. L3_SEL = 0 */
  10925. /* .. ==> 0XF8000748[7:5] = 0x00000000U */
  10926. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10927. /* .. Speed = 1 */
  10928. /* .. ==> 0XF8000748[8:8] = 0x00000001U */
  10929. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10930. /* .. IO_Type = 4 */
  10931. /* .. ==> 0XF8000748[11:9] = 0x00000004U */
  10932. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  10933. /* .. PULLUP = 0 */
  10934. /* .. ==> 0XF8000748[12:12] = 0x00000000U */
  10935. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10936. /* .. DisableRcvr = 1 */
  10937. /* .. ==> 0XF8000748[13:13] = 0x00000001U */
  10938. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  10939. /* .. */
  10940. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
  10941. /* .. TRI_ENABLE = 0 */
  10942. /* .. ==> 0XF800074C[0:0] = 0x00000000U */
  10943. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10944. /* .. L0_SEL = 1 */
  10945. /* .. ==> 0XF800074C[1:1] = 0x00000001U */
  10946. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10947. /* .. L1_SEL = 0 */
  10948. /* .. ==> 0XF800074C[2:2] = 0x00000000U */
  10949. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10950. /* .. L2_SEL = 0 */
  10951. /* .. ==> 0XF800074C[4:3] = 0x00000000U */
  10952. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10953. /* .. L3_SEL = 0 */
  10954. /* .. ==> 0XF800074C[7:5] = 0x00000000U */
  10955. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10956. /* .. Speed = 1 */
  10957. /* .. ==> 0XF800074C[8:8] = 0x00000001U */
  10958. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10959. /* .. IO_Type = 4 */
  10960. /* .. ==> 0XF800074C[11:9] = 0x00000004U */
  10961. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  10962. /* .. PULLUP = 0 */
  10963. /* .. ==> 0XF800074C[12:12] = 0x00000000U */
  10964. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10965. /* .. DisableRcvr = 1 */
  10966. /* .. ==> 0XF800074C[13:13] = 0x00000001U */
  10967. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  10968. /* .. */
  10969. EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
  10970. /* .. TRI_ENABLE = 0 */
  10971. /* .. ==> 0XF8000750[0:0] = 0x00000000U */
  10972. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  10973. /* .. L0_SEL = 1 */
  10974. /* .. ==> 0XF8000750[1:1] = 0x00000001U */
  10975. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  10976. /* .. L1_SEL = 0 */
  10977. /* .. ==> 0XF8000750[2:2] = 0x00000000U */
  10978. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  10979. /* .. L2_SEL = 0 */
  10980. /* .. ==> 0XF8000750[4:3] = 0x00000000U */
  10981. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  10982. /* .. L3_SEL = 0 */
  10983. /* .. ==> 0XF8000750[7:5] = 0x00000000U */
  10984. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  10985. /* .. Speed = 1 */
  10986. /* .. ==> 0XF8000750[8:8] = 0x00000001U */
  10987. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  10988. /* .. IO_Type = 4 */
  10989. /* .. ==> 0XF8000750[11:9] = 0x00000004U */
  10990. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  10991. /* .. PULLUP = 0 */
  10992. /* .. ==> 0XF8000750[12:12] = 0x00000000U */
  10993. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  10994. /* .. DisableRcvr = 1 */
  10995. /* .. ==> 0XF8000750[13:13] = 0x00000001U */
  10996. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  10997. /* .. */
  10998. EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
  10999. /* .. TRI_ENABLE = 0 */
  11000. /* .. ==> 0XF8000754[0:0] = 0x00000000U */
  11001. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11002. /* .. L0_SEL = 1 */
  11003. /* .. ==> 0XF8000754[1:1] = 0x00000001U */
  11004. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  11005. /* .. L1_SEL = 0 */
  11006. /* .. ==> 0XF8000754[2:2] = 0x00000000U */
  11007. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11008. /* .. L2_SEL = 0 */
  11009. /* .. ==> 0XF8000754[4:3] = 0x00000000U */
  11010. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11011. /* .. L3_SEL = 0 */
  11012. /* .. ==> 0XF8000754[7:5] = 0x00000000U */
  11013. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11014. /* .. Speed = 1 */
  11015. /* .. ==> 0XF8000754[8:8] = 0x00000001U */
  11016. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11017. /* .. IO_Type = 4 */
  11018. /* .. ==> 0XF8000754[11:9] = 0x00000004U */
  11019. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  11020. /* .. PULLUP = 0 */
  11021. /* .. ==> 0XF8000754[12:12] = 0x00000000U */
  11022. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11023. /* .. DisableRcvr = 1 */
  11024. /* .. ==> 0XF8000754[13:13] = 0x00000001U */
  11025. /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
  11026. /* .. */
  11027. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
  11028. /* .. TRI_ENABLE = 1 */
  11029. /* .. ==> 0XF8000758[0:0] = 0x00000001U */
  11030. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11031. /* .. L0_SEL = 1 */
  11032. /* .. ==> 0XF8000758[1:1] = 0x00000001U */
  11033. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  11034. /* .. L1_SEL = 0 */
  11035. /* .. ==> 0XF8000758[2:2] = 0x00000000U */
  11036. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11037. /* .. L2_SEL = 0 */
  11038. /* .. ==> 0XF8000758[4:3] = 0x00000000U */
  11039. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11040. /* .. L3_SEL = 0 */
  11041. /* .. ==> 0XF8000758[7:5] = 0x00000000U */
  11042. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11043. /* .. Speed = 1 */
  11044. /* .. ==> 0XF8000758[8:8] = 0x00000001U */
  11045. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11046. /* .. IO_Type = 4 */
  11047. /* .. ==> 0XF8000758[11:9] = 0x00000004U */
  11048. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  11049. /* .. PULLUP = 0 */
  11050. /* .. ==> 0XF8000758[12:12] = 0x00000000U */
  11051. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11052. /* .. DisableRcvr = 0 */
  11053. /* .. ==> 0XF8000758[13:13] = 0x00000000U */
  11054. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11055. /* .. */
  11056. EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
  11057. /* .. TRI_ENABLE = 1 */
  11058. /* .. ==> 0XF800075C[0:0] = 0x00000001U */
  11059. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11060. /* .. L0_SEL = 1 */
  11061. /* .. ==> 0XF800075C[1:1] = 0x00000001U */
  11062. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  11063. /* .. L1_SEL = 0 */
  11064. /* .. ==> 0XF800075C[2:2] = 0x00000000U */
  11065. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11066. /* .. L2_SEL = 0 */
  11067. /* .. ==> 0XF800075C[4:3] = 0x00000000U */
  11068. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11069. /* .. L3_SEL = 0 */
  11070. /* .. ==> 0XF800075C[7:5] = 0x00000000U */
  11071. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11072. /* .. Speed = 1 */
  11073. /* .. ==> 0XF800075C[8:8] = 0x00000001U */
  11074. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11075. /* .. IO_Type = 4 */
  11076. /* .. ==> 0XF800075C[11:9] = 0x00000004U */
  11077. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  11078. /* .. PULLUP = 0 */
  11079. /* .. ==> 0XF800075C[12:12] = 0x00000000U */
  11080. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11081. /* .. DisableRcvr = 0 */
  11082. /* .. ==> 0XF800075C[13:13] = 0x00000000U */
  11083. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11084. /* .. */
  11085. EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
  11086. /* .. TRI_ENABLE = 1 */
  11087. /* .. ==> 0XF8000760[0:0] = 0x00000001U */
  11088. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11089. /* .. L0_SEL = 1 */
  11090. /* .. ==> 0XF8000760[1:1] = 0x00000001U */
  11091. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  11092. /* .. L1_SEL = 0 */
  11093. /* .. ==> 0XF8000760[2:2] = 0x00000000U */
  11094. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11095. /* .. L2_SEL = 0 */
  11096. /* .. ==> 0XF8000760[4:3] = 0x00000000U */
  11097. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11098. /* .. L3_SEL = 0 */
  11099. /* .. ==> 0XF8000760[7:5] = 0x00000000U */
  11100. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11101. /* .. Speed = 1 */
  11102. /* .. ==> 0XF8000760[8:8] = 0x00000001U */
  11103. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11104. /* .. IO_Type = 4 */
  11105. /* .. ==> 0XF8000760[11:9] = 0x00000004U */
  11106. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  11107. /* .. PULLUP = 0 */
  11108. /* .. ==> 0XF8000760[12:12] = 0x00000000U */
  11109. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11110. /* .. DisableRcvr = 0 */
  11111. /* .. ==> 0XF8000760[13:13] = 0x00000000U */
  11112. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11113. /* .. */
  11114. EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
  11115. /* .. TRI_ENABLE = 1 */
  11116. /* .. ==> 0XF8000764[0:0] = 0x00000001U */
  11117. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11118. /* .. L0_SEL = 1 */
  11119. /* .. ==> 0XF8000764[1:1] = 0x00000001U */
  11120. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  11121. /* .. L1_SEL = 0 */
  11122. /* .. ==> 0XF8000764[2:2] = 0x00000000U */
  11123. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11124. /* .. L2_SEL = 0 */
  11125. /* .. ==> 0XF8000764[4:3] = 0x00000000U */
  11126. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11127. /* .. L3_SEL = 0 */
  11128. /* .. ==> 0XF8000764[7:5] = 0x00000000U */
  11129. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11130. /* .. Speed = 1 */
  11131. /* .. ==> 0XF8000764[8:8] = 0x00000001U */
  11132. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11133. /* .. IO_Type = 4 */
  11134. /* .. ==> 0XF8000764[11:9] = 0x00000004U */
  11135. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  11136. /* .. PULLUP = 0 */
  11137. /* .. ==> 0XF8000764[12:12] = 0x00000000U */
  11138. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11139. /* .. DisableRcvr = 0 */
  11140. /* .. ==> 0XF8000764[13:13] = 0x00000000U */
  11141. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11142. /* .. */
  11143. EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
  11144. /* .. TRI_ENABLE = 1 */
  11145. /* .. ==> 0XF8000768[0:0] = 0x00000001U */
  11146. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11147. /* .. L0_SEL = 1 */
  11148. /* .. ==> 0XF8000768[1:1] = 0x00000001U */
  11149. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  11150. /* .. L1_SEL = 0 */
  11151. /* .. ==> 0XF8000768[2:2] = 0x00000000U */
  11152. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11153. /* .. L2_SEL = 0 */
  11154. /* .. ==> 0XF8000768[4:3] = 0x00000000U */
  11155. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11156. /* .. L3_SEL = 0 */
  11157. /* .. ==> 0XF8000768[7:5] = 0x00000000U */
  11158. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11159. /* .. Speed = 1 */
  11160. /* .. ==> 0XF8000768[8:8] = 0x00000001U */
  11161. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11162. /* .. IO_Type = 4 */
  11163. /* .. ==> 0XF8000768[11:9] = 0x00000004U */
  11164. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  11165. /* .. PULLUP = 0 */
  11166. /* .. ==> 0XF8000768[12:12] = 0x00000000U */
  11167. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11168. /* .. DisableRcvr = 0 */
  11169. /* .. ==> 0XF8000768[13:13] = 0x00000000U */
  11170. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11171. /* .. */
  11172. EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
  11173. /* .. TRI_ENABLE = 1 */
  11174. /* .. ==> 0XF800076C[0:0] = 0x00000001U */
  11175. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11176. /* .. L0_SEL = 1 */
  11177. /* .. ==> 0XF800076C[1:1] = 0x00000001U */
  11178. /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
  11179. /* .. L1_SEL = 0 */
  11180. /* .. ==> 0XF800076C[2:2] = 0x00000000U */
  11181. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11182. /* .. L2_SEL = 0 */
  11183. /* .. ==> 0XF800076C[4:3] = 0x00000000U */
  11184. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11185. /* .. L3_SEL = 0 */
  11186. /* .. ==> 0XF800076C[7:5] = 0x00000000U */
  11187. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11188. /* .. Speed = 1 */
  11189. /* .. ==> 0XF800076C[8:8] = 0x00000001U */
  11190. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11191. /* .. IO_Type = 4 */
  11192. /* .. ==> 0XF800076C[11:9] = 0x00000004U */
  11193. /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
  11194. /* .. PULLUP = 0 */
  11195. /* .. ==> 0XF800076C[12:12] = 0x00000000U */
  11196. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11197. /* .. DisableRcvr = 0 */
  11198. /* .. ==> 0XF800076C[13:13] = 0x00000000U */
  11199. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11200. /* .. */
  11201. EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
  11202. /* .. TRI_ENABLE = 0 */
  11203. /* .. ==> 0XF8000770[0:0] = 0x00000000U */
  11204. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11205. /* .. L0_SEL = 0 */
  11206. /* .. ==> 0XF8000770[1:1] = 0x00000000U */
  11207. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11208. /* .. L1_SEL = 1 */
  11209. /* .. ==> 0XF8000770[2:2] = 0x00000001U */
  11210. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11211. /* .. L2_SEL = 0 */
  11212. /* .. ==> 0XF8000770[4:3] = 0x00000000U */
  11213. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11214. /* .. L3_SEL = 0 */
  11215. /* .. ==> 0XF8000770[7:5] = 0x00000000U */
  11216. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11217. /* .. Speed = 1 */
  11218. /* .. ==> 0XF8000770[8:8] = 0x00000001U */
  11219. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11220. /* .. IO_Type = 1 */
  11221. /* .. ==> 0XF8000770[11:9] = 0x00000001U */
  11222. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11223. /* .. PULLUP = 0 */
  11224. /* .. ==> 0XF8000770[12:12] = 0x00000000U */
  11225. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11226. /* .. DisableRcvr = 0 */
  11227. /* .. ==> 0XF8000770[13:13] = 0x00000000U */
  11228. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11229. /* .. */
  11230. EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
  11231. /* .. TRI_ENABLE = 1 */
  11232. /* .. ==> 0XF8000774[0:0] = 0x00000001U */
  11233. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11234. /* .. L0_SEL = 0 */
  11235. /* .. ==> 0XF8000774[1:1] = 0x00000000U */
  11236. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11237. /* .. L1_SEL = 1 */
  11238. /* .. ==> 0XF8000774[2:2] = 0x00000001U */
  11239. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11240. /* .. L2_SEL = 0 */
  11241. /* .. ==> 0XF8000774[4:3] = 0x00000000U */
  11242. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11243. /* .. L3_SEL = 0 */
  11244. /* .. ==> 0XF8000774[7:5] = 0x00000000U */
  11245. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11246. /* .. Speed = 1 */
  11247. /* .. ==> 0XF8000774[8:8] = 0x00000001U */
  11248. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11249. /* .. IO_Type = 1 */
  11250. /* .. ==> 0XF8000774[11:9] = 0x00000001U */
  11251. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11252. /* .. PULLUP = 0 */
  11253. /* .. ==> 0XF8000774[12:12] = 0x00000000U */
  11254. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11255. /* .. DisableRcvr = 0 */
  11256. /* .. ==> 0XF8000774[13:13] = 0x00000000U */
  11257. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11258. /* .. */
  11259. EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
  11260. /* .. TRI_ENABLE = 0 */
  11261. /* .. ==> 0XF8000778[0:0] = 0x00000000U */
  11262. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11263. /* .. L0_SEL = 0 */
  11264. /* .. ==> 0XF8000778[1:1] = 0x00000000U */
  11265. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11266. /* .. L1_SEL = 1 */
  11267. /* .. ==> 0XF8000778[2:2] = 0x00000001U */
  11268. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11269. /* .. L2_SEL = 0 */
  11270. /* .. ==> 0XF8000778[4:3] = 0x00000000U */
  11271. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11272. /* .. L3_SEL = 0 */
  11273. /* .. ==> 0XF8000778[7:5] = 0x00000000U */
  11274. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11275. /* .. Speed = 1 */
  11276. /* .. ==> 0XF8000778[8:8] = 0x00000001U */
  11277. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11278. /* .. IO_Type = 1 */
  11279. /* .. ==> 0XF8000778[11:9] = 0x00000001U */
  11280. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11281. /* .. PULLUP = 0 */
  11282. /* .. ==> 0XF8000778[12:12] = 0x00000000U */
  11283. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11284. /* .. DisableRcvr = 0 */
  11285. /* .. ==> 0XF8000778[13:13] = 0x00000000U */
  11286. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11287. /* .. */
  11288. EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
  11289. /* .. TRI_ENABLE = 1 */
  11290. /* .. ==> 0XF800077C[0:0] = 0x00000001U */
  11291. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11292. /* .. L0_SEL = 0 */
  11293. /* .. ==> 0XF800077C[1:1] = 0x00000000U */
  11294. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11295. /* .. L1_SEL = 1 */
  11296. /* .. ==> 0XF800077C[2:2] = 0x00000001U */
  11297. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11298. /* .. L2_SEL = 0 */
  11299. /* .. ==> 0XF800077C[4:3] = 0x00000000U */
  11300. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11301. /* .. L3_SEL = 0 */
  11302. /* .. ==> 0XF800077C[7:5] = 0x00000000U */
  11303. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11304. /* .. Speed = 1 */
  11305. /* .. ==> 0XF800077C[8:8] = 0x00000001U */
  11306. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11307. /* .. IO_Type = 1 */
  11308. /* .. ==> 0XF800077C[11:9] = 0x00000001U */
  11309. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11310. /* .. PULLUP = 0 */
  11311. /* .. ==> 0XF800077C[12:12] = 0x00000000U */
  11312. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11313. /* .. DisableRcvr = 0 */
  11314. /* .. ==> 0XF800077C[13:13] = 0x00000000U */
  11315. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11316. /* .. */
  11317. EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
  11318. /* .. TRI_ENABLE = 0 */
  11319. /* .. ==> 0XF8000780[0:0] = 0x00000000U */
  11320. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11321. /* .. L0_SEL = 0 */
  11322. /* .. ==> 0XF8000780[1:1] = 0x00000000U */
  11323. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11324. /* .. L1_SEL = 1 */
  11325. /* .. ==> 0XF8000780[2:2] = 0x00000001U */
  11326. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11327. /* .. L2_SEL = 0 */
  11328. /* .. ==> 0XF8000780[4:3] = 0x00000000U */
  11329. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11330. /* .. L3_SEL = 0 */
  11331. /* .. ==> 0XF8000780[7:5] = 0x00000000U */
  11332. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11333. /* .. Speed = 1 */
  11334. /* .. ==> 0XF8000780[8:8] = 0x00000001U */
  11335. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11336. /* .. IO_Type = 1 */
  11337. /* .. ==> 0XF8000780[11:9] = 0x00000001U */
  11338. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11339. /* .. PULLUP = 0 */
  11340. /* .. ==> 0XF8000780[12:12] = 0x00000000U */
  11341. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11342. /* .. DisableRcvr = 0 */
  11343. /* .. ==> 0XF8000780[13:13] = 0x00000000U */
  11344. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11345. /* .. */
  11346. EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
  11347. /* .. TRI_ENABLE = 0 */
  11348. /* .. ==> 0XF8000784[0:0] = 0x00000000U */
  11349. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11350. /* .. L0_SEL = 0 */
  11351. /* .. ==> 0XF8000784[1:1] = 0x00000000U */
  11352. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11353. /* .. L1_SEL = 1 */
  11354. /* .. ==> 0XF8000784[2:2] = 0x00000001U */
  11355. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11356. /* .. L2_SEL = 0 */
  11357. /* .. ==> 0XF8000784[4:3] = 0x00000000U */
  11358. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11359. /* .. L3_SEL = 0 */
  11360. /* .. ==> 0XF8000784[7:5] = 0x00000000U */
  11361. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11362. /* .. Speed = 1 */
  11363. /* .. ==> 0XF8000784[8:8] = 0x00000001U */
  11364. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11365. /* .. IO_Type = 1 */
  11366. /* .. ==> 0XF8000784[11:9] = 0x00000001U */
  11367. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11368. /* .. PULLUP = 0 */
  11369. /* .. ==> 0XF8000784[12:12] = 0x00000000U */
  11370. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11371. /* .. DisableRcvr = 0 */
  11372. /* .. ==> 0XF8000784[13:13] = 0x00000000U */
  11373. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11374. /* .. */
  11375. EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
  11376. /* .. TRI_ENABLE = 0 */
  11377. /* .. ==> 0XF8000788[0:0] = 0x00000000U */
  11378. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11379. /* .. L0_SEL = 0 */
  11380. /* .. ==> 0XF8000788[1:1] = 0x00000000U */
  11381. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11382. /* .. L1_SEL = 1 */
  11383. /* .. ==> 0XF8000788[2:2] = 0x00000001U */
  11384. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11385. /* .. L2_SEL = 0 */
  11386. /* .. ==> 0XF8000788[4:3] = 0x00000000U */
  11387. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11388. /* .. L3_SEL = 0 */
  11389. /* .. ==> 0XF8000788[7:5] = 0x00000000U */
  11390. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11391. /* .. Speed = 1 */
  11392. /* .. ==> 0XF8000788[8:8] = 0x00000001U */
  11393. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11394. /* .. IO_Type = 1 */
  11395. /* .. ==> 0XF8000788[11:9] = 0x00000001U */
  11396. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11397. /* .. PULLUP = 0 */
  11398. /* .. ==> 0XF8000788[12:12] = 0x00000000U */
  11399. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11400. /* .. DisableRcvr = 0 */
  11401. /* .. ==> 0XF8000788[13:13] = 0x00000000U */
  11402. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11403. /* .. */
  11404. EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
  11405. /* .. TRI_ENABLE = 0 */
  11406. /* .. ==> 0XF800078C[0:0] = 0x00000000U */
  11407. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11408. /* .. L0_SEL = 0 */
  11409. /* .. ==> 0XF800078C[1:1] = 0x00000000U */
  11410. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11411. /* .. L1_SEL = 1 */
  11412. /* .. ==> 0XF800078C[2:2] = 0x00000001U */
  11413. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11414. /* .. L2_SEL = 0 */
  11415. /* .. ==> 0XF800078C[4:3] = 0x00000000U */
  11416. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11417. /* .. L3_SEL = 0 */
  11418. /* .. ==> 0XF800078C[7:5] = 0x00000000U */
  11419. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11420. /* .. Speed = 1 */
  11421. /* .. ==> 0XF800078C[8:8] = 0x00000001U */
  11422. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11423. /* .. IO_Type = 1 */
  11424. /* .. ==> 0XF800078C[11:9] = 0x00000001U */
  11425. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11426. /* .. PULLUP = 0 */
  11427. /* .. ==> 0XF800078C[12:12] = 0x00000000U */
  11428. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11429. /* .. DisableRcvr = 0 */
  11430. /* .. ==> 0XF800078C[13:13] = 0x00000000U */
  11431. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11432. /* .. */
  11433. EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
  11434. /* .. TRI_ENABLE = 1 */
  11435. /* .. ==> 0XF8000790[0:0] = 0x00000001U */
  11436. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11437. /* .. L0_SEL = 0 */
  11438. /* .. ==> 0XF8000790[1:1] = 0x00000000U */
  11439. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11440. /* .. L1_SEL = 1 */
  11441. /* .. ==> 0XF8000790[2:2] = 0x00000001U */
  11442. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11443. /* .. L2_SEL = 0 */
  11444. /* .. ==> 0XF8000790[4:3] = 0x00000000U */
  11445. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11446. /* .. L3_SEL = 0 */
  11447. /* .. ==> 0XF8000790[7:5] = 0x00000000U */
  11448. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11449. /* .. Speed = 1 */
  11450. /* .. ==> 0XF8000790[8:8] = 0x00000001U */
  11451. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11452. /* .. IO_Type = 1 */
  11453. /* .. ==> 0XF8000790[11:9] = 0x00000001U */
  11454. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11455. /* .. PULLUP = 0 */
  11456. /* .. ==> 0XF8000790[12:12] = 0x00000000U */
  11457. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11458. /* .. DisableRcvr = 0 */
  11459. /* .. ==> 0XF8000790[13:13] = 0x00000000U */
  11460. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11461. /* .. */
  11462. EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
  11463. /* .. TRI_ENABLE = 0 */
  11464. /* .. ==> 0XF8000794[0:0] = 0x00000000U */
  11465. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11466. /* .. L0_SEL = 0 */
  11467. /* .. ==> 0XF8000794[1:1] = 0x00000000U */
  11468. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11469. /* .. L1_SEL = 1 */
  11470. /* .. ==> 0XF8000794[2:2] = 0x00000001U */
  11471. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11472. /* .. L2_SEL = 0 */
  11473. /* .. ==> 0XF8000794[4:3] = 0x00000000U */
  11474. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11475. /* .. L3_SEL = 0 */
  11476. /* .. ==> 0XF8000794[7:5] = 0x00000000U */
  11477. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11478. /* .. Speed = 1 */
  11479. /* .. ==> 0XF8000794[8:8] = 0x00000001U */
  11480. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11481. /* .. IO_Type = 1 */
  11482. /* .. ==> 0XF8000794[11:9] = 0x00000001U */
  11483. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11484. /* .. PULLUP = 0 */
  11485. /* .. ==> 0XF8000794[12:12] = 0x00000000U */
  11486. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11487. /* .. DisableRcvr = 0 */
  11488. /* .. ==> 0XF8000794[13:13] = 0x00000000U */
  11489. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11490. /* .. */
  11491. EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
  11492. /* .. TRI_ENABLE = 0 */
  11493. /* .. ==> 0XF8000798[0:0] = 0x00000000U */
  11494. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11495. /* .. L0_SEL = 0 */
  11496. /* .. ==> 0XF8000798[1:1] = 0x00000000U */
  11497. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11498. /* .. L1_SEL = 1 */
  11499. /* .. ==> 0XF8000798[2:2] = 0x00000001U */
  11500. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11501. /* .. L2_SEL = 0 */
  11502. /* .. ==> 0XF8000798[4:3] = 0x00000000U */
  11503. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11504. /* .. L3_SEL = 0 */
  11505. /* .. ==> 0XF8000798[7:5] = 0x00000000U */
  11506. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11507. /* .. Speed = 1 */
  11508. /* .. ==> 0XF8000798[8:8] = 0x00000001U */
  11509. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11510. /* .. IO_Type = 1 */
  11511. /* .. ==> 0XF8000798[11:9] = 0x00000001U */
  11512. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11513. /* .. PULLUP = 0 */
  11514. /* .. ==> 0XF8000798[12:12] = 0x00000000U */
  11515. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11516. /* .. DisableRcvr = 0 */
  11517. /* .. ==> 0XF8000798[13:13] = 0x00000000U */
  11518. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11519. /* .. */
  11520. EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
  11521. /* .. TRI_ENABLE = 0 */
  11522. /* .. ==> 0XF800079C[0:0] = 0x00000000U */
  11523. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11524. /* .. L0_SEL = 0 */
  11525. /* .. ==> 0XF800079C[1:1] = 0x00000000U */
  11526. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11527. /* .. L1_SEL = 1 */
  11528. /* .. ==> 0XF800079C[2:2] = 0x00000001U */
  11529. /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
  11530. /* .. L2_SEL = 0 */
  11531. /* .. ==> 0XF800079C[4:3] = 0x00000000U */
  11532. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11533. /* .. L3_SEL = 0 */
  11534. /* .. ==> 0XF800079C[7:5] = 0x00000000U */
  11535. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11536. /* .. Speed = 1 */
  11537. /* .. ==> 0XF800079C[8:8] = 0x00000001U */
  11538. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11539. /* .. IO_Type = 1 */
  11540. /* .. ==> 0XF800079C[11:9] = 0x00000001U */
  11541. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11542. /* .. PULLUP = 0 */
  11543. /* .. ==> 0XF800079C[12:12] = 0x00000000U */
  11544. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11545. /* .. DisableRcvr = 0 */
  11546. /* .. ==> 0XF800079C[13:13] = 0x00000000U */
  11547. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11548. /* .. */
  11549. EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
  11550. /* .. TRI_ENABLE = 0 */
  11551. /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
  11552. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11553. /* .. L0_SEL = 0 */
  11554. /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
  11555. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11556. /* .. L1_SEL = 0 */
  11557. /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
  11558. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11559. /* .. L2_SEL = 0 */
  11560. /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
  11561. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11562. /* .. L3_SEL = 4 */
  11563. /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
  11564. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11565. /* .. Speed = 1 */
  11566. /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
  11567. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11568. /* .. IO_Type = 1 */
  11569. /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
  11570. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11571. /* .. PULLUP = 0 */
  11572. /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
  11573. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11574. /* .. DisableRcvr = 0 */
  11575. /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
  11576. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11577. /* .. */
  11578. EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
  11579. /* .. TRI_ENABLE = 0 */
  11580. /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
  11581. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11582. /* .. L0_SEL = 0 */
  11583. /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
  11584. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11585. /* .. L1_SEL = 0 */
  11586. /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
  11587. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11588. /* .. L2_SEL = 0 */
  11589. /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
  11590. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11591. /* .. L3_SEL = 4 */
  11592. /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
  11593. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11594. /* .. Speed = 1 */
  11595. /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
  11596. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11597. /* .. IO_Type = 1 */
  11598. /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
  11599. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11600. /* .. PULLUP = 0 */
  11601. /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
  11602. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11603. /* .. DisableRcvr = 0 */
  11604. /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
  11605. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11606. /* .. */
  11607. EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
  11608. /* .. TRI_ENABLE = 0 */
  11609. /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
  11610. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11611. /* .. L0_SEL = 0 */
  11612. /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
  11613. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11614. /* .. L1_SEL = 0 */
  11615. /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
  11616. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11617. /* .. L2_SEL = 0 */
  11618. /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
  11619. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11620. /* .. L3_SEL = 4 */
  11621. /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
  11622. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11623. /* .. Speed = 1 */
  11624. /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
  11625. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11626. /* .. IO_Type = 1 */
  11627. /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
  11628. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11629. /* .. PULLUP = 0 */
  11630. /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
  11631. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11632. /* .. DisableRcvr = 0 */
  11633. /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
  11634. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11635. /* .. */
  11636. EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
  11637. /* .. TRI_ENABLE = 0 */
  11638. /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
  11639. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11640. /* .. L0_SEL = 0 */
  11641. /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
  11642. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11643. /* .. L1_SEL = 0 */
  11644. /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
  11645. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11646. /* .. L2_SEL = 0 */
  11647. /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
  11648. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11649. /* .. L3_SEL = 4 */
  11650. /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
  11651. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11652. /* .. Speed = 1 */
  11653. /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
  11654. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11655. /* .. IO_Type = 1 */
  11656. /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
  11657. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11658. /* .. PULLUP = 0 */
  11659. /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
  11660. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11661. /* .. DisableRcvr = 0 */
  11662. /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
  11663. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11664. /* .. */
  11665. EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
  11666. /* .. TRI_ENABLE = 0 */
  11667. /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
  11668. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11669. /* .. L0_SEL = 0 */
  11670. /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
  11671. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11672. /* .. L1_SEL = 0 */
  11673. /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
  11674. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11675. /* .. L2_SEL = 0 */
  11676. /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
  11677. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11678. /* .. L3_SEL = 4 */
  11679. /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
  11680. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11681. /* .. Speed = 1 */
  11682. /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
  11683. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11684. /* .. IO_Type = 1 */
  11685. /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
  11686. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11687. /* .. PULLUP = 0 */
  11688. /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
  11689. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11690. /* .. DisableRcvr = 0 */
  11691. /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
  11692. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11693. /* .. */
  11694. EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
  11695. /* .. TRI_ENABLE = 0 */
  11696. /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
  11697. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11698. /* .. L0_SEL = 0 */
  11699. /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
  11700. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11701. /* .. L1_SEL = 0 */
  11702. /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
  11703. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11704. /* .. L2_SEL = 0 */
  11705. /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
  11706. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11707. /* .. L3_SEL = 4 */
  11708. /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
  11709. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11710. /* .. Speed = 1 */
  11711. /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
  11712. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11713. /* .. IO_Type = 1 */
  11714. /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
  11715. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11716. /* .. PULLUP = 0 */
  11717. /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
  11718. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11719. /* .. DisableRcvr = 0 */
  11720. /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
  11721. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11722. /* .. */
  11723. EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
  11724. /* .. TRI_ENABLE = 0 */
  11725. /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
  11726. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11727. /* .. L0_SEL = 0 */
  11728. /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
  11729. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11730. /* .. L1_SEL = 0 */
  11731. /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
  11732. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11733. /* .. L2_SEL = 0 */
  11734. /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
  11735. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11736. /* .. L3_SEL = 0 */
  11737. /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
  11738. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11739. /* .. Speed = 0 */
  11740. /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
  11741. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11742. /* .. IO_Type = 1 */
  11743. /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
  11744. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11745. /* .. PULLUP = 1 */
  11746. /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
  11747. /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
  11748. /* .. DisableRcvr = 0 */
  11749. /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
  11750. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11751. /* .. */
  11752. EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
  11753. /* .. TRI_ENABLE = 1 */
  11754. /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
  11755. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11756. /* .. Speed = 0 */
  11757. /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
  11758. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11759. /* .. IO_Type = 1 */
  11760. /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
  11761. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11762. /* .. PULLUP = 0 */
  11763. /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
  11764. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11765. /* .. DisableRcvr = 0 */
  11766. /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
  11767. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11768. /* .. */
  11769. EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
  11770. /* .. TRI_ENABLE = 0 */
  11771. /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
  11772. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11773. /* .. L0_SEL = 0 */
  11774. /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
  11775. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11776. /* .. L1_SEL = 0 */
  11777. /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
  11778. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11779. /* .. L2_SEL = 0 */
  11780. /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
  11781. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11782. /* .. L3_SEL = 7 */
  11783. /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
  11784. /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
  11785. /* .. Speed = 0 */
  11786. /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
  11787. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11788. /* .. IO_Type = 1 */
  11789. /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
  11790. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11791. /* .. PULLUP = 0 */
  11792. /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
  11793. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11794. /* .. DisableRcvr = 0 */
  11795. /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
  11796. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11797. /* .. */
  11798. EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
  11799. /* .. TRI_ENABLE = 1 */
  11800. /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
  11801. /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
  11802. /* .. L0_SEL = 0 */
  11803. /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
  11804. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11805. /* .. L1_SEL = 0 */
  11806. /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
  11807. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11808. /* .. L2_SEL = 0 */
  11809. /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
  11810. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11811. /* .. L3_SEL = 7 */
  11812. /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
  11813. /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
  11814. /* .. Speed = 0 */
  11815. /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
  11816. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11817. /* .. IO_Type = 1 */
  11818. /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
  11819. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11820. /* .. PULLUP = 0 */
  11821. /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
  11822. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11823. /* .. DisableRcvr = 0 */
  11824. /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
  11825. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11826. /* .. */
  11827. EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
  11828. /* .. TRI_ENABLE = 0 */
  11829. /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
  11830. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11831. /* .. L0_SEL = 0 */
  11832. /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
  11833. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11834. /* .. L1_SEL = 0 */
  11835. /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
  11836. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11837. /* .. L2_SEL = 0 */
  11838. /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
  11839. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11840. /* .. L3_SEL = 0 */
  11841. /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
  11842. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11843. /* .. Speed = 0 */
  11844. /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
  11845. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11846. /* .. IO_Type = 1 */
  11847. /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
  11848. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11849. /* .. PULLUP = 0 */
  11850. /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
  11851. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11852. /* .. DisableRcvr = 0 */
  11853. /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
  11854. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11855. /* .. */
  11856. EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
  11857. /* .. TRI_ENABLE = 0 */
  11858. /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
  11859. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11860. /* .. L0_SEL = 0 */
  11861. /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
  11862. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11863. /* .. L1_SEL = 0 */
  11864. /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
  11865. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11866. /* .. L2_SEL = 0 */
  11867. /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
  11868. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11869. /* .. L3_SEL = 0 */
  11870. /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
  11871. /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
  11872. /* .. Speed = 0 */
  11873. /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
  11874. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11875. /* .. IO_Type = 1 */
  11876. /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
  11877. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11878. /* .. PULLUP = 0 */
  11879. /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
  11880. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11881. /* .. DisableRcvr = 0 */
  11882. /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
  11883. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11884. /* .. */
  11885. EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
  11886. /* .. TRI_ENABLE = 0 */
  11887. /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
  11888. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11889. /* .. L0_SEL = 0 */
  11890. /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
  11891. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11892. /* .. L1_SEL = 0 */
  11893. /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
  11894. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11895. /* .. L2_SEL = 0 */
  11896. /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
  11897. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11898. /* .. L3_SEL = 4 */
  11899. /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
  11900. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11901. /* .. Speed = 0 */
  11902. /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
  11903. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11904. /* .. IO_Type = 1 */
  11905. /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
  11906. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11907. /* .. PULLUP = 0 */
  11908. /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
  11909. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11910. /* .. DisableRcvr = 0 */
  11911. /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
  11912. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11913. /* .. */
  11914. EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
  11915. /* .. TRI_ENABLE = 0 */
  11916. /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
  11917. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  11918. /* .. L0_SEL = 0 */
  11919. /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
  11920. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  11921. /* .. L1_SEL = 0 */
  11922. /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
  11923. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  11924. /* .. L2_SEL = 0 */
  11925. /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
  11926. /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
  11927. /* .. L3_SEL = 4 */
  11928. /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
  11929. /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
  11930. /* .. Speed = 0 */
  11931. /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
  11932. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  11933. /* .. IO_Type = 1 */
  11934. /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
  11935. /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
  11936. /* .. PULLUP = 0 */
  11937. /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
  11938. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  11939. /* .. DisableRcvr = 0 */
  11940. /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
  11941. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  11942. /* .. */
  11943. EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
  11944. /* .. SDIO0_WP_SEL = 55 */
  11945. /* .. ==> 0XF8000830[5:0] = 0x00000037U */
  11946. /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
  11947. /* .. SDIO0_CD_SEL = 47 */
  11948. /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
  11949. /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
  11950. /* .. */
  11951. EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
  11952. /* .. FINISH: MIO PROGRAMMING */
  11953. /* .. START: LOCK IT BACK */
  11954. /* .. LOCK_KEY = 0X767B */
  11955. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  11956. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  11957. /* .. */
  11958. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  11959. /* .. FINISH: LOCK IT BACK */
  11960. /* FINISH: top */
  11961. /* */
  11962. EMIT_EXIT(),
  11963. /* */
  11964. };
  11965. unsigned long ps7_peripherals_init_data_1_0[] = {
  11966. /* START: top */
  11967. /* .. START: SLCR SETTINGS */
  11968. /* .. UNLOCK_KEY = 0XDF0D */
  11969. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  11970. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  11971. /* .. */
  11972. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  11973. /* .. FINISH: SLCR SETTINGS */
  11974. /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
  11975. /* .. IBUF_DISABLE_MODE = 0x1 */
  11976. /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
  11977. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  11978. /* .. TERM_DISABLE_MODE = 0x1 */
  11979. /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
  11980. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11981. /* .. */
  11982. EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
  11983. /* .. IBUF_DISABLE_MODE = 0x1 */
  11984. /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
  11985. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  11986. /* .. TERM_DISABLE_MODE = 0x1 */
  11987. /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
  11988. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11989. /* .. */
  11990. EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
  11991. /* .. IBUF_DISABLE_MODE = 0x1 */
  11992. /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
  11993. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  11994. /* .. TERM_DISABLE_MODE = 0x1 */
  11995. /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
  11996. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  11997. /* .. */
  11998. EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
  11999. /* .. IBUF_DISABLE_MODE = 0x1 */
  12000. /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
  12001. /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
  12002. /* .. TERM_DISABLE_MODE = 0x1 */
  12003. /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
  12004. /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
  12005. /* .. */
  12006. EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
  12007. /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
  12008. /* .. START: LOCK IT BACK */
  12009. /* .. LOCK_KEY = 0X767B */
  12010. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  12011. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  12012. /* .. */
  12013. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  12014. /* .. FINISH: LOCK IT BACK */
  12015. /* .. START: SRAM/NOR SET OPMODE */
  12016. /* .. FINISH: SRAM/NOR SET OPMODE */
  12017. /* .. START: QSPI REGISTERS */
  12018. /* .. Holdb_dr = 1 */
  12019. /* .. ==> 0XE000D000[19:19] = 0x00000001U */
  12020. /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
  12021. /* .. */
  12022. EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
  12023. /* .. FINISH: QSPI REGISTERS */
  12024. /* .. START: PL POWER ON RESET REGISTERS */
  12025. /* .. PCFG_POR_CNT_4K = 0 */
  12026. /* .. ==> 0XF8007000[29:29] = 0x00000000U */
  12027. /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
  12028. /* .. */
  12029. EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
  12030. /* .. FINISH: PL POWER ON RESET REGISTERS */
  12031. /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
  12032. /* .. .. START: NAND SET CYCLE */
  12033. /* .. .. FINISH: NAND SET CYCLE */
  12034. /* .. .. START: OPMODE */
  12035. /* .. .. FINISH: OPMODE */
  12036. /* .. .. START: DIRECT COMMAND */
  12037. /* .. .. FINISH: DIRECT COMMAND */
  12038. /* .. .. START: SRAM/NOR CS0 SET CYCLE */
  12039. /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
  12040. /* .. .. START: DIRECT COMMAND */
  12041. /* .. .. FINISH: DIRECT COMMAND */
  12042. /* .. .. START: NOR CS0 BASE ADDRESS */
  12043. /* .. .. FINISH: NOR CS0 BASE ADDRESS */
  12044. /* .. .. START: SRAM/NOR CS1 SET CYCLE */
  12045. /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
  12046. /* .. .. START: DIRECT COMMAND */
  12047. /* .. .. FINISH: DIRECT COMMAND */
  12048. /* .. .. START: NOR CS1 BASE ADDRESS */
  12049. /* .. .. FINISH: NOR CS1 BASE ADDRESS */
  12050. /* .. .. START: USB RESET */
  12051. /* .. .. .. START: USB0 RESET */
  12052. /* .. .. .. .. START: DIR MODE BANK 0 */
  12053. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  12054. /* .. .. .. .. START: DIR MODE BANK 1 */
  12055. /* .. .. .. .. DIRECTION_1 = 0x4000 */
  12056. /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
  12057. /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
  12058. /* .. .. .. .. */
  12059. EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
  12060. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  12061. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12062. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12063. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12064. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12065. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12066. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  12067. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  12068. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  12069. /* .. .. .. .. DATA_1_LSW = 0x4000 */
  12070. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
  12071. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
  12072. /* .. .. .. .. */
  12073. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
  12074. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12075. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12076. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12077. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  12078. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  12079. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  12080. /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
  12081. /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
  12082. /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
  12083. /* .. .. .. .. */
  12084. EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
  12085. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  12086. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  12087. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  12088. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  12089. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  12090. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  12091. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  12092. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  12093. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  12094. /* .. .. .. .. DATA_1_LSW = 0x0 */
  12095. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
  12096. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
  12097. /* .. .. .. .. */
  12098. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
  12099. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  12100. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  12101. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  12102. /* .. .. .. .. START: ADD 1 MS DELAY */
  12103. /* .. .. .. .. */
  12104. EMIT_MASKDELAY(0XF8F00200, 1),
  12105. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  12106. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12107. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12108. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12109. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12110. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12111. /* .. .. .. .. MASK_1_LSW = 0xbfff */
  12112. /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
  12113. /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
  12114. /* .. .. .. .. DATA_1_LSW = 0x4000 */
  12115. /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
  12116. /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
  12117. /* .. .. .. .. */
  12118. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
  12119. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12120. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12121. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12122. /* .. .. .. FINISH: USB0 RESET */
  12123. /* .. .. .. START: USB1 RESET */
  12124. /* .. .. .. .. START: DIR MODE BANK 0 */
  12125. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  12126. /* .. .. .. .. START: DIR MODE BANK 1 */
  12127. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  12128. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12129. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12130. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12131. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12132. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12133. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12134. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12135. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12136. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  12137. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  12138. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  12139. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  12140. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  12141. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  12142. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  12143. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  12144. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  12145. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  12146. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  12147. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  12148. /* .. .. .. .. START: ADD 1 MS DELAY */
  12149. /* .. .. .. .. */
  12150. EMIT_MASKDELAY(0XF8F00200, 1),
  12151. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  12152. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12153. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12154. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12155. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12156. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12157. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12158. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12159. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12160. /* .. .. .. FINISH: USB1 RESET */
  12161. /* .. .. FINISH: USB RESET */
  12162. /* .. .. START: ENET RESET */
  12163. /* .. .. .. START: ENET0 RESET */
  12164. /* .. .. .. .. START: DIR MODE BANK 0 */
  12165. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  12166. /* .. .. .. .. START: DIR MODE BANK 1 */
  12167. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  12168. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12169. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12170. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12171. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12172. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12173. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12174. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12175. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12176. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  12177. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  12178. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  12179. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  12180. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  12181. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  12182. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  12183. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  12184. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  12185. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  12186. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  12187. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  12188. /* .. .. .. .. START: ADD 1 MS DELAY */
  12189. /* .. .. .. .. */
  12190. EMIT_MASKDELAY(0XF8F00200, 1),
  12191. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  12192. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12193. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12194. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12195. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12196. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12197. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12198. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12199. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12200. /* .. .. .. FINISH: ENET0 RESET */
  12201. /* .. .. .. START: ENET1 RESET */
  12202. /* .. .. .. .. START: DIR MODE BANK 0 */
  12203. /* .. .. .. .. FINISH: DIR MODE BANK 0 */
  12204. /* .. .. .. .. START: DIR MODE BANK 1 */
  12205. /* .. .. .. .. FINISH: DIR MODE BANK 1 */
  12206. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12207. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12208. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12209. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12210. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12211. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12212. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12213. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12214. /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
  12215. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  12216. /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
  12217. /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
  12218. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  12219. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  12220. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  12221. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  12222. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  12223. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  12224. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  12225. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  12226. /* .. .. .. .. START: ADD 1 MS DELAY */
  12227. /* .. .. .. .. */
  12228. EMIT_MASKDELAY(0XF8F00200, 1),
  12229. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  12230. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12231. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12232. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12233. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12234. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12235. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12236. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12237. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12238. /* .. .. .. FINISH: ENET1 RESET */
  12239. /* .. .. FINISH: ENET RESET */
  12240. /* .. .. START: I2C RESET */
  12241. /* .. .. .. START: I2C0 RESET */
  12242. /* .. .. .. .. START: DIR MODE GPIO BANK0 */
  12243. /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
  12244. /* .. .. .. .. START: DIR MODE GPIO BANK1 */
  12245. /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
  12246. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12247. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12248. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12249. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12250. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12251. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12252. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12253. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12254. /* .. .. .. .. START: OUTPUT ENABLE */
  12255. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  12256. /* .. .. .. .. START: OUTPUT ENABLE */
  12257. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  12258. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  12259. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  12260. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  12261. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  12262. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  12263. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  12264. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  12265. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  12266. /* .. .. .. .. START: ADD 1 MS DELAY */
  12267. /* .. .. .. .. */
  12268. EMIT_MASKDELAY(0XF8F00200, 1),
  12269. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  12270. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12271. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12272. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12273. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12274. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12275. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12276. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12277. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12278. /* .. .. .. FINISH: I2C0 RESET */
  12279. /* .. .. .. START: I2C1 RESET */
  12280. /* .. .. .. .. START: DIR MODE GPIO BANK0 */
  12281. /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
  12282. /* .. .. .. .. START: DIR MODE GPIO BANK1 */
  12283. /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
  12284. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12285. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12286. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12287. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12288. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12289. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12290. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12291. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12292. /* .. .. .. .. START: OUTPUT ENABLE */
  12293. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  12294. /* .. .. .. .. START: OUTPUT ENABLE */
  12295. /* .. .. .. .. FINISH: OUTPUT ENABLE */
  12296. /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
  12297. /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
  12298. /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
  12299. /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
  12300. /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
  12301. /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
  12302. /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
  12303. /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
  12304. /* .. .. .. .. START: ADD 1 MS DELAY */
  12305. /* .. .. .. .. */
  12306. EMIT_MASKDELAY(0XF8F00200, 1),
  12307. /* .. .. .. .. FINISH: ADD 1 MS DELAY */
  12308. /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12309. /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12310. /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12311. /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
  12312. /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12313. /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
  12314. /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12315. /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
  12316. /* .. .. .. FINISH: I2C1 RESET */
  12317. /* .. .. FINISH: I2C RESET */
  12318. /* .. .. START: NOR CHIP SELECT */
  12319. /* .. .. .. START: DIR MODE BANK 0 */
  12320. /* .. .. .. FINISH: DIR MODE BANK 0 */
  12321. /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12322. /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
  12323. /* .. .. .. START: OUTPUT ENABLE BANK 0 */
  12324. /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
  12325. /* .. .. FINISH: NOR CHIP SELECT */
  12326. /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
  12327. /* FINISH: top */
  12328. /* */
  12329. EMIT_EXIT(),
  12330. /* */
  12331. };
  12332. unsigned long ps7_post_config_1_0[] = {
  12333. /* START: top */
  12334. /* .. START: SLCR SETTINGS */
  12335. /* .. UNLOCK_KEY = 0XDF0D */
  12336. /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
  12337. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
  12338. /* .. */
  12339. EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
  12340. /* .. FINISH: SLCR SETTINGS */
  12341. /* .. START: ENABLING LEVEL SHIFTER */
  12342. /* .. USER_INP_ICT_EN_0 = 3 */
  12343. /* .. ==> 0XF8000900[1:0] = 0x00000003U */
  12344. /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
  12345. /* .. USER_INP_ICT_EN_1 = 3 */
  12346. /* .. ==> 0XF8000900[3:2] = 0x00000003U */
  12347. /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
  12348. /* .. */
  12349. EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
  12350. /* .. FINISH: ENABLING LEVEL SHIFTER */
  12351. /* .. START: FPGA RESETS TO 0 */
  12352. /* .. reserved_3 = 0 */
  12353. /* .. ==> 0XF8000240[31:25] = 0x00000000U */
  12354. /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
  12355. /* .. FPGA_ACP_RST = 0 */
  12356. /* .. ==> 0XF8000240[24:24] = 0x00000000U */
  12357. /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
  12358. /* .. FPGA_AXDS3_RST = 0 */
  12359. /* .. ==> 0XF8000240[23:23] = 0x00000000U */
  12360. /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
  12361. /* .. FPGA_AXDS2_RST = 0 */
  12362. /* .. ==> 0XF8000240[22:22] = 0x00000000U */
  12363. /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
  12364. /* .. FPGA_AXDS1_RST = 0 */
  12365. /* .. ==> 0XF8000240[21:21] = 0x00000000U */
  12366. /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
  12367. /* .. FPGA_AXDS0_RST = 0 */
  12368. /* .. ==> 0XF8000240[20:20] = 0x00000000U */
  12369. /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
  12370. /* .. reserved_2 = 0 */
  12371. /* .. ==> 0XF8000240[19:18] = 0x00000000U */
  12372. /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
  12373. /* .. FSSW1_FPGA_RST = 0 */
  12374. /* .. ==> 0XF8000240[17:17] = 0x00000000U */
  12375. /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
  12376. /* .. FSSW0_FPGA_RST = 0 */
  12377. /* .. ==> 0XF8000240[16:16] = 0x00000000U */
  12378. /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
  12379. /* .. reserved_1 = 0 */
  12380. /* .. ==> 0XF8000240[15:14] = 0x00000000U */
  12381. /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
  12382. /* .. FPGA_FMSW1_RST = 0 */
  12383. /* .. ==> 0XF8000240[13:13] = 0x00000000U */
  12384. /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
  12385. /* .. FPGA_FMSW0_RST = 0 */
  12386. /* .. ==> 0XF8000240[12:12] = 0x00000000U */
  12387. /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
  12388. /* .. FPGA_DMA3_RST = 0 */
  12389. /* .. ==> 0XF8000240[11:11] = 0x00000000U */
  12390. /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
  12391. /* .. FPGA_DMA2_RST = 0 */
  12392. /* .. ==> 0XF8000240[10:10] = 0x00000000U */
  12393. /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
  12394. /* .. FPGA_DMA1_RST = 0 */
  12395. /* .. ==> 0XF8000240[9:9] = 0x00000000U */
  12396. /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
  12397. /* .. FPGA_DMA0_RST = 0 */
  12398. /* .. ==> 0XF8000240[8:8] = 0x00000000U */
  12399. /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
  12400. /* .. reserved = 0 */
  12401. /* .. ==> 0XF8000240[7:4] = 0x00000000U */
  12402. /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
  12403. /* .. FPGA3_OUT_RST = 0 */
  12404. /* .. ==> 0XF8000240[3:3] = 0x00000000U */
  12405. /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
  12406. /* .. FPGA2_OUT_RST = 0 */
  12407. /* .. ==> 0XF8000240[2:2] = 0x00000000U */
  12408. /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
  12409. /* .. FPGA1_OUT_RST = 0 */
  12410. /* .. ==> 0XF8000240[1:1] = 0x00000000U */
  12411. /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
  12412. /* .. FPGA0_OUT_RST = 0 */
  12413. /* .. ==> 0XF8000240[0:0] = 0x00000000U */
  12414. /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
  12415. /* .. */
  12416. EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
  12417. /* .. FINISH: FPGA RESETS TO 0 */
  12418. /* .. START: AFI REGISTERS */
  12419. /* .. .. START: AFI0 REGISTERS */
  12420. /* .. .. FINISH: AFI0 REGISTERS */
  12421. /* .. .. START: AFI1 REGISTERS */
  12422. /* .. .. FINISH: AFI1 REGISTERS */
  12423. /* .. .. START: AFI2 REGISTERS */
  12424. /* .. .. FINISH: AFI2 REGISTERS */
  12425. /* .. .. START: AFI3 REGISTERS */
  12426. /* .. .. FINISH: AFI3 REGISTERS */
  12427. /* .. FINISH: AFI REGISTERS */
  12428. /* .. START: LOCK IT BACK */
  12429. /* .. LOCK_KEY = 0X767B */
  12430. /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
  12431. /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
  12432. /* .. */
  12433. EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
  12434. /* .. FINISH: LOCK IT BACK */
  12435. /* FINISH: top */
  12436. /* */
  12437. EMIT_EXIT(),
  12438. /* */
  12439. };
  12440. #include "xil_io.h"
  12441. unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
  12442. unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
  12443. unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
  12444. unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
  12445. unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
  12446. int ps7_post_config(void)
  12447. {
  12448. /* Get the PS_VERSION on run time */
  12449. unsigned long si_ver = ps7GetSiliconVersion();
  12450. int ret = -1;
  12451. if (si_ver == PCW_SILICON_VERSION_1) {
  12452. ret = ps7_config(ps7_post_config_1_0);
  12453. if (ret != PS7_INIT_SUCCESS)
  12454. return ret;
  12455. } else if (si_ver == PCW_SILICON_VERSION_2) {
  12456. ret = ps7_config(ps7_post_config_2_0);
  12457. if (ret != PS7_INIT_SUCCESS)
  12458. return ret;
  12459. } else {
  12460. ret = ps7_config(ps7_post_config_3_0);
  12461. if (ret != PS7_INIT_SUCCESS)
  12462. return ret;
  12463. }
  12464. return PS7_INIT_SUCCESS;
  12465. }
  12466. int ps7_init(void)
  12467. {
  12468. /* Get the PS_VERSION on run time */
  12469. unsigned long si_ver = ps7GetSiliconVersion();
  12470. int ret;
  12471. /*int pcw_ver = 0; */
  12472. if (si_ver == PCW_SILICON_VERSION_1) {
  12473. ps7_mio_init_data = ps7_mio_init_data_1_0;
  12474. ps7_pll_init_data = ps7_pll_init_data_1_0;
  12475. ps7_clock_init_data = ps7_clock_init_data_1_0;
  12476. ps7_ddr_init_data = ps7_ddr_init_data_1_0;
  12477. ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
  12478. /*pcw_ver = 1; */
  12479. } else if (si_ver == PCW_SILICON_VERSION_2) {
  12480. ps7_mio_init_data = ps7_mio_init_data_2_0;
  12481. ps7_pll_init_data = ps7_pll_init_data_2_0;
  12482. ps7_clock_init_data = ps7_clock_init_data_2_0;
  12483. ps7_ddr_init_data = ps7_ddr_init_data_2_0;
  12484. ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
  12485. /*pcw_ver = 2; */
  12486. } else {
  12487. ps7_mio_init_data = ps7_mio_init_data_3_0;
  12488. ps7_pll_init_data = ps7_pll_init_data_3_0;
  12489. ps7_clock_init_data = ps7_clock_init_data_3_0;
  12490. ps7_ddr_init_data = ps7_ddr_init_data_3_0;
  12491. ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
  12492. /*pcw_ver = 3; */
  12493. }
  12494. /* MIO init */
  12495. ret = ps7_config(ps7_mio_init_data);
  12496. if (ret != PS7_INIT_SUCCESS)
  12497. return ret;
  12498. /* PLL init */
  12499. ret = ps7_config(ps7_pll_init_data);
  12500. if (ret != PS7_INIT_SUCCESS)
  12501. return ret;
  12502. /* Clock init */
  12503. ret = ps7_config(ps7_clock_init_data);
  12504. if (ret != PS7_INIT_SUCCESS)
  12505. return ret;
  12506. /* DDR init */
  12507. ret = ps7_config(ps7_ddr_init_data);
  12508. if (ret != PS7_INIT_SUCCESS)
  12509. return ret;
  12510. /* Peripherals init */
  12511. ret = ps7_config(ps7_peripherals_init_data);
  12512. if (ret != PS7_INIT_SUCCESS)
  12513. return ret;
  12514. return PS7_INIT_SUCCESS;
  12515. }