vexpress-v2m.dtsi 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ARM Ltd. Versatile Express
  4. *
  5. * Motherboard Express uATX
  6. * V2M-P1
  7. *
  8. * HBI-0190D
  9. *
  10. * Original memory map ("Legacy memory map" in the board's
  11. * Technical Reference Manual)
  12. *
  13. * WARNING! The hardware described in this file is independent from the
  14. * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
  15. * correspondence between the two configurations.
  16. *
  17. * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  18. * CHANGES TO vexpress-v2m-rs1.dtsi!
  19. */
  20. / {
  21. smb@4000000 {
  22. motherboard {
  23. model = "V2M-P1";
  24. arm,hbi = <0x190>;
  25. arm,vexpress,site = <0>;
  26. compatible = "arm,vexpress,v2m-p1", "simple-bus";
  27. #address-cells = <2>; /* SMB chipselect number and offset */
  28. #size-cells = <1>;
  29. #interrupt-cells = <1>;
  30. ranges;
  31. flash@0,00000000 {
  32. compatible = "arm,vexpress-flash", "cfi-flash";
  33. reg = <0 0x00000000 0x04000000>,
  34. <1 0x00000000 0x04000000>;
  35. bank-width = <4>;
  36. };
  37. psram@2,00000000 {
  38. compatible = "arm,vexpress-psram", "mtd-ram";
  39. reg = <2 0x00000000 0x02000000>;
  40. bank-width = <4>;
  41. };
  42. ethernet@3,02000000 {
  43. compatible = "smsc,lan9118", "smsc,lan9115";
  44. reg = <3 0x02000000 0x10000>;
  45. interrupts = <15>;
  46. phy-mode = "mii";
  47. reg-io-width = <4>;
  48. smsc,irq-active-high;
  49. smsc,irq-push-pull;
  50. vdd33a-supply = <&v2m_fixed_3v3>;
  51. vddvario-supply = <&v2m_fixed_3v3>;
  52. };
  53. usb@3,03000000 {
  54. compatible = "nxp,usb-isp1761";
  55. reg = <3 0x03000000 0x20000>;
  56. interrupts = <16>;
  57. port1-otg;
  58. };
  59. iofpga@7,00000000 {
  60. compatible = "simple-bus";
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. ranges = <0 7 0 0x20000>;
  64. v2m_sysreg: sysreg@0 {
  65. compatible = "arm,vexpress-sysreg";
  66. reg = <0x00000 0x1000>;
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. ranges = <0 0 0x1000>;
  70. v2m_led_gpios: gpio@8 {
  71. compatible = "arm,vexpress-sysreg,sys_led";
  72. reg = <0x008 4>;
  73. gpio-controller;
  74. #gpio-cells = <2>;
  75. };
  76. v2m_mmc_gpios: gpio@48 {
  77. compatible = "arm,vexpress-sysreg,sys_mci";
  78. reg = <0x048 4>;
  79. gpio-controller;
  80. #gpio-cells = <2>;
  81. };
  82. v2m_flash_gpios: gpio@4c {
  83. compatible = "arm,vexpress-sysreg,sys_flash";
  84. reg = <0x04c 4>;
  85. gpio-controller;
  86. #gpio-cells = <2>;
  87. };
  88. };
  89. v2m_sysctl: sysctl@1000 {
  90. compatible = "arm,sp810", "arm,primecell";
  91. reg = <0x01000 0x1000>;
  92. clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
  93. clock-names = "refclk", "timclk", "apb_pclk";
  94. #clock-cells = <1>;
  95. clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
  96. assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
  97. assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
  98. };
  99. /* PCI-E I2C bus */
  100. v2m_i2c_pcie: i2c@2000 {
  101. compatible = "arm,versatile-i2c";
  102. reg = <0x02000 0x1000>;
  103. #address-cells = <1>;
  104. #size-cells = <0>;
  105. pcie-switch@60 {
  106. compatible = "idt,89hpes32h8";
  107. reg = <0x60>;
  108. };
  109. };
  110. aaci@4000 {
  111. compatible = "arm,pl041", "arm,primecell";
  112. reg = <0x04000 0x1000>;
  113. interrupts = <11>;
  114. clocks = <&smbclk>;
  115. clock-names = "apb_pclk";
  116. };
  117. mmci@5000 {
  118. compatible = "arm,pl180", "arm,primecell";
  119. reg = <0x05000 0x1000>;
  120. interrupts = <9>, <10>;
  121. cd-gpios = <&v2m_mmc_gpios 0 0>;
  122. wp-gpios = <&v2m_mmc_gpios 1 0>;
  123. max-frequency = <12000000>;
  124. vmmc-supply = <&v2m_fixed_3v3>;
  125. clocks = <&v2m_clk24mhz>, <&smbclk>;
  126. clock-names = "mclk", "apb_pclk";
  127. };
  128. kmi@6000 {
  129. compatible = "arm,pl050", "arm,primecell";
  130. reg = <0x06000 0x1000>;
  131. interrupts = <12>;
  132. clocks = <&v2m_clk24mhz>, <&smbclk>;
  133. clock-names = "KMIREFCLK", "apb_pclk";
  134. };
  135. kmi@7000 {
  136. compatible = "arm,pl050", "arm,primecell";
  137. reg = <0x07000 0x1000>;
  138. interrupts = <13>;
  139. clocks = <&v2m_clk24mhz>, <&smbclk>;
  140. clock-names = "KMIREFCLK", "apb_pclk";
  141. };
  142. v2m_serial0: uart@9000 {
  143. compatible = "arm,pl011", "arm,primecell";
  144. reg = <0x09000 0x1000>;
  145. interrupts = <5>;
  146. clocks = <&v2m_oscclk2>, <&smbclk>;
  147. clock-names = "uartclk", "apb_pclk";
  148. };
  149. v2m_serial1: uart@a000 {
  150. compatible = "arm,pl011", "arm,primecell";
  151. reg = <0x0a000 0x1000>;
  152. interrupts = <6>;
  153. clocks = <&v2m_oscclk2>, <&smbclk>;
  154. clock-names = "uartclk", "apb_pclk";
  155. };
  156. v2m_serial2: uart@b000 {
  157. compatible = "arm,pl011", "arm,primecell";
  158. reg = <0x0b000 0x1000>;
  159. interrupts = <7>;
  160. clocks = <&v2m_oscclk2>, <&smbclk>;
  161. clock-names = "uartclk", "apb_pclk";
  162. };
  163. v2m_serial3: uart@c000 {
  164. compatible = "arm,pl011", "arm,primecell";
  165. reg = <0x0c000 0x1000>;
  166. interrupts = <8>;
  167. clocks = <&v2m_oscclk2>, <&smbclk>;
  168. clock-names = "uartclk", "apb_pclk";
  169. };
  170. wdt@f000 {
  171. compatible = "arm,sp805", "arm,primecell";
  172. reg = <0x0f000 0x1000>;
  173. interrupts = <0>;
  174. clocks = <&v2m_refclk32khz>, <&smbclk>;
  175. clock-names = "wdogclk", "apb_pclk";
  176. };
  177. v2m_timer01: timer@11000 {
  178. compatible = "arm,sp804", "arm,primecell";
  179. reg = <0x11000 0x1000>;
  180. interrupts = <2>;
  181. clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
  182. clock-names = "timclken1", "timclken2", "apb_pclk";
  183. };
  184. v2m_timer23: timer@12000 {
  185. compatible = "arm,sp804", "arm,primecell";
  186. reg = <0x12000 0x1000>;
  187. interrupts = <3>;
  188. clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
  189. clock-names = "timclken1", "timclken2", "apb_pclk";
  190. };
  191. /* DVI I2C bus */
  192. v2m_i2c_dvi: i2c@16000 {
  193. compatible = "arm,versatile-i2c";
  194. reg = <0x16000 0x1000>;
  195. #address-cells = <1>;
  196. #size-cells = <0>;
  197. dvi-transmitter@39 {
  198. compatible = "sil,sii9022-tpi", "sil,sii9022";
  199. reg = <0x39>;
  200. ports {
  201. #address-cells = <1>;
  202. #size-cells = <0>;
  203. /*
  204. * Both the core tile and the motherboard routes their output
  205. * pads to this transmitter. The motherboard system controller
  206. * can select one of them as input using a mux register in
  207. * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
  208. * the only platform with this specific set-up.
  209. */
  210. port@0 {
  211. reg = <0>;
  212. dvi_bridge_in_ct: endpoint {
  213. remote-endpoint = <&clcd_pads_ct>;
  214. };
  215. };
  216. port@1 {
  217. reg = <1>;
  218. dvi_bridge_in_mb: endpoint {
  219. remote-endpoint = <&clcd_pads_mb>;
  220. };
  221. };
  222. };
  223. };
  224. dvi-transmitter@60 {
  225. compatible = "sil,sii9022-cpi", "sil,sii9022";
  226. reg = <0x60>;
  227. };
  228. };
  229. rtc@17000 {
  230. compatible = "arm,pl031", "arm,primecell";
  231. reg = <0x17000 0x1000>;
  232. interrupts = <4>;
  233. clocks = <&smbclk>;
  234. clock-names = "apb_pclk";
  235. };
  236. compact-flash@1a000 {
  237. compatible = "arm,vexpress-cf", "ata-generic";
  238. reg = <0x1a000 0x100
  239. 0x1a100 0xf00>;
  240. reg-shift = <2>;
  241. };
  242. clcd@1f000 {
  243. compatible = "arm,pl111", "arm,primecell";
  244. reg = <0x1f000 0x1000>;
  245. interrupt-names = "combined";
  246. interrupts = <14>;
  247. clocks = <&v2m_oscclk1>, <&smbclk>;
  248. clock-names = "clcdclk", "apb_pclk";
  249. /* 800x600 16bpp @36MHz works fine */
  250. max-memory-bandwidth = <54000000>;
  251. memory-region = <&vram>;
  252. port {
  253. clcd_pads_mb: endpoint {
  254. remote-endpoint = <&dvi_bridge_in_mb>;
  255. arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
  256. };
  257. };
  258. };
  259. };
  260. v2m_fixed_3v3: fixed-regulator-0 {
  261. compatible = "regulator-fixed";
  262. regulator-name = "3V3";
  263. regulator-min-microvolt = <3300000>;
  264. regulator-max-microvolt = <3300000>;
  265. regulator-always-on;
  266. };
  267. v2m_clk24mhz: clk24mhz {
  268. compatible = "fixed-clock";
  269. #clock-cells = <0>;
  270. clock-frequency = <24000000>;
  271. clock-output-names = "v2m:clk24mhz";
  272. };
  273. v2m_refclk1mhz: refclk1mhz {
  274. compatible = "fixed-clock";
  275. #clock-cells = <0>;
  276. clock-frequency = <1000000>;
  277. clock-output-names = "v2m:refclk1mhz";
  278. };
  279. v2m_refclk32khz: refclk32khz {
  280. compatible = "fixed-clock";
  281. #clock-cells = <0>;
  282. clock-frequency = <32768>;
  283. clock-output-names = "v2m:refclk32khz";
  284. };
  285. leds {
  286. compatible = "gpio-leds";
  287. user1 {
  288. label = "v2m:green:user1";
  289. gpios = <&v2m_led_gpios 0 0>;
  290. linux,default-trigger = "heartbeat";
  291. };
  292. user2 {
  293. label = "v2m:green:user2";
  294. gpios = <&v2m_led_gpios 1 0>;
  295. linux,default-trigger = "mmc0";
  296. };
  297. user3 {
  298. label = "v2m:green:user3";
  299. gpios = <&v2m_led_gpios 2 0>;
  300. linux,default-trigger = "cpu0";
  301. };
  302. user4 {
  303. label = "v2m:green:user4";
  304. gpios = <&v2m_led_gpios 3 0>;
  305. linux,default-trigger = "cpu1";
  306. };
  307. user5 {
  308. label = "v2m:green:user5";
  309. gpios = <&v2m_led_gpios 4 0>;
  310. linux,default-trigger = "cpu2";
  311. };
  312. user6 {
  313. label = "v2m:green:user6";
  314. gpios = <&v2m_led_gpios 5 0>;
  315. linux,default-trigger = "cpu3";
  316. };
  317. user7 {
  318. label = "v2m:green:user7";
  319. gpios = <&v2m_led_gpios 6 0>;
  320. linux,default-trigger = "cpu4";
  321. };
  322. user8 {
  323. label = "v2m:green:user8";
  324. gpios = <&v2m_led_gpios 7 0>;
  325. linux,default-trigger = "cpu5";
  326. };
  327. };
  328. mcc {
  329. compatible = "arm,vexpress,config-bus";
  330. arm,vexpress,config-bridge = <&v2m_sysreg>;
  331. oscclk0 {
  332. /* MCC static memory clock */
  333. compatible = "arm,vexpress-osc";
  334. arm,vexpress-sysreg,func = <1 0>;
  335. freq-range = <25000000 60000000>;
  336. #clock-cells = <0>;
  337. clock-output-names = "v2m:oscclk0";
  338. };
  339. v2m_oscclk1: oscclk1 {
  340. /* CLCD clock */
  341. compatible = "arm,vexpress-osc";
  342. arm,vexpress-sysreg,func = <1 1>;
  343. freq-range = <23750000 65000000>;
  344. #clock-cells = <0>;
  345. clock-output-names = "v2m:oscclk1";
  346. };
  347. v2m_oscclk2: oscclk2 {
  348. /* IO FPGA peripheral clock */
  349. compatible = "arm,vexpress-osc";
  350. arm,vexpress-sysreg,func = <1 2>;
  351. freq-range = <24000000 24000000>;
  352. #clock-cells = <0>;
  353. clock-output-names = "v2m:oscclk2";
  354. };
  355. volt-vio {
  356. /* Logic level voltage */
  357. compatible = "arm,vexpress-volt";
  358. arm,vexpress-sysreg,func = <2 0>;
  359. regulator-name = "VIO";
  360. regulator-always-on;
  361. label = "VIO";
  362. };
  363. temp-mcc {
  364. /* MCC internal operating temperature */
  365. compatible = "arm,vexpress-temp";
  366. arm,vexpress-sysreg,func = <4 0>;
  367. label = "MCC";
  368. };
  369. reset {
  370. compatible = "arm,vexpress-reset";
  371. arm,vexpress-sysreg,func = <5 0>;
  372. };
  373. muxfpga {
  374. compatible = "arm,vexpress-muxfpga";
  375. arm,vexpress-sysreg,func = <7 0>;
  376. };
  377. shutdown {
  378. compatible = "arm,vexpress-shutdown";
  379. arm,vexpress-sysreg,func = <8 0>;
  380. };
  381. reboot {
  382. compatible = "arm,vexpress-reboot";
  383. arm,vexpress-sysreg,func = <9 0>;
  384. };
  385. dvimode {
  386. compatible = "arm,vexpress-dvimode";
  387. arm,vexpress-sysreg,func = <11 0>;
  388. };
  389. };
  390. };
  391. };
  392. };