xilinx_emaclite.c 9.8 KB

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  1. /*
  2. * (C) Copyright 2007-2009 Michal Simek
  3. * (C) Copyright 2003 Xilinx Inc.
  4. *
  5. * Michal SIMEK <monstr@monstr.eu>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <net.h>
  11. #include <config.h>
  12. #include <malloc.h>
  13. #include <asm/io.h>
  14. #include <fdtdec.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #undef DEBUG
  17. #define ENET_ADDR_LENGTH 6
  18. /* EmacLite constants */
  19. #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
  20. #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
  21. #define XEL_TSR_OFFSET 0x07FC /* Tx status */
  22. #define XEL_RSR_OFFSET 0x17FC /* Rx status */
  23. #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
  24. /* Xmit complete */
  25. #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
  26. /* Xmit interrupt enable bit */
  27. #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
  28. /* Buffer is active, SW bit only */
  29. #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
  30. /* Program the MAC address */
  31. #define XEL_TSR_PROGRAM_MASK 0x00000002UL
  32. /* define for programming the MAC address into the EMAC Lite */
  33. #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
  34. /* Transmit packet length upper byte */
  35. #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
  36. /* Transmit packet length lower byte */
  37. #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
  38. /* Recv complete */
  39. #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
  40. /* Recv interrupt enable bit */
  41. #define XEL_RSR_RECV_IE_MASK 0x00000008UL
  42. struct xemaclite {
  43. u32 nexttxbuffertouse; /* Next TX buffer to write to */
  44. u32 nextrxbuffertouse; /* Next RX buffer to read from */
  45. u32 txpp; /* TX ping pong buffer */
  46. u32 rxpp; /* RX ping pong buffer */
  47. };
  48. static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
  49. static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
  50. {
  51. u32 i;
  52. u32 alignbuffer;
  53. u32 *to32ptr;
  54. u32 *from32ptr;
  55. u8 *to8ptr;
  56. u8 *from8ptr;
  57. from32ptr = (u32 *) srcptr;
  58. /* Word aligned buffer, no correction needed. */
  59. to32ptr = (u32 *) destptr;
  60. while (bytecount > 3) {
  61. *to32ptr++ = *from32ptr++;
  62. bytecount -= 4;
  63. }
  64. to8ptr = (u8 *) to32ptr;
  65. alignbuffer = *from32ptr++;
  66. from8ptr = (u8 *) &alignbuffer;
  67. for (i = 0; i < bytecount; i++)
  68. *to8ptr++ = *from8ptr++;
  69. }
  70. static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
  71. {
  72. u32 i;
  73. u32 alignbuffer;
  74. u32 *to32ptr = (u32 *) destptr;
  75. u32 *from32ptr;
  76. u8 *to8ptr;
  77. u8 *from8ptr;
  78. from32ptr = (u32 *) srcptr;
  79. while (bytecount > 3) {
  80. *to32ptr++ = *from32ptr++;
  81. bytecount -= 4;
  82. }
  83. alignbuffer = 0;
  84. to8ptr = (u8 *) &alignbuffer;
  85. from8ptr = (u8 *) from32ptr;
  86. for (i = 0; i < bytecount; i++)
  87. *to8ptr++ = *from8ptr++;
  88. *to32ptr++ = alignbuffer;
  89. }
  90. static void emaclite_halt(struct eth_device *dev)
  91. {
  92. debug("eth_halt\n");
  93. }
  94. static int emaclite_init(struct eth_device *dev, bd_t *bis)
  95. {
  96. struct xemaclite *emaclite = dev->priv;
  97. debug("EmacLite Initialization Started\n");
  98. /*
  99. * TX - TX_PING & TX_PONG initialization
  100. */
  101. /* Restart PING TX */
  102. out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
  103. /* Copy MAC address */
  104. xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
  105. /* Set the length */
  106. out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
  107. /* Update the MAC address in the EMAC Lite */
  108. out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
  109. /* Wait for EMAC Lite to finish with the MAC address update */
  110. while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
  111. XEL_TSR_PROG_MAC_ADDR) != 0)
  112. ;
  113. if (emaclite->txpp) {
  114. /* The same operation with PONG TX */
  115. out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
  116. xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
  117. XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
  118. out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
  119. out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
  120. XEL_TSR_PROG_MAC_ADDR);
  121. while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
  122. XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
  123. ;
  124. }
  125. /*
  126. * RX - RX_PING & RX_PONG initialization
  127. */
  128. /* Write out the value to flush the RX buffer */
  129. out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
  130. if (emaclite->rxpp)
  131. out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
  132. XEL_RSR_RECV_IE_MASK);
  133. debug("EmacLite Initialization complete\n");
  134. return 0;
  135. }
  136. static int xemaclite_txbufferavailable(struct eth_device *dev)
  137. {
  138. u32 reg;
  139. u32 txpingbusy;
  140. u32 txpongbusy;
  141. struct xemaclite *emaclite = dev->priv;
  142. /*
  143. * Read the other buffer register
  144. * and determine if the other buffer is available
  145. */
  146. reg = in_be32 (dev->iobase +
  147. emaclite->nexttxbuffertouse + 0);
  148. txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
  149. XEL_TSR_XMIT_BUSY_MASK);
  150. reg = in_be32 (dev->iobase +
  151. (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
  152. txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
  153. XEL_TSR_XMIT_BUSY_MASK);
  154. return !(txpingbusy && txpongbusy);
  155. }
  156. static int emaclite_send(struct eth_device *dev, void *ptr, int len)
  157. {
  158. u32 reg;
  159. u32 baseaddress;
  160. struct xemaclite *emaclite = dev->priv;
  161. u32 maxtry = 1000;
  162. if (len > PKTSIZE)
  163. len = PKTSIZE;
  164. while (!xemaclite_txbufferavailable(dev) && maxtry) {
  165. udelay(10);
  166. maxtry--;
  167. }
  168. if (!maxtry) {
  169. printf("Error: Timeout waiting for ethernet TX buffer\n");
  170. /* Restart PING TX */
  171. out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
  172. if (emaclite->txpp) {
  173. out_be32 (dev->iobase + XEL_TSR_OFFSET +
  174. XEL_BUFFER_OFFSET, 0);
  175. }
  176. return -1;
  177. }
  178. /* Determine the expected TX buffer address */
  179. baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
  180. /* Determine if the expected buffer address is empty */
  181. reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
  182. if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
  183. && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
  184. & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
  185. if (emaclite->txpp)
  186. emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
  187. debug("Send packet from 0x%x\n", baseaddress);
  188. /* Write the frame to the buffer */
  189. xemaclite_alignedwrite(ptr, baseaddress, len);
  190. out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
  191. (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
  192. reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
  193. reg |= XEL_TSR_XMIT_BUSY_MASK;
  194. if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
  195. reg |= XEL_TSR_XMIT_ACTIVE_MASK;
  196. out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
  197. return 0;
  198. }
  199. if (emaclite->txpp) {
  200. /* Switch to second buffer */
  201. baseaddress ^= XEL_BUFFER_OFFSET;
  202. /* Determine if the expected buffer address is empty */
  203. reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
  204. if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
  205. && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
  206. & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
  207. debug("Send packet from 0x%x\n", baseaddress);
  208. /* Write the frame to the buffer */
  209. xemaclite_alignedwrite(ptr, baseaddress, len);
  210. out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
  211. (XEL_TPLR_LENGTH_MASK_HI |
  212. XEL_TPLR_LENGTH_MASK_LO)));
  213. reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
  214. reg |= XEL_TSR_XMIT_BUSY_MASK;
  215. if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
  216. reg |= XEL_TSR_XMIT_ACTIVE_MASK;
  217. out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
  218. return 0;
  219. }
  220. }
  221. puts("Error while sending frame\n");
  222. return -1;
  223. }
  224. static int emaclite_recv(struct eth_device *dev)
  225. {
  226. u32 length;
  227. u32 reg;
  228. u32 baseaddress;
  229. struct xemaclite *emaclite = dev->priv;
  230. baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
  231. reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
  232. debug("Testing data at address 0x%x\n", baseaddress);
  233. if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
  234. if (emaclite->rxpp)
  235. emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
  236. } else {
  237. if (!emaclite->rxpp) {
  238. debug("No data was available - address 0x%x\n",
  239. baseaddress);
  240. return 0;
  241. } else {
  242. baseaddress ^= XEL_BUFFER_OFFSET;
  243. reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
  244. if ((reg & XEL_RSR_RECV_DONE_MASK) !=
  245. XEL_RSR_RECV_DONE_MASK) {
  246. debug("No data was available - address 0x%x\n",
  247. baseaddress);
  248. return 0;
  249. }
  250. }
  251. }
  252. /* Get the length of the frame that arrived */
  253. switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
  254. 0xFFFF0000 ) >> 16) {
  255. case 0x806:
  256. length = 42 + 20; /* FIXME size of ARP */
  257. debug("ARP Packet\n");
  258. break;
  259. case 0x800:
  260. length = 14 + 14 +
  261. (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
  262. 0x10))) & 0xFFFF0000) >> 16);
  263. /* FIXME size of IP packet */
  264. debug ("IP Packet\n");
  265. break;
  266. default:
  267. debug("Other Packet\n");
  268. length = PKTSIZE;
  269. break;
  270. }
  271. xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
  272. etherrxbuff, length);
  273. /* Acknowledge the frame */
  274. reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
  275. reg &= ~XEL_RSR_RECV_DONE_MASK;
  276. out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
  277. debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
  278. NetReceive((uchar *) etherrxbuff, length);
  279. return length;
  280. }
  281. int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
  282. int txpp, int rxpp)
  283. {
  284. struct eth_device *dev;
  285. struct xemaclite *emaclite;
  286. dev = calloc(1, sizeof(*dev));
  287. if (dev == NULL)
  288. return -1;
  289. emaclite = calloc(1, sizeof(struct xemaclite));
  290. if (emaclite == NULL) {
  291. free(dev);
  292. return -1;
  293. }
  294. dev->priv = emaclite;
  295. emaclite->txpp = txpp;
  296. emaclite->rxpp = rxpp;
  297. sprintf(dev->name, "Xelite.%lx", base_addr);
  298. dev->iobase = base_addr;
  299. dev->init = emaclite_init;
  300. dev->halt = emaclite_halt;
  301. dev->send = emaclite_send;
  302. dev->recv = emaclite_recv;
  303. eth_register(dev);
  304. return 1;
  305. }
  306. #ifdef CONFIG_OF_CONTROL
  307. int xilinx_emaclite_init(bd_t *bis)
  308. {
  309. int offset = 0;
  310. u32 ret = 0;
  311. u32 reg;
  312. do {
  313. offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
  314. "xlnx,xps-ethernetlite-1.00.a");
  315. if (offset != -1) {
  316. reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg");
  317. if (reg != FDT_ADDR_T_NONE) {
  318. u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset,
  319. "xlnx,rx-ping-pong", 0);
  320. u32 txpp = fdtdec_get_int(gd->fdt_blob, offset,
  321. "xlnx,tx-ping-pong", 0);
  322. ret |= xilinx_emaclite_initialize(bis, reg,
  323. txpp, rxpp);
  324. }
  325. }
  326. } while (offset != -1);
  327. return ret;
  328. }
  329. #endif