tsec.c 18 KB

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  1. /*
  2. * Freescale Three Speed Ethernet Controller driver
  3. *
  4. * This software may be used and distributed according to the
  5. * terms of the GNU Public License, Version 2, incorporated
  6. * herein by reference.
  7. *
  8. * Copyright 2004-2011 Freescale Semiconductor, Inc.
  9. * (C) Copyright 2003, Motorola, Inc.
  10. * author Andy Fleming
  11. *
  12. */
  13. #include <config.h>
  14. #include <common.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <command.h>
  18. #include <tsec.h>
  19. #include <fsl_mdio.h>
  20. #include <asm/errno.h>
  21. #include <asm/processor.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define TX_BUF_CNT 2
  24. static uint rxIdx; /* index of the current RX buffer */
  25. static uint txIdx; /* index of the current TX buffer */
  26. typedef volatile struct rtxbd {
  27. txbd8_t txbd[TX_BUF_CNT];
  28. rxbd8_t rxbd[PKTBUFSRX];
  29. } RTXBD;
  30. #define MAXCONTROLLERS (8)
  31. static struct tsec_private *privlist[MAXCONTROLLERS];
  32. static int num_tsecs = 0;
  33. #ifdef __GNUC__
  34. static RTXBD rtx __attribute__ ((aligned(8)));
  35. #else
  36. #error "rtx must be 64-bit aligned"
  37. #endif
  38. static int tsec_send(struct eth_device *dev, void *packet, int length);
  39. /* Default initializations for TSEC controllers. */
  40. static struct tsec_info_struct tsec_info[] = {
  41. #ifdef CONFIG_TSEC1
  42. STD_TSEC_INFO(1), /* TSEC1 */
  43. #endif
  44. #ifdef CONFIG_TSEC2
  45. STD_TSEC_INFO(2), /* TSEC2 */
  46. #endif
  47. #ifdef CONFIG_MPC85XX_FEC
  48. {
  49. .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
  50. .devname = CONFIG_MPC85XX_FEC_NAME,
  51. .phyaddr = FEC_PHY_ADDR,
  52. .flags = FEC_FLAGS,
  53. .mii_devname = DEFAULT_MII_NAME
  54. }, /* FEC */
  55. #endif
  56. #ifdef CONFIG_TSEC3
  57. STD_TSEC_INFO(3), /* TSEC3 */
  58. #endif
  59. #ifdef CONFIG_TSEC4
  60. STD_TSEC_INFO(4), /* TSEC4 */
  61. #endif
  62. };
  63. #define TBIANA_SETTINGS ( \
  64. TBIANA_ASYMMETRIC_PAUSE \
  65. | TBIANA_SYMMETRIC_PAUSE \
  66. | TBIANA_FULL_DUPLEX \
  67. )
  68. /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  69. #ifndef CONFIG_TSEC_TBICR_SETTINGS
  70. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  71. TBICR_PHY_RESET \
  72. | TBICR_ANEG_ENABLE \
  73. | TBICR_FULL_DUPLEX \
  74. | TBICR_SPEED1_SET \
  75. )
  76. #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  77. /* Configure the TBI for SGMII operation */
  78. static void tsec_configure_serdes(struct tsec_private *priv)
  79. {
  80. /* Access TBI PHY registers at given TSEC register offset as opposed
  81. * to the register offset used for external PHY accesses */
  82. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  83. 0, TBI_ANA, TBIANA_SETTINGS);
  84. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  85. 0, TBI_TBICON, TBICON_CLK_SELECT);
  86. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  87. 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  88. }
  89. #ifdef CONFIG_MCAST_TFTP
  90. /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  91. /* Set the appropriate hash bit for the given addr */
  92. /* The algorithm works like so:
  93. * 1) Take the Destination Address (ie the multicast address), and
  94. * do a CRC on it (little endian), and reverse the bits of the
  95. * result.
  96. * 2) Use the 8 most significant bits as a hash into a 256-entry
  97. * table. The table is controlled through 8 32-bit registers:
  98. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
  99. * gaddr7. This means that the 3 most significant bits in the
  100. * hash index which gaddr register to use, and the 5 other bits
  101. * indicate which bit (assuming an IBM numbering scheme, which
  102. * for PowerPC (tm) is usually the case) in the tregister holds
  103. * the entry. */
  104. static int
  105. tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
  106. {
  107. struct tsec_private *priv = privlist[1];
  108. volatile tsec_t *regs = priv->regs;
  109. volatile u32 *reg_array, value;
  110. u8 result, whichbit, whichreg;
  111. result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
  112. whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
  113. whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
  114. value = (1 << (31-whichbit));
  115. reg_array = &(regs->hash.gaddr0);
  116. if (set) {
  117. reg_array[whichreg] |= value;
  118. } else {
  119. reg_array[whichreg] &= ~value;
  120. }
  121. return 0;
  122. }
  123. #endif /* Multicast TFTP ? */
  124. /* Initialized required registers to appropriate values, zeroing
  125. * those we don't care about (unless zero is bad, in which case,
  126. * choose a more appropriate value)
  127. */
  128. static void init_registers(tsec_t *regs)
  129. {
  130. /* Clear IEVENT */
  131. out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
  132. out_be32(&regs->imask, IMASK_INIT_CLEAR);
  133. out_be32(&regs->hash.iaddr0, 0);
  134. out_be32(&regs->hash.iaddr1, 0);
  135. out_be32(&regs->hash.iaddr2, 0);
  136. out_be32(&regs->hash.iaddr3, 0);
  137. out_be32(&regs->hash.iaddr4, 0);
  138. out_be32(&regs->hash.iaddr5, 0);
  139. out_be32(&regs->hash.iaddr6, 0);
  140. out_be32(&regs->hash.iaddr7, 0);
  141. out_be32(&regs->hash.gaddr0, 0);
  142. out_be32(&regs->hash.gaddr1, 0);
  143. out_be32(&regs->hash.gaddr2, 0);
  144. out_be32(&regs->hash.gaddr3, 0);
  145. out_be32(&regs->hash.gaddr4, 0);
  146. out_be32(&regs->hash.gaddr5, 0);
  147. out_be32(&regs->hash.gaddr6, 0);
  148. out_be32(&regs->hash.gaddr7, 0);
  149. out_be32(&regs->rctrl, 0x00000000);
  150. /* Init RMON mib registers */
  151. memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
  152. out_be32(&regs->rmon.cam1, 0xffffffff);
  153. out_be32(&regs->rmon.cam2, 0xffffffff);
  154. out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
  155. out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
  156. out_be32(&regs->attr, ATTR_INIT_SETTINGS);
  157. out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
  158. }
  159. /* Configure maccfg2 based on negotiated speed and duplex
  160. * reported by PHY handling code
  161. */
  162. static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
  163. {
  164. tsec_t *regs = priv->regs;
  165. u32 ecntrl, maccfg2;
  166. if (!phydev->link) {
  167. printf("%s: No link.\n", phydev->dev->name);
  168. return;
  169. }
  170. /* clear all bits relative with interface mode */
  171. ecntrl = in_be32(&regs->ecntrl);
  172. ecntrl &= ~ECNTRL_R100;
  173. maccfg2 = in_be32(&regs->maccfg2);
  174. maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
  175. if (phydev->duplex)
  176. maccfg2 |= MACCFG2_FULL_DUPLEX;
  177. switch (phydev->speed) {
  178. case 1000:
  179. maccfg2 |= MACCFG2_GMII;
  180. break;
  181. case 100:
  182. case 10:
  183. maccfg2 |= MACCFG2_MII;
  184. /* Set R100 bit in all modes although
  185. * it is only used in RGMII mode
  186. */
  187. if (phydev->speed == 100)
  188. ecntrl |= ECNTRL_R100;
  189. break;
  190. default:
  191. printf("%s: Speed was bad\n", phydev->dev->name);
  192. break;
  193. }
  194. out_be32(&regs->ecntrl, ecntrl);
  195. out_be32(&regs->maccfg2, maccfg2);
  196. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  197. (phydev->duplex) ? "full" : "half",
  198. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  199. }
  200. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  201. /*
  202. * When MACCFG1[Rx_EN] is enabled during system boot as part
  203. * of the eTSEC port initialization sequence,
  204. * the eTSEC Rx logic may not be properly initialized.
  205. */
  206. void redundant_init(struct eth_device *dev)
  207. {
  208. struct tsec_private *priv = dev->priv;
  209. tsec_t *regs = priv->regs;
  210. uint t, count = 0;
  211. int fail = 1;
  212. static const u8 pkt[] = {
  213. 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
  214. 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
  215. 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
  216. 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
  217. 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
  218. 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
  219. 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
  220. 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
  221. 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
  222. 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  223. 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
  224. 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
  225. 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
  226. 0x71, 0x72};
  227. /* Enable promiscuous mode */
  228. setbits_be32(&regs->rctrl, 0x8);
  229. /* Enable loopback mode */
  230. setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  231. /* Enable transmit and receive */
  232. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  233. /* Tell the DMA it is clear to go */
  234. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  235. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  236. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  237. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  238. do {
  239. tsec_send(dev, (void *)pkt, sizeof(pkt));
  240. /* Wait for buffer to be received */
  241. for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
  242. if (t >= 10 * TOUT_LOOP) {
  243. printf("%s: tsec: rx error\n", dev->name);
  244. break;
  245. }
  246. }
  247. if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
  248. fail = 0;
  249. rtx.rxbd[rxIdx].length = 0;
  250. rtx.rxbd[rxIdx].status =
  251. RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
  252. rxIdx = (rxIdx + 1) % PKTBUFSRX;
  253. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  254. out_be32(&regs->ievent, IEVENT_BSY);
  255. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  256. }
  257. if (fail) {
  258. printf("loopback recv packet error!\n");
  259. clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  260. udelay(1000);
  261. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  262. }
  263. } while ((count++ < 4) && (fail == 1));
  264. if (fail)
  265. panic("eTSEC init fail!\n");
  266. /* Disable promiscuous mode */
  267. clrbits_be32(&regs->rctrl, 0x8);
  268. /* Disable loopback mode */
  269. clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  270. }
  271. #endif
  272. /* Set up the buffers and their descriptors, and bring up the
  273. * interface
  274. */
  275. static void startup_tsec(struct eth_device *dev)
  276. {
  277. int i;
  278. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  279. tsec_t *regs = priv->regs;
  280. /* reset the indices to zero */
  281. rxIdx = 0;
  282. txIdx = 0;
  283. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  284. uint svr;
  285. #endif
  286. /* Point to the buffer descriptors */
  287. out_be32(&regs->tbase, (unsigned int)(&rtx.txbd[txIdx]));
  288. out_be32(&regs->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
  289. /* Initialize the Rx Buffer descriptors */
  290. for (i = 0; i < PKTBUFSRX; i++) {
  291. rtx.rxbd[i].status = RXBD_EMPTY;
  292. rtx.rxbd[i].length = 0;
  293. rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
  294. }
  295. rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
  296. /* Initialize the TX Buffer Descriptors */
  297. for (i = 0; i < TX_BUF_CNT; i++) {
  298. rtx.txbd[i].status = 0;
  299. rtx.txbd[i].length = 0;
  300. rtx.txbd[i].bufPtr = 0;
  301. }
  302. rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
  303. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  304. svr = get_svr();
  305. if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
  306. redundant_init(dev);
  307. #endif
  308. /* Enable Transmit and Receive */
  309. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  310. /* Tell the DMA it is clear to go */
  311. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  312. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  313. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  314. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  315. }
  316. /* This returns the status bits of the device. The return value
  317. * is never checked, and this is what the 8260 driver did, so we
  318. * do the same. Presumably, this would be zero if there were no
  319. * errors
  320. */
  321. static int tsec_send(struct eth_device *dev, void *packet, int length)
  322. {
  323. int i;
  324. int result = 0;
  325. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  326. tsec_t *regs = priv->regs;
  327. /* Find an empty buffer descriptor */
  328. for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
  329. if (i >= TOUT_LOOP) {
  330. debug("%s: tsec: tx buffers full\n", dev->name);
  331. return result;
  332. }
  333. }
  334. rtx.txbd[txIdx].bufPtr = (uint) packet;
  335. rtx.txbd[txIdx].length = length;
  336. rtx.txbd[txIdx].status |=
  337. (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
  338. /* Tell the DMA to go */
  339. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  340. /* Wait for buffer to be transmitted */
  341. for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
  342. if (i >= TOUT_LOOP) {
  343. debug("%s: tsec: tx error\n", dev->name);
  344. return result;
  345. }
  346. }
  347. txIdx = (txIdx + 1) % TX_BUF_CNT;
  348. result = rtx.txbd[txIdx].status & TXBD_STATS;
  349. return result;
  350. }
  351. static int tsec_recv(struct eth_device *dev)
  352. {
  353. int length;
  354. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  355. tsec_t *regs = priv->regs;
  356. while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
  357. length = rtx.rxbd[rxIdx].length;
  358. /* Send the packet up if there were no errors */
  359. if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
  360. NetReceive(NetRxPackets[rxIdx], length - 4);
  361. } else {
  362. printf("Got error %x\n",
  363. (rtx.rxbd[rxIdx].status & RXBD_STATS));
  364. }
  365. rtx.rxbd[rxIdx].length = 0;
  366. /* Set the wrap bit if this is the last element in the list */
  367. rtx.rxbd[rxIdx].status =
  368. RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
  369. rxIdx = (rxIdx + 1) % PKTBUFSRX;
  370. }
  371. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  372. out_be32(&regs->ievent, IEVENT_BSY);
  373. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  374. }
  375. return -1;
  376. }
  377. /* Stop the interface */
  378. static void tsec_halt(struct eth_device *dev)
  379. {
  380. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  381. tsec_t *regs = priv->regs;
  382. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  383. setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  384. while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
  385. != (IEVENT_GRSC | IEVENT_GTSC))
  386. ;
  387. clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
  388. /* Shut down the PHY, as needed */
  389. phy_shutdown(priv->phydev);
  390. }
  391. /* Initializes data structures and registers for the controller,
  392. * and brings the interface up. Returns the link status, meaning
  393. * that it returns success if the link is up, failure otherwise.
  394. * This allows u-boot to find the first active controller.
  395. */
  396. static int tsec_init(struct eth_device *dev, bd_t * bd)
  397. {
  398. uint tempval;
  399. char tmpbuf[MAC_ADDR_LEN];
  400. int i;
  401. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  402. tsec_t *regs = priv->regs;
  403. int ret;
  404. /* Make sure the controller is stopped */
  405. tsec_halt(dev);
  406. /* Init MACCFG2. Defaults to GMII */
  407. out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  408. /* Init ECNTRL */
  409. out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  410. /* Copy the station address into the address registers.
  411. * Backwards, because little endian MACS are dumb */
  412. for (i = 0; i < MAC_ADDR_LEN; i++)
  413. tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
  414. tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
  415. tmpbuf[3];
  416. out_be32(&regs->macstnaddr1, tempval);
  417. tempval = *((uint *) (tmpbuf + 4));
  418. out_be32(&regs->macstnaddr2, tempval);
  419. /* Clear out (for the most part) the other registers */
  420. init_registers(regs);
  421. /* Ready the device for tx/rx */
  422. startup_tsec(dev);
  423. /* Start up the PHY */
  424. ret = phy_startup(priv->phydev);
  425. if (ret) {
  426. printf("Could not initialize PHY %s\n",
  427. priv->phydev->dev->name);
  428. return ret;
  429. }
  430. adjust_link(priv, priv->phydev);
  431. /* If there's no link, fail */
  432. return priv->phydev->link ? 0 : -1;
  433. }
  434. static phy_interface_t tsec_get_interface(struct tsec_private *priv)
  435. {
  436. tsec_t *regs = priv->regs;
  437. u32 ecntrl;
  438. ecntrl = in_be32(&regs->ecntrl);
  439. if (ecntrl & ECNTRL_SGMII_MODE)
  440. return PHY_INTERFACE_MODE_SGMII;
  441. if (ecntrl & ECNTRL_TBI_MODE) {
  442. if (ecntrl & ECNTRL_REDUCED_MODE)
  443. return PHY_INTERFACE_MODE_RTBI;
  444. else
  445. return PHY_INTERFACE_MODE_TBI;
  446. }
  447. if (ecntrl & ECNTRL_REDUCED_MODE) {
  448. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  449. return PHY_INTERFACE_MODE_RMII;
  450. else {
  451. phy_interface_t interface = priv->interface;
  452. /*
  453. * This isn't autodetected, so it must
  454. * be set by the platform code.
  455. */
  456. if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  457. (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
  458. (interface == PHY_INTERFACE_MODE_RGMII_RXID))
  459. return interface;
  460. return PHY_INTERFACE_MODE_RGMII;
  461. }
  462. }
  463. if (priv->flags & TSEC_GIGABIT)
  464. return PHY_INTERFACE_MODE_GMII;
  465. return PHY_INTERFACE_MODE_MII;
  466. }
  467. /* Discover which PHY is attached to the device, and configure it
  468. * properly. If the PHY is not recognized, then return 0
  469. * (failure). Otherwise, return 1
  470. */
  471. static int init_phy(struct eth_device *dev)
  472. {
  473. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  474. struct phy_device *phydev;
  475. tsec_t *regs = priv->regs;
  476. u32 supported = (SUPPORTED_10baseT_Half |
  477. SUPPORTED_10baseT_Full |
  478. SUPPORTED_100baseT_Half |
  479. SUPPORTED_100baseT_Full);
  480. if (priv->flags & TSEC_GIGABIT)
  481. supported |= SUPPORTED_1000baseT_Full;
  482. /* Assign a Physical address to the TBI */
  483. out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
  484. priv->interface = tsec_get_interface(priv);
  485. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  486. tsec_configure_serdes(priv);
  487. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  488. phydev->supported &= supported;
  489. phydev->advertising = phydev->supported;
  490. priv->phydev = phydev;
  491. phy_config(phydev);
  492. return 1;
  493. }
  494. /* Initialize device structure. Returns success if PHY
  495. * initialization succeeded (i.e. if it recognizes the PHY)
  496. */
  497. static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
  498. {
  499. struct eth_device *dev;
  500. int i;
  501. struct tsec_private *priv;
  502. dev = (struct eth_device *)malloc(sizeof *dev);
  503. if (NULL == dev)
  504. return 0;
  505. memset(dev, 0, sizeof *dev);
  506. priv = (struct tsec_private *)malloc(sizeof(*priv));
  507. if (NULL == priv)
  508. return 0;
  509. privlist[num_tsecs++] = priv;
  510. priv->regs = tsec_info->regs;
  511. priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
  512. priv->phyaddr = tsec_info->phyaddr;
  513. priv->flags = tsec_info->flags;
  514. sprintf(dev->name, tsec_info->devname);
  515. priv->interface = tsec_info->interface;
  516. priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
  517. dev->iobase = 0;
  518. dev->priv = priv;
  519. dev->init = tsec_init;
  520. dev->halt = tsec_halt;
  521. dev->send = tsec_send;
  522. dev->recv = tsec_recv;
  523. #ifdef CONFIG_MCAST_TFTP
  524. dev->mcast = tsec_mcast_addr;
  525. #endif
  526. /* Tell u-boot to get the addr from the env */
  527. for (i = 0; i < 6; i++)
  528. dev->enetaddr[i] = 0;
  529. eth_register(dev);
  530. /* Reset the MAC */
  531. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  532. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  533. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  534. /* Try to initialize PHY here, and return */
  535. return init_phy(dev);
  536. }
  537. /*
  538. * Initialize all the TSEC devices
  539. *
  540. * Returns the number of TSEC devices that were initialized
  541. */
  542. int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
  543. {
  544. int i;
  545. int ret, count = 0;
  546. for (i = 0; i < num; i++) {
  547. ret = tsec_initialize(bis, &tsecs[i]);
  548. if (ret > 0)
  549. count += ret;
  550. }
  551. return count;
  552. }
  553. int tsec_standard_init(bd_t *bis)
  554. {
  555. struct fsl_pq_mdio_info info;
  556. info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  557. info.name = DEFAULT_MII_NAME;
  558. fsl_pq_mdio_init(bis, &info);
  559. return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
  560. }