macb.c 16 KB

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  1. /*
  2. * Copyright (C) 2005-2006 Atmel Corporation
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. /*
  8. * The u-boot networking stack is a little weird. It seems like the
  9. * networking core allocates receive buffers up front without any
  10. * regard to the hardware that's supposed to actually receive those
  11. * packets.
  12. *
  13. * The MACB receives packets into 128-byte receive buffers, so the
  14. * buffers allocated by the core isn't very practical to use. We'll
  15. * allocate our own, but we need one such buffer in case a packet
  16. * wraps around the DMA ring so that we have to copy it.
  17. *
  18. * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
  19. * configuration header. This way, the core allocates one RX buffer
  20. * and one TX buffer, each of which can hold a ethernet packet of
  21. * maximum size.
  22. *
  23. * For some reason, the networking core unconditionally specifies a
  24. * 32-byte packet "alignment" (which really should be called
  25. * "padding"). MACB shouldn't need that, but we'll refrain from any
  26. * core modifications here...
  27. */
  28. #include <net.h>
  29. #include <netdev.h>
  30. #include <malloc.h>
  31. #include <miiphy.h>
  32. #include <linux/mii.h>
  33. #include <asm/io.h>
  34. #include <asm/dma-mapping.h>
  35. #include <asm/arch/clk.h>
  36. #include "macb.h"
  37. #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
  38. #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
  39. #define CONFIG_SYS_MACB_TX_RING_SIZE 16
  40. #define CONFIG_SYS_MACB_TX_TIMEOUT 1000
  41. #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
  42. struct macb_dma_desc {
  43. u32 addr;
  44. u32 ctrl;
  45. };
  46. #define RXADDR_USED 0x00000001
  47. #define RXADDR_WRAP 0x00000002
  48. #define RXBUF_FRMLEN_MASK 0x00000fff
  49. #define RXBUF_FRAME_START 0x00004000
  50. #define RXBUF_FRAME_END 0x00008000
  51. #define RXBUF_TYPEID_MATCH 0x00400000
  52. #define RXBUF_ADDR4_MATCH 0x00800000
  53. #define RXBUF_ADDR3_MATCH 0x01000000
  54. #define RXBUF_ADDR2_MATCH 0x02000000
  55. #define RXBUF_ADDR1_MATCH 0x04000000
  56. #define RXBUF_BROADCAST 0x80000000
  57. #define TXBUF_FRMLEN_MASK 0x000007ff
  58. #define TXBUF_FRAME_END 0x00008000
  59. #define TXBUF_NOCRC 0x00010000
  60. #define TXBUF_EXHAUSTED 0x08000000
  61. #define TXBUF_UNDERRUN 0x10000000
  62. #define TXBUF_MAXRETRY 0x20000000
  63. #define TXBUF_WRAP 0x40000000
  64. #define TXBUF_USED 0x80000000
  65. struct macb_device {
  66. void *regs;
  67. unsigned int rx_tail;
  68. unsigned int tx_head;
  69. unsigned int tx_tail;
  70. void *rx_buffer;
  71. void *tx_buffer;
  72. struct macb_dma_desc *rx_ring;
  73. struct macb_dma_desc *tx_ring;
  74. unsigned long rx_buffer_dma;
  75. unsigned long rx_ring_dma;
  76. unsigned long tx_ring_dma;
  77. const struct device *dev;
  78. struct eth_device netdev;
  79. unsigned short phy_addr;
  80. struct mii_dev *bus;
  81. };
  82. #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
  83. static int macb_is_gem(struct macb_device *macb)
  84. {
  85. return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
  86. }
  87. static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
  88. {
  89. unsigned long netctl;
  90. unsigned long netstat;
  91. unsigned long frame;
  92. netctl = macb_readl(macb, NCR);
  93. netctl |= MACB_BIT(MPE);
  94. macb_writel(macb, NCR, netctl);
  95. frame = (MACB_BF(SOF, 1)
  96. | MACB_BF(RW, 1)
  97. | MACB_BF(PHYA, macb->phy_addr)
  98. | MACB_BF(REGA, reg)
  99. | MACB_BF(CODE, 2)
  100. | MACB_BF(DATA, value));
  101. macb_writel(macb, MAN, frame);
  102. do {
  103. netstat = macb_readl(macb, NSR);
  104. } while (!(netstat & MACB_BIT(IDLE)));
  105. netctl = macb_readl(macb, NCR);
  106. netctl &= ~MACB_BIT(MPE);
  107. macb_writel(macb, NCR, netctl);
  108. }
  109. static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
  110. {
  111. unsigned long netctl;
  112. unsigned long netstat;
  113. unsigned long frame;
  114. netctl = macb_readl(macb, NCR);
  115. netctl |= MACB_BIT(MPE);
  116. macb_writel(macb, NCR, netctl);
  117. frame = (MACB_BF(SOF, 1)
  118. | MACB_BF(RW, 2)
  119. | MACB_BF(PHYA, macb->phy_addr)
  120. | MACB_BF(REGA, reg)
  121. | MACB_BF(CODE, 2));
  122. macb_writel(macb, MAN, frame);
  123. do {
  124. netstat = macb_readl(macb, NSR);
  125. } while (!(netstat & MACB_BIT(IDLE)));
  126. frame = macb_readl(macb, MAN);
  127. netctl = macb_readl(macb, NCR);
  128. netctl &= ~MACB_BIT(MPE);
  129. macb_writel(macb, NCR, netctl);
  130. return MACB_BFEXT(DATA, frame);
  131. }
  132. void __weak arch_get_mdio_control(const char *name)
  133. {
  134. return;
  135. }
  136. #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  137. int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
  138. {
  139. struct eth_device *dev = eth_get_dev_by_name(devname);
  140. struct macb_device *macb = to_macb(dev);
  141. if ( macb->phy_addr != phy_adr )
  142. return -1;
  143. arch_get_mdio_control(devname);
  144. *value = macb_mdio_read(macb, reg);
  145. return 0;
  146. }
  147. int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
  148. {
  149. struct eth_device *dev = eth_get_dev_by_name(devname);
  150. struct macb_device *macb = to_macb(dev);
  151. if ( macb->phy_addr != phy_adr )
  152. return -1;
  153. arch_get_mdio_control(devname);
  154. macb_mdio_write(macb, reg, value);
  155. return 0;
  156. }
  157. #endif
  158. #if defined(CONFIG_CMD_NET)
  159. static int macb_send(struct eth_device *netdev, void *packet, int length)
  160. {
  161. struct macb_device *macb = to_macb(netdev);
  162. unsigned long paddr, ctrl;
  163. unsigned int tx_head = macb->tx_head;
  164. int i;
  165. paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
  166. ctrl = length & TXBUF_FRMLEN_MASK;
  167. ctrl |= TXBUF_FRAME_END;
  168. if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) {
  169. ctrl |= TXBUF_WRAP;
  170. macb->tx_head = 0;
  171. } else
  172. macb->tx_head++;
  173. macb->tx_ring[tx_head].ctrl = ctrl;
  174. macb->tx_ring[tx_head].addr = paddr;
  175. barrier();
  176. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
  177. /*
  178. * I guess this is necessary because the networking core may
  179. * re-use the transmit buffer as soon as we return...
  180. */
  181. for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) {
  182. barrier();
  183. ctrl = macb->tx_ring[tx_head].ctrl;
  184. if (ctrl & TXBUF_USED)
  185. break;
  186. udelay(1);
  187. }
  188. dma_unmap_single(packet, length, paddr);
  189. if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) {
  190. if (ctrl & TXBUF_UNDERRUN)
  191. printf("%s: TX underrun\n", netdev->name);
  192. if (ctrl & TXBUF_EXHAUSTED)
  193. printf("%s: TX buffers exhausted in mid frame\n",
  194. netdev->name);
  195. } else {
  196. printf("%s: TX timeout\n", netdev->name);
  197. }
  198. /* No one cares anyway */
  199. return 0;
  200. }
  201. static void reclaim_rx_buffers(struct macb_device *macb,
  202. unsigned int new_tail)
  203. {
  204. unsigned int i;
  205. i = macb->rx_tail;
  206. while (i > new_tail) {
  207. macb->rx_ring[i].addr &= ~RXADDR_USED;
  208. i++;
  209. if (i > CONFIG_SYS_MACB_RX_RING_SIZE)
  210. i = 0;
  211. }
  212. while (i < new_tail) {
  213. macb->rx_ring[i].addr &= ~RXADDR_USED;
  214. i++;
  215. }
  216. barrier();
  217. macb->rx_tail = new_tail;
  218. }
  219. static int macb_recv(struct eth_device *netdev)
  220. {
  221. struct macb_device *macb = to_macb(netdev);
  222. unsigned int rx_tail = macb->rx_tail;
  223. void *buffer;
  224. int length;
  225. int wrapped = 0;
  226. u32 status;
  227. for (;;) {
  228. if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
  229. return -1;
  230. status = macb->rx_ring[rx_tail].ctrl;
  231. if (status & RXBUF_FRAME_START) {
  232. if (rx_tail != macb->rx_tail)
  233. reclaim_rx_buffers(macb, rx_tail);
  234. wrapped = 0;
  235. }
  236. if (status & RXBUF_FRAME_END) {
  237. buffer = macb->rx_buffer + 128 * macb->rx_tail;
  238. length = status & RXBUF_FRMLEN_MASK;
  239. if (wrapped) {
  240. unsigned int headlen, taillen;
  241. headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE
  242. - macb->rx_tail);
  243. taillen = length - headlen;
  244. memcpy((void *)NetRxPackets[0],
  245. buffer, headlen);
  246. memcpy((void *)NetRxPackets[0] + headlen,
  247. macb->rx_buffer, taillen);
  248. buffer = (void *)NetRxPackets[0];
  249. }
  250. NetReceive(buffer, length);
  251. if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE)
  252. rx_tail = 0;
  253. reclaim_rx_buffers(macb, rx_tail);
  254. } else {
  255. if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) {
  256. wrapped = 1;
  257. rx_tail = 0;
  258. }
  259. }
  260. barrier();
  261. }
  262. return 0;
  263. }
  264. static void macb_phy_reset(struct macb_device *macb)
  265. {
  266. struct eth_device *netdev = &macb->netdev;
  267. int i;
  268. u16 status, adv;
  269. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  270. macb_mdio_write(macb, MII_ADVERTISE, adv);
  271. printf("%s: Starting autonegotiation...\n", netdev->name);
  272. macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
  273. | BMCR_ANRESTART));
  274. for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
  275. status = macb_mdio_read(macb, MII_BMSR);
  276. if (status & BMSR_ANEGCOMPLETE)
  277. break;
  278. udelay(100);
  279. }
  280. if (status & BMSR_ANEGCOMPLETE)
  281. printf("%s: Autonegotiation complete\n", netdev->name);
  282. else
  283. printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  284. netdev->name, status);
  285. }
  286. #ifdef CONFIG_MACB_SEARCH_PHY
  287. static int macb_phy_find(struct macb_device *macb)
  288. {
  289. int i;
  290. u16 phy_id;
  291. /* Search for PHY... */
  292. for (i = 0; i < 32; i++) {
  293. macb->phy_addr = i;
  294. phy_id = macb_mdio_read(macb, MII_PHYSID1);
  295. if (phy_id != 0xffff) {
  296. printf("%s: PHY present at %d\n", macb->netdev.name, i);
  297. return 1;
  298. }
  299. }
  300. /* PHY isn't up to snuff */
  301. printf("%s: PHY not found\n", macb->netdev.name);
  302. return 0;
  303. }
  304. #endif /* CONFIG_MACB_SEARCH_PHY */
  305. static int macb_phy_init(struct macb_device *macb)
  306. {
  307. struct eth_device *netdev = &macb->netdev;
  308. #ifdef CONFIG_PHYLIB
  309. struct phy_device *phydev;
  310. #endif
  311. u32 ncfgr;
  312. u16 phy_id, status, adv, lpa;
  313. int media, speed, duplex;
  314. int i;
  315. arch_get_mdio_control(netdev->name);
  316. #ifdef CONFIG_MACB_SEARCH_PHY
  317. /* Auto-detect phy_addr */
  318. if (!macb_phy_find(macb)) {
  319. return 0;
  320. }
  321. #endif /* CONFIG_MACB_SEARCH_PHY */
  322. /* Check if the PHY is up to snuff... */
  323. phy_id = macb_mdio_read(macb, MII_PHYSID1);
  324. if (phy_id == 0xffff) {
  325. printf("%s: No PHY present\n", netdev->name);
  326. return 0;
  327. }
  328. #ifdef CONFIG_PHYLIB
  329. phydev->bus = macb->bus;
  330. phydev->dev = netdev;
  331. phydev->addr = macb->phy_addr;
  332. phy_config(phydev);
  333. #endif
  334. status = macb_mdio_read(macb, MII_BMSR);
  335. if (!(status & BMSR_LSTATUS)) {
  336. /* Try to re-negotiate if we don't have link already. */
  337. macb_phy_reset(macb);
  338. for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
  339. status = macb_mdio_read(macb, MII_BMSR);
  340. if (status & BMSR_LSTATUS)
  341. break;
  342. udelay(100);
  343. }
  344. }
  345. if (!(status & BMSR_LSTATUS)) {
  346. printf("%s: link down (status: 0x%04x)\n",
  347. netdev->name, status);
  348. return 0;
  349. }
  350. /* First check for GMAC */
  351. if (macb_is_gem(macb)) {
  352. lpa = macb_mdio_read(macb, MII_STAT1000);
  353. if (lpa & (1 << 11)) {
  354. speed = 1000;
  355. duplex = 1;
  356. } else {
  357. if (lpa & (1 << 10)) {
  358. speed = 1000;
  359. duplex = 1;
  360. } else {
  361. speed = 0;
  362. }
  363. }
  364. if (speed == 1000) {
  365. printf("%s: link up, %dMbps %s-duplex (lpa: 0x%04x)\n",
  366. netdev->name,
  367. speed,
  368. duplex ? "full" : "half",
  369. lpa);
  370. ncfgr = macb_readl(macb, NCFGR);
  371. ncfgr &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD));
  372. if (speed)
  373. ncfgr |= GEM_BIT(GBE);
  374. if (duplex)
  375. ncfgr |= MACB_BIT(FD);
  376. macb_writel(macb, NCFGR, ncfgr);
  377. return 1;
  378. }
  379. }
  380. /* fall back for EMAC checking */
  381. adv = macb_mdio_read(macb, MII_ADVERTISE);
  382. lpa = macb_mdio_read(macb, MII_LPA);
  383. media = mii_nway_result(lpa & adv);
  384. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  385. ? 1 : 0);
  386. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  387. printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
  388. netdev->name,
  389. speed ? "100" : "10",
  390. duplex ? "full" : "half",
  391. lpa);
  392. ncfgr = macb_readl(macb, NCFGR);
  393. ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  394. if (speed)
  395. ncfgr |= MACB_BIT(SPD);
  396. if (duplex)
  397. ncfgr |= MACB_BIT(FD);
  398. macb_writel(macb, NCFGR, ncfgr);
  399. return 1;
  400. }
  401. static int macb_init(struct eth_device *netdev, bd_t *bd)
  402. {
  403. struct macb_device *macb = to_macb(netdev);
  404. unsigned long paddr;
  405. int i;
  406. /*
  407. * macb_halt should have been called at some point before now,
  408. * so we'll assume the controller is idle.
  409. */
  410. /* initialize DMA descriptors */
  411. paddr = macb->rx_buffer_dma;
  412. for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) {
  413. if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1))
  414. paddr |= RXADDR_WRAP;
  415. macb->rx_ring[i].addr = paddr;
  416. macb->rx_ring[i].ctrl = 0;
  417. paddr += 128;
  418. }
  419. for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) {
  420. macb->tx_ring[i].addr = 0;
  421. if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1))
  422. macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
  423. else
  424. macb->tx_ring[i].ctrl = TXBUF_USED;
  425. }
  426. macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
  427. macb_writel(macb, RBQP, macb->rx_ring_dma);
  428. macb_writel(macb, TBQP, macb->tx_ring_dma);
  429. if (macb_is_gem(macb)) {
  430. #ifdef CONFIG_RGMII
  431. gem_writel(macb, UR, GEM_BIT(RGMII));
  432. #else
  433. gem_writel(macb, UR, 0);
  434. #endif
  435. } else {
  436. /* choose RMII or MII mode. This depends on the board */
  437. #ifdef CONFIG_RMII
  438. #ifdef CONFIG_AT91FAMILY
  439. macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
  440. #else
  441. macb_writel(macb, USRIO, 0);
  442. #endif
  443. #else
  444. #ifdef CONFIG_AT91FAMILY
  445. macb_writel(macb, USRIO, MACB_BIT(CLKEN));
  446. #else
  447. macb_writel(macb, USRIO, MACB_BIT(MII));
  448. #endif
  449. #endif /* CONFIG_RMII */
  450. }
  451. if (!macb_phy_init(macb))
  452. return -1;
  453. /* Enable TX and RX */
  454. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
  455. return 0;
  456. }
  457. static void macb_halt(struct eth_device *netdev)
  458. {
  459. struct macb_device *macb = to_macb(netdev);
  460. u32 ncr, tsr;
  461. /* Halt the controller and wait for any ongoing transmission to end. */
  462. ncr = macb_readl(macb, NCR);
  463. ncr |= MACB_BIT(THALT);
  464. macb_writel(macb, NCR, ncr);
  465. do {
  466. tsr = macb_readl(macb, TSR);
  467. } while (tsr & MACB_BIT(TGO));
  468. /* Disable TX and RX, and clear statistics */
  469. macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
  470. }
  471. static int macb_write_hwaddr(struct eth_device *dev)
  472. {
  473. struct macb_device *macb = to_macb(dev);
  474. u32 hwaddr_bottom;
  475. u16 hwaddr_top;
  476. /* set hardware address */
  477. hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
  478. dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
  479. macb_writel(macb, SA1B, hwaddr_bottom);
  480. hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
  481. macb_writel(macb, SA1T, hwaddr_top);
  482. return 0;
  483. }
  484. static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
  485. {
  486. u32 config;
  487. unsigned long macb_hz = get_macb_pclk_rate(id);
  488. if (macb_hz < 20000000)
  489. config = MACB_BF(CLK, MACB_CLK_DIV8);
  490. else if (macb_hz < 40000000)
  491. config = MACB_BF(CLK, MACB_CLK_DIV16);
  492. else if (macb_hz < 80000000)
  493. config = MACB_BF(CLK, MACB_CLK_DIV32);
  494. else
  495. config = MACB_BF(CLK, MACB_CLK_DIV64);
  496. return config;
  497. }
  498. static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
  499. {
  500. u32 config;
  501. unsigned long macb_hz = get_macb_pclk_rate(id);
  502. if (macb_hz < 20000000)
  503. config = GEM_BF(CLK, GEM_CLK_DIV8);
  504. else if (macb_hz < 40000000)
  505. config = GEM_BF(CLK, GEM_CLK_DIV16);
  506. else if (macb_hz < 80000000)
  507. config = GEM_BF(CLK, GEM_CLK_DIV32);
  508. else if (macb_hz < 120000000)
  509. config = GEM_BF(CLK, GEM_CLK_DIV48);
  510. else if (macb_hz < 160000000)
  511. config = GEM_BF(CLK, GEM_CLK_DIV64);
  512. else
  513. config = GEM_BF(CLK, GEM_CLK_DIV96);
  514. return config;
  515. }
  516. int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
  517. {
  518. struct macb_device *macb;
  519. struct eth_device *netdev;
  520. u32 ncfgr;
  521. macb = malloc(sizeof(struct macb_device));
  522. if (!macb) {
  523. printf("Error: Failed to allocate memory for MACB%d\n", id);
  524. return -1;
  525. }
  526. memset(macb, 0, sizeof(struct macb_device));
  527. netdev = &macb->netdev;
  528. macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
  529. &macb->rx_buffer_dma);
  530. macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
  531. * sizeof(struct macb_dma_desc),
  532. &macb->rx_ring_dma);
  533. macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
  534. * sizeof(struct macb_dma_desc),
  535. &macb->tx_ring_dma);
  536. macb->regs = regs;
  537. macb->phy_addr = phy_addr;
  538. if (macb_is_gem(macb))
  539. sprintf(netdev->name, "gmac%d", id);
  540. else
  541. sprintf(netdev->name, "macb%d", id);
  542. netdev->init = macb_init;
  543. netdev->halt = macb_halt;
  544. netdev->send = macb_send;
  545. netdev->recv = macb_recv;
  546. netdev->write_hwaddr = macb_write_hwaddr;
  547. /*
  548. * Do some basic initialization so that we at least can talk
  549. * to the PHY
  550. */
  551. if (macb_is_gem(macb)) {
  552. ncfgr = gem_mdc_clk_div(id, macb);
  553. ncfgr |= GEM_BF(DBW, 1);
  554. } else {
  555. ncfgr = macb_mdc_clk_div(id, macb);
  556. }
  557. macb_writel(macb, NCFGR, ncfgr);
  558. eth_register(netdev);
  559. #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  560. miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
  561. macb->bus = miiphy_get_dev_by_name(netdev->name);
  562. #endif
  563. return 0;
  564. }
  565. #endif