ethoc.c 13 KB

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  1. /*
  2. * Opencore 10/100 ethernet mac driver
  3. *
  4. * Copyright (C) 2007-2008 Avionic Design Development GmbH
  5. * Copyright (C) 2008-2009 Avionic Design GmbH
  6. * Thierry Reding <thierry.reding@avionic-design.de>
  7. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <miiphy.h>
  18. #include <asm/io.h>
  19. #include <asm/cache.h>
  20. /* register offsets */
  21. #define MODER 0x00
  22. #define INT_SOURCE 0x04
  23. #define INT_MASK 0x08
  24. #define IPGT 0x0c
  25. #define IPGR1 0x10
  26. #define IPGR2 0x14
  27. #define PACKETLEN 0x18
  28. #define COLLCONF 0x1c
  29. #define TX_BD_NUM 0x20
  30. #define CTRLMODER 0x24
  31. #define MIIMODER 0x28
  32. #define MIICOMMAND 0x2c
  33. #define MIIADDRESS 0x30
  34. #define MIITX_DATA 0x34
  35. #define MIIRX_DATA 0x38
  36. #define MIISTATUS 0x3c
  37. #define MAC_ADDR0 0x40
  38. #define MAC_ADDR1 0x44
  39. #define ETH_HASH0 0x48
  40. #define ETH_HASH1 0x4c
  41. #define ETH_TXCTRL 0x50
  42. /* mode register */
  43. #define MODER_RXEN (1 << 0) /* receive enable */
  44. #define MODER_TXEN (1 << 1) /* transmit enable */
  45. #define MODER_NOPRE (1 << 2) /* no preamble */
  46. #define MODER_BRO (1 << 3) /* broadcast address */
  47. #define MODER_IAM (1 << 4) /* individual address mode */
  48. #define MODER_PRO (1 << 5) /* promiscuous mode */
  49. #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
  50. #define MODER_LOOP (1 << 7) /* loopback */
  51. #define MODER_NBO (1 << 8) /* no back-off */
  52. #define MODER_EDE (1 << 9) /* excess defer enable */
  53. #define MODER_FULLD (1 << 10) /* full duplex */
  54. #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
  55. #define MODER_DCRC (1 << 12) /* delayed CRC enable */
  56. #define MODER_CRC (1 << 13) /* CRC enable */
  57. #define MODER_HUGE (1 << 14) /* huge packets enable */
  58. #define MODER_PAD (1 << 15) /* padding enabled */
  59. #define MODER_RSM (1 << 16) /* receive small packets */
  60. /* interrupt source and mask registers */
  61. #define INT_MASK_TXF (1 << 0) /* transmit frame */
  62. #define INT_MASK_TXE (1 << 1) /* transmit error */
  63. #define INT_MASK_RXF (1 << 2) /* receive frame */
  64. #define INT_MASK_RXE (1 << 3) /* receive error */
  65. #define INT_MASK_BUSY (1 << 4)
  66. #define INT_MASK_TXC (1 << 5) /* transmit control frame */
  67. #define INT_MASK_RXC (1 << 6) /* receive control frame */
  68. #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
  69. #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
  70. #define INT_MASK_ALL ( \
  71. INT_MASK_TXF | INT_MASK_TXE | \
  72. INT_MASK_RXF | INT_MASK_RXE | \
  73. INT_MASK_TXC | INT_MASK_RXC | \
  74. INT_MASK_BUSY \
  75. )
  76. /* packet length register */
  77. #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
  78. #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
  79. #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
  80. PACKETLEN_MAX(max))
  81. /* transmit buffer number register */
  82. #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
  83. /* control module mode register */
  84. #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
  85. #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
  86. #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
  87. /* MII mode register */
  88. #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
  89. #define MIIMODER_NOPRE (1 << 8) /* no preamble */
  90. /* MII command register */
  91. #define MIICOMMAND_SCAN (1 << 0) /* scan status */
  92. #define MIICOMMAND_READ (1 << 1) /* read status */
  93. #define MIICOMMAND_WRITE (1 << 2) /* write control data */
  94. /* MII address register */
  95. #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
  96. #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
  97. #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
  98. MIIADDRESS_RGAD(reg))
  99. /* MII transmit data register */
  100. #define MIITX_DATA_VAL(x) ((x) & 0xffff)
  101. /* MII receive data register */
  102. #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
  103. /* MII status register */
  104. #define MIISTATUS_LINKFAIL (1 << 0)
  105. #define MIISTATUS_BUSY (1 << 1)
  106. #define MIISTATUS_INVALID (1 << 2)
  107. /* TX buffer descriptor */
  108. #define TX_BD_CS (1 << 0) /* carrier sense lost */
  109. #define TX_BD_DF (1 << 1) /* defer indication */
  110. #define TX_BD_LC (1 << 2) /* late collision */
  111. #define TX_BD_RL (1 << 3) /* retransmission limit */
  112. #define TX_BD_RETRY_MASK (0x00f0)
  113. #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
  114. #define TX_BD_UR (1 << 8) /* transmitter underrun */
  115. #define TX_BD_CRC (1 << 11) /* TX CRC enable */
  116. #define TX_BD_PAD (1 << 12) /* pad enable */
  117. #define TX_BD_WRAP (1 << 13)
  118. #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
  119. #define TX_BD_READY (1 << 15) /* TX buffer ready */
  120. #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
  121. #define TX_BD_LEN_MASK (0xffff << 16)
  122. #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
  123. TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
  124. /* RX buffer descriptor */
  125. #define RX_BD_LC (1 << 0) /* late collision */
  126. #define RX_BD_CRC (1 << 1) /* RX CRC error */
  127. #define RX_BD_SF (1 << 2) /* short frame */
  128. #define RX_BD_TL (1 << 3) /* too long */
  129. #define RX_BD_DN (1 << 4) /* dribble nibble */
  130. #define RX_BD_IS (1 << 5) /* invalid symbol */
  131. #define RX_BD_OR (1 << 6) /* receiver overrun */
  132. #define RX_BD_MISS (1 << 7)
  133. #define RX_BD_CF (1 << 8) /* control frame */
  134. #define RX_BD_WRAP (1 << 13)
  135. #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
  136. #define RX_BD_EMPTY (1 << 15)
  137. #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
  138. #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
  139. RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
  140. #define ETHOC_BUFSIZ 1536
  141. #define ETHOC_ZLEN 64
  142. #define ETHOC_BD_BASE 0x400
  143. #define ETHOC_TIMEOUT (HZ / 2)
  144. #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
  145. /**
  146. * struct ethoc - driver-private device structure
  147. * @num_tx: number of send buffers
  148. * @cur_tx: last send buffer written
  149. * @dty_tx: last buffer actually sent
  150. * @num_rx: number of receive buffers
  151. * @cur_rx: current receive buffer
  152. */
  153. struct ethoc {
  154. u32 num_tx;
  155. u32 cur_tx;
  156. u32 dty_tx;
  157. u32 num_rx;
  158. u32 cur_rx;
  159. };
  160. /**
  161. * struct ethoc_bd - buffer descriptor
  162. * @stat: buffer statistics
  163. * @addr: physical memory address
  164. */
  165. struct ethoc_bd {
  166. u32 stat;
  167. u32 addr;
  168. };
  169. static inline u32 ethoc_read(struct eth_device *dev, loff_t offset)
  170. {
  171. return readl(dev->iobase + offset);
  172. }
  173. static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data)
  174. {
  175. writel(data, dev->iobase + offset);
  176. }
  177. static inline void ethoc_read_bd(struct eth_device *dev, int index,
  178. struct ethoc_bd *bd)
  179. {
  180. loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  181. bd->stat = ethoc_read(dev, offset + 0);
  182. bd->addr = ethoc_read(dev, offset + 4);
  183. }
  184. static inline void ethoc_write_bd(struct eth_device *dev, int index,
  185. const struct ethoc_bd *bd)
  186. {
  187. loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  188. ethoc_write(dev, offset + 0, bd->stat);
  189. ethoc_write(dev, offset + 4, bd->addr);
  190. }
  191. static int ethoc_set_mac_address(struct eth_device *dev)
  192. {
  193. u8 *mac = dev->enetaddr;
  194. ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
  195. (mac[4] << 8) | (mac[5] << 0));
  196. ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
  197. return 0;
  198. }
  199. static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask)
  200. {
  201. ethoc_write(dev, INT_SOURCE, mask);
  202. }
  203. static inline void ethoc_enable_rx_and_tx(struct eth_device *dev)
  204. {
  205. u32 mode = ethoc_read(dev, MODER);
  206. mode |= MODER_RXEN | MODER_TXEN;
  207. ethoc_write(dev, MODER, mode);
  208. }
  209. static inline void ethoc_disable_rx_and_tx(struct eth_device *dev)
  210. {
  211. u32 mode = ethoc_read(dev, MODER);
  212. mode &= ~(MODER_RXEN | MODER_TXEN);
  213. ethoc_write(dev, MODER, mode);
  214. }
  215. static int ethoc_init_ring(struct eth_device *dev)
  216. {
  217. struct ethoc *priv = (struct ethoc *)dev->priv;
  218. struct ethoc_bd bd;
  219. int i;
  220. priv->cur_tx = 0;
  221. priv->dty_tx = 0;
  222. priv->cur_rx = 0;
  223. /* setup transmission buffers */
  224. bd.stat = TX_BD_IRQ | TX_BD_CRC;
  225. for (i = 0; i < priv->num_tx; i++) {
  226. if (i == priv->num_tx - 1)
  227. bd.stat |= TX_BD_WRAP;
  228. ethoc_write_bd(dev, i, &bd);
  229. }
  230. bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
  231. for (i = 0; i < priv->num_rx; i++) {
  232. bd.addr = (u32)NetRxPackets[i];
  233. if (i == priv->num_rx - 1)
  234. bd.stat |= RX_BD_WRAP;
  235. flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
  236. ethoc_write_bd(dev, priv->num_tx + i, &bd);
  237. }
  238. return 0;
  239. }
  240. static int ethoc_reset(struct eth_device *dev)
  241. {
  242. u32 mode;
  243. /* TODO: reset controller? */
  244. ethoc_disable_rx_and_tx(dev);
  245. /* TODO: setup registers */
  246. /* enable FCS generation and automatic padding */
  247. mode = ethoc_read(dev, MODER);
  248. mode |= MODER_CRC | MODER_PAD;
  249. ethoc_write(dev, MODER, mode);
  250. /* set full-duplex mode */
  251. mode = ethoc_read(dev, MODER);
  252. mode |= MODER_FULLD;
  253. ethoc_write(dev, MODER, mode);
  254. ethoc_write(dev, IPGT, 0x15);
  255. ethoc_ack_irq(dev, INT_MASK_ALL);
  256. ethoc_enable_rx_and_tx(dev);
  257. return 0;
  258. }
  259. static int ethoc_init(struct eth_device *dev, bd_t * bd)
  260. {
  261. struct ethoc *priv = (struct ethoc *)dev->priv;
  262. printf("ethoc\n");
  263. priv->num_tx = 1;
  264. priv->num_rx = PKTBUFSRX;
  265. ethoc_write(dev, TX_BD_NUM, priv->num_tx);
  266. ethoc_init_ring(dev);
  267. ethoc_reset(dev);
  268. return 0;
  269. }
  270. static int ethoc_update_rx_stats(struct ethoc_bd *bd)
  271. {
  272. int ret = 0;
  273. if (bd->stat & RX_BD_TL) {
  274. debug("ETHOC: " "RX: frame too long\n");
  275. ret++;
  276. }
  277. if (bd->stat & RX_BD_SF) {
  278. debug("ETHOC: " "RX: frame too short\n");
  279. ret++;
  280. }
  281. if (bd->stat & RX_BD_DN)
  282. debug("ETHOC: " "RX: dribble nibble\n");
  283. if (bd->stat & RX_BD_CRC) {
  284. debug("ETHOC: " "RX: wrong CRC\n");
  285. ret++;
  286. }
  287. if (bd->stat & RX_BD_OR) {
  288. debug("ETHOC: " "RX: overrun\n");
  289. ret++;
  290. }
  291. if (bd->stat & RX_BD_LC) {
  292. debug("ETHOC: " "RX: late collision\n");
  293. ret++;
  294. }
  295. return ret;
  296. }
  297. static int ethoc_rx(struct eth_device *dev, int limit)
  298. {
  299. struct ethoc *priv = (struct ethoc *)dev->priv;
  300. int count;
  301. for (count = 0; count < limit; ++count) {
  302. u32 entry;
  303. struct ethoc_bd bd;
  304. entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
  305. ethoc_read_bd(dev, entry, &bd);
  306. if (bd.stat & RX_BD_EMPTY)
  307. break;
  308. debug("%s(): RX buffer %d, %x received\n",
  309. __func__, priv->cur_rx, bd.stat);
  310. if (ethoc_update_rx_stats(&bd) == 0) {
  311. int size = bd.stat >> 16;
  312. size -= 4; /* strip the CRC */
  313. NetReceive((void *)bd.addr, size);
  314. }
  315. /* clear the buffer descriptor so it can be reused */
  316. flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
  317. bd.stat &= ~RX_BD_STATS;
  318. bd.stat |= RX_BD_EMPTY;
  319. ethoc_write_bd(dev, entry, &bd);
  320. priv->cur_rx++;
  321. }
  322. return count;
  323. }
  324. static int ethoc_update_tx_stats(struct ethoc_bd *bd)
  325. {
  326. if (bd->stat & TX_BD_LC)
  327. debug("ETHOC: " "TX: late collision\n");
  328. if (bd->stat & TX_BD_RL)
  329. debug("ETHOC: " "TX: retransmit limit\n");
  330. if (bd->stat & TX_BD_UR)
  331. debug("ETHOC: " "TX: underrun\n");
  332. if (bd->stat & TX_BD_CS)
  333. debug("ETHOC: " "TX: carrier sense lost\n");
  334. return 0;
  335. }
  336. static void ethoc_tx(struct eth_device *dev)
  337. {
  338. struct ethoc *priv = (struct ethoc *)dev->priv;
  339. u32 entry = priv->dty_tx % priv->num_tx;
  340. struct ethoc_bd bd;
  341. ethoc_read_bd(dev, entry, &bd);
  342. if ((bd.stat & TX_BD_READY) == 0)
  343. (void)ethoc_update_tx_stats(&bd);
  344. }
  345. static int ethoc_send(struct eth_device *dev, void *packet, int length)
  346. {
  347. struct ethoc *priv = (struct ethoc *)dev->priv;
  348. struct ethoc_bd bd;
  349. u32 entry;
  350. u32 pending;
  351. int tmo;
  352. entry = priv->cur_tx % priv->num_tx;
  353. ethoc_read_bd(dev, entry, &bd);
  354. if (unlikely(length < ETHOC_ZLEN))
  355. bd.stat |= TX_BD_PAD;
  356. else
  357. bd.stat &= ~TX_BD_PAD;
  358. bd.addr = (u32)packet;
  359. flush_dcache_range(bd.addr, bd.addr + length);
  360. bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
  361. bd.stat |= TX_BD_LEN(length);
  362. ethoc_write_bd(dev, entry, &bd);
  363. /* start transmit */
  364. bd.stat |= TX_BD_READY;
  365. ethoc_write_bd(dev, entry, &bd);
  366. /* wait for transfer to succeed */
  367. tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
  368. while (1) {
  369. pending = ethoc_read(dev, INT_SOURCE);
  370. ethoc_ack_irq(dev, pending & ~INT_MASK_RX);
  371. if (pending & INT_MASK_BUSY)
  372. debug("%s(): packet dropped\n", __func__);
  373. if (pending & INT_MASK_TX) {
  374. ethoc_tx(dev);
  375. break;
  376. }
  377. if (get_timer(0) >= tmo) {
  378. debug("%s(): timed out\n", __func__);
  379. return -1;
  380. }
  381. }
  382. debug("%s(): packet sent\n", __func__);
  383. return 0;
  384. }
  385. static void ethoc_halt(struct eth_device *dev)
  386. {
  387. ethoc_disable_rx_and_tx(dev);
  388. }
  389. static int ethoc_recv(struct eth_device *dev)
  390. {
  391. u32 pending;
  392. pending = ethoc_read(dev, INT_SOURCE);
  393. ethoc_ack_irq(dev, pending);
  394. if (pending & INT_MASK_BUSY)
  395. debug("%s(): packet dropped\n", __func__);
  396. if (pending & INT_MASK_RX) {
  397. debug("%s(): rx irq\n", __func__);
  398. ethoc_rx(dev, PKTBUFSRX);
  399. }
  400. return 0;
  401. }
  402. int ethoc_initialize(u8 dev_num, int base_addr)
  403. {
  404. struct ethoc *priv;
  405. struct eth_device *dev;
  406. priv = malloc(sizeof(*priv));
  407. if (!priv)
  408. return 0;
  409. dev = malloc(sizeof(*dev));
  410. if (!dev) {
  411. free(priv);
  412. return 0;
  413. }
  414. memset(dev, 0, sizeof(*dev));
  415. dev->priv = priv;
  416. dev->iobase = base_addr;
  417. dev->init = ethoc_init;
  418. dev->halt = ethoc_halt;
  419. dev->send = ethoc_send;
  420. dev->recv = ethoc_recv;
  421. dev->write_hwaddr = ethoc_set_mac_address;
  422. sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
  423. eth_register(dev);
  424. return 1;
  425. }