init.S 8.3 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. #include <config.h>
  5. #include <asm/ppc4xx.h>
  6. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  7. #include <ppc_asm.tmpl>
  8. #include <ppc_defs.h>
  9. #include <asm/cache.h>
  10. #include <asm/mmu.h>
  11. /******************************************************************************
  12. * Function: ext_bus_cntlr_init
  13. *
  14. * Description: Configures EBC Controller and a few basic chip selects.
  15. *
  16. * CS0 is setup to get the Boot Flash out of the addresss range
  17. * so that we may setup a stack. CS7 is setup so that we can
  18. * access and reset the hardware watchdog.
  19. *
  20. * IMPORTANT: For pass1 this code must run from
  21. * cache since you can not reliably change a peripheral banks
  22. * timing register (pbxap) while running code from that bank.
  23. * For ex., since we are running from ROM on bank 0, we can NOT
  24. * execute the code that modifies bank 0 timings from ROM, so
  25. * we run it from cache.
  26. *
  27. * Notes: Does NOT use the stack.
  28. *****************************************************************************/
  29. .section ".text"
  30. .align 2
  31. .globl ext_bus_cntlr_init
  32. .type ext_bus_cntlr_init, @function
  33. ext_bus_cntlr_init:
  34. mflr r0
  35. /********************************************************************
  36. * Prefetch entire ext_bus_cntrl_init function into the icache.
  37. * This is necessary because we are going to change the same CS we
  38. * are executing from. Otherwise a CPU lockup may occur.
  39. *******************************************************************/
  40. bl ..getAddr
  41. ..getAddr:
  42. mflr r3 /* get address of ..getAddr */
  43. /* Calculate number of cache lines for this function */
  44. addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
  45. mtctr r4
  46. ..ebcloop:
  47. icbt r0, r3 /* prefetch cache line for addr in r3*/
  48. addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
  49. bdnz ..ebcloop /* continue for $CTR cache lines */
  50. /********************************************************************
  51. * Delay to ensure all accesses to ROM are complete before changing
  52. * bank 0 timings. 200usec should be enough.
  53. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
  54. *******************************************************************/
  55. addis r3, 0, 0x0
  56. ori r3, r3, 0xA000 /* wait 200us from reset */
  57. mtctr r3
  58. ..spinlp:
  59. bdnz ..spinlp /* spin loop */
  60. /********************************************************************
  61. * Setup External Bus Controller (EBC).
  62. *******************************************************************/
  63. addi r3, 0, EBC0_CFG
  64. mtdcr EBC0_CFGADDR, r3
  65. addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
  66. ori r4, r4, 0x0 /* Drive CS with external master */
  67. mtdcr EBC0_CFGDATA, r4
  68. /********************************************************************
  69. * Change PCIINT signal to PerWE
  70. *******************************************************************/
  71. mfdcr r4, CPC0_CR1
  72. ori r4, r4, 0x4000
  73. mtdcr CPC0_CR1, r4
  74. /********************************************************************
  75. * Memory Bank 0 (Flash Bank 0) initialization
  76. *******************************************************************/
  77. addi r3, 0, PB1AP
  78. mtdcr EBC0_CFGADDR, r3
  79. addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
  80. ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
  81. mtdcr EBC0_CFGDATA, r4
  82. addi r3, 0, PB0CR
  83. mtdcr EBC0_CFGADDR, r3
  84. addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
  85. ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
  86. mtdcr EBC0_CFGDATA, r4
  87. /********************************************************************
  88. * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
  89. *******************************************************************/
  90. addi r3, 0, PB7AP
  91. mtdcr EBC0_CFGADDR, r3
  92. addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
  93. ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
  94. mtdcr EBC0_CFGDATA, r4
  95. addi r3, 0, PB7CR
  96. mtdcr EBC0_CFGADDR, r3
  97. addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
  98. ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
  99. mtdcr EBC0_CFGDATA, r4
  100. /* We are all done */
  101. mtlr r0 /* Restore link register */
  102. blr /* Return to calling function */
  103. .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
  104. /* end ext_bus_cntlr_init() */
  105. /******************************************************************************
  106. * Function: sdram_init
  107. *
  108. * Description: Configures SDRAM memory banks.
  109. *
  110. * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
  111. * via the IIC bus and then configures the SDRAM memory
  112. * banks appropriately. If Auto Memory Configuration is
  113. * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
  114. * SDRAM is soldered down.
  115. *
  116. * Notes: Expects that the stack is already setup.
  117. *****************************************************************************/
  118. .section ".text"
  119. .align 2
  120. .globl sdram_init
  121. .type sdram_init, @function
  122. sdram_init:
  123. /* save the return info on stack */
  124. mflr r0 /* Get link register */
  125. stwu r1, -8(r1) /* Save back chain and move SP */
  126. stw r0, +12(r1) /* Save link register */
  127. /*
  128. * First call spd_sdram to try to init SDRAM according to the
  129. * contents of the SPD EEPROM. If the SPD EEPROM is blank or
  130. * erronious, spd_sdram returns 0 in R3.
  131. */
  132. li r3,0
  133. bl spd_sdram
  134. addic. r3, r3, 0 /* Check for error, save dram size */
  135. bne ..sdri_done /* If it worked, we're done... */
  136. /********************************************************************
  137. * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
  138. * is the SMALLEST SDRAM size the 405 supports. We can do this
  139. * because W7O boards have soldered on RAM, and there will always
  140. * be some amount present. If we were using DIMMs, we should hang
  141. * the board instead, since it doesn't have any RAM to continue
  142. * running with.
  143. *******************************************************************/
  144. /*
  145. * Disable memory controller to allow
  146. * values to be changed.
  147. */
  148. addi r3, 0, SDRAM0_CFG
  149. mtdcr SDRAM0_CFGADDR, r3
  150. addis r4, 0, 0x0
  151. ori r4, r4, 0x0
  152. mtdcr SDRAM0_CFGDATA, r4
  153. /*
  154. * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
  155. * All other banks are disabled.
  156. */
  157. addi r3, 0, SDRAM0_B0CR
  158. mtdcr SDRAM0_CFGADDR, r3
  159. addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
  160. ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
  161. mtdcr SDRAM0_CFGDATA, r4
  162. /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
  163. addi r4, 0, 0 /* Zero the data reg */
  164. addi r3, r3, 4 /* Point to MB1CF reg */
  165. mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
  166. mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
  167. addi r3, r3, 4 /* Point to MB2CF reg */
  168. mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
  169. mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
  170. addi r3, r3, 4 /* Point to MB3CF reg */
  171. mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
  172. mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
  173. /********************************************************************
  174. * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
  175. * To set the appropriate timings, we assume sdram is
  176. * 100MHz (pc100 compliant).
  177. *******************************************************************/
  178. /*
  179. * Set up SDTR1
  180. */
  181. addi r3, 0, SDRAM0_TR
  182. mtdcr SDRAM0_CFGADDR, r3
  183. addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
  184. ori r4, r4, 0x400D
  185. mtdcr SDRAM0_CFGDATA, r4
  186. /*
  187. * Set RTR
  188. */
  189. addi r3, 0, SDRAM0_RTR
  190. mtdcr SDRAM0_CFGADDR, r3
  191. addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
  192. mtdcr SDRAM0_CFGDATA, r4
  193. /********************************************************************
  194. * Delay to ensure 200usec have elapsed since reset. Assume worst
  195. * case that the core is running 200Mhz:
  196. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  197. *******************************************************************/
  198. addis r3, 0, 0x0000
  199. ori r3, r3, 0xA000 /* Wait 200us from reset */
  200. mtctr r3
  201. ..spinlp2:
  202. bdnz ..spinlp2 /* spin loop */
  203. /********************************************************************
  204. * Set memory controller options reg, MCOPT1.
  205. *******************************************************************/
  206. addi r3, 0, SDRAM0_CFG
  207. mtdcr SDRAM0_CFGADDR, r3
  208. addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
  209. ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
  210. mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
  211. ..sdri_done:
  212. /* restore and return */
  213. lwz r0, +12(r1) /* Get saved link register */
  214. addi r1, r1, +8 /* Remove frame from stack */
  215. mtlr r0 /* Restore link register */
  216. blr /* Return to calling function */
  217. .Lfe1: .size sdram_init,.Lfe1-sdram_init
  218. /* end sdram_init() */