init.S 6.0 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*-----------------------------------------------------------------------------
  5. * Function: ext_bus_cntlr_init
  6. * Description: Initializes the External Bus Controller for the external
  7. * peripherals. IMPORTANT: For pass1 this code must run from
  8. * cache since you can not reliably change a peripheral banks
  9. * timing register (pbxap) while running code from that bank.
  10. * For ex., since we are running from ROM on bank 0, we can NOT
  11. * execute the code that modifies bank 0 timings from ROM, so
  12. * we run it from cache.
  13. * Bank 0 - Flash or Multi Purpose Socket
  14. * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
  15. * Bank 2 - UART 1 (set in C-Code)
  16. * Bank 3 - UART 2 (set in C-Code)
  17. * Bank 4 - not used
  18. * Bank 5 - not used
  19. * Bank 6 - not used
  20. * Bank 7 - PLD Register
  21. *-----------------------------------------------------------------------------*/
  22. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  23. #include <configs/MIP405.h>
  24. #include <ppc_asm.tmpl>
  25. #include <ppc_defs.h>
  26. #include <asm/cache.h>
  27. #include <asm/mmu.h>
  28. #include <asm/ppc4xx.h>
  29. #include "mip405.h"
  30. .globl ext_bus_cntlr_init
  31. ext_bus_cntlr_init:
  32. mflr r4 /* save link register */
  33. mfdcr r3,CPC0_PSR /* get strapping reg */
  34. andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
  35. bnelr /* jump back if PCI boot */
  36. bl ..getAddr
  37. ..getAddr:
  38. mflr r3 /* get address of ..getAddr */
  39. mtlr r4 /* restore link register */
  40. addi r4,0,14 /* set ctr to 14; used to prefetch */
  41. mtctr r4 /* 14 cache lines to fit this function */
  42. /* in cache (gives us 8x14=112 instrctns) */
  43. ..ebcloop:
  44. icbt r0,r3 /* prefetch cache line for addr in r3 */
  45. addi r3,r3,32 /* move to next cache line */
  46. bdnz ..ebcloop /* continue for 14 cache lines */
  47. /*-------------------------------------------------------------------
  48. * Delay to ensure all accesses to ROM are complete before changing
  49. * bank 0 timings.
  50. *------------------------------------------------------------------- */
  51. addis r3,0,0x0
  52. ori r3,r3,0xA000
  53. mtctr r3
  54. ..spinlp:
  55. bdnz ..spinlp /* spin loop */
  56. /*-----------------------------------------------------------------------
  57. * decide boot up mode
  58. *----------------------------------------------------------------------- */
  59. addi r4,0,PB0CR
  60. mtdcr EBC0_CFGADDR,r4
  61. mfdcr r4,EBC0_CFGDATA
  62. andi. r0, r4, 0x2000 /* mask out irrelevant bits */
  63. beq 0f /* jump if 8 bit bus width */
  64. /* setup 16 bit things
  65. *-----------------------------------------------------------------------
  66. * Memory Bank 0 (16 Bit Flash) initialization
  67. *---------------------------------------------------------------------- */
  68. addi r4,0,PB1AP
  69. mtdcr EBC0_CFGADDR,r4
  70. addis r4,0,(FLASH_AP_B)@h
  71. ori r4,r4,(FLASH_AP_B)@l
  72. mtdcr EBC0_CFGDATA,r4
  73. addi r4,0,PB0CR
  74. mtdcr EBC0_CFGADDR,r4
  75. /* BS=0x010(4MB),BU=0x3(R/W), */
  76. addis r4,0,(FLASH_CR_B)@h
  77. ori r4,r4,(FLASH_CR_B)@l
  78. mtdcr EBC0_CFGDATA,r4
  79. b 1f
  80. 0:
  81. /* 8Bit boot mode: */
  82. /*-----------------------------------------------------------------------
  83. * Memory Bank 0 Multi Purpose Socket initialization
  84. *----------------------------------------------------------------------- */
  85. /* 0x7F8FFE80 slowest boot */
  86. addi r4,0,PB1AP
  87. mtdcr EBC0_CFGADDR,r4
  88. addis r4,0,(MPS_AP_B)@h
  89. ori r4,r4,(MPS_AP_B)@l
  90. mtdcr EBC0_CFGDATA,r4
  91. addi r4,0,PB0CR
  92. mtdcr EBC0_CFGADDR,r4
  93. /* BS=0x010(4MB),BU=0x3(R/W), */
  94. addis r4,0,(MPS_CR_B)@h
  95. ori r4,r4,(MPS_CR_B)@l
  96. mtdcr EBC0_CFGDATA,r4
  97. 1:
  98. /*-----------------------------------------------------------------------
  99. * Memory Bank 2-3-4-5-6 (not used) initialization
  100. *-----------------------------------------------------------------------*/
  101. addi r4,0,PB1CR
  102. mtdcr EBC0_CFGADDR,r4
  103. addis r4,0,0x0000
  104. ori r4,r4,0x0000
  105. mtdcr EBC0_CFGDATA,r4
  106. addi r4,0,PB2CR
  107. mtdcr EBC0_CFGADDR,r4
  108. addis r4,0,0x0000
  109. ori r4,r4,0x0000
  110. mtdcr EBC0_CFGDATA,r4
  111. addi r4,0,PB3CR
  112. mtdcr EBC0_CFGADDR,r4
  113. addis r4,0,0x0000
  114. ori r4,r4,0x0000
  115. mtdcr EBC0_CFGDATA,r4
  116. addi r4,0,PB4CR
  117. mtdcr EBC0_CFGADDR,r4
  118. addis r4,0,0x0000
  119. ori r4,r4,0x0000
  120. mtdcr EBC0_CFGDATA,r4
  121. addi r4,0,PB5CR
  122. mtdcr EBC0_CFGADDR,r4
  123. addis r4,0,0x0000
  124. ori r4,r4,0x0000
  125. mtdcr EBC0_CFGDATA,r4
  126. addi r4,0,PB6CR
  127. mtdcr EBC0_CFGADDR,r4
  128. addis r4,0,0x0000
  129. ori r4,r4,0x0000
  130. mtdcr EBC0_CFGDATA,r4
  131. addi r4,0,PB7CR
  132. mtdcr EBC0_CFGADDR,r4
  133. addis r4,0,0x0000
  134. ori r4,r4,0x0000
  135. mtdcr EBC0_CFGDATA,r4
  136. nop /* pass2 DCR errata #8 */
  137. blr
  138. #if defined(CONFIG_BOOT_PCI)
  139. .section .bootpg,"ax"
  140. .globl _start_pci
  141. /*******************************************
  142. */
  143. _start_pci:
  144. /* first handle errata #68 / PCI_18 */
  145. iccci r0, r0 /* invalidate I-cache */
  146. lis r31, 0
  147. mticcr r31 /* ICCR = 0 (all uncachable) */
  148. isync
  149. mfccr0 r28 /* set CCR0[24] = 1 */
  150. ori r28, r28, 0x0080
  151. mtccr0 r28
  152. /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
  153. lis r28, 0xEF40
  154. addi r28, r28, 0x0004
  155. stw r31, 0x0C(r28) /* clear PMM0PCIHA */
  156. lis r29, 0xFFF8 /* open 512 kByte */
  157. addi r29, r29, 0x0001/* and enable this region */
  158. stwbrx r29, r0, r28 /* write PMM0MA */
  159. lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
  160. addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
  161. lis r31, 0x8000 /* set en bit bus 0 */
  162. ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
  163. stwbrx r31, r0, r28 /* write it */
  164. lwbrx r31, r0, r29 /* load XBCS register */
  165. oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
  166. stwbrx r31, r0, r29 /* write back XBCS register */
  167. nop
  168. nop
  169. b _start /* normal start */
  170. #endif