miiphy.c 8.5 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 ibm-pibs
  3. */
  4. /*-----------------------------------------------------------------------------+
  5. |
  6. | File Name: miiphy.c
  7. |
  8. | Function: This module has utilities for accessing the MII PHY through
  9. | the EMAC3 macro.
  10. |
  11. | Author: Mark Wisner
  12. |
  13. +-----------------------------------------------------------------------------*/
  14. /* define DEBUG for debugging output (obviously ;-)) */
  15. #if 0
  16. #define DEBUG
  17. #endif
  18. #include <common.h>
  19. #include <asm/processor.h>
  20. #include <asm/io.h>
  21. #include <ppc_asm.tmpl>
  22. #include <commproc.h>
  23. #include <asm/ppc4xx-emac.h>
  24. #include <asm/ppc4xx-mal.h>
  25. #include <miiphy.h>
  26. #if !defined(CONFIG_PHY_CLK_FREQ)
  27. #define CONFIG_PHY_CLK_FREQ 0
  28. #endif
  29. /***********************************************************/
  30. /* Dump out to the screen PHY regs */
  31. /***********************************************************/
  32. void miiphy_dump (char *devname, unsigned char addr)
  33. {
  34. unsigned long i;
  35. unsigned short data;
  36. for (i = 0; i < 0x1A; i++) {
  37. if (miiphy_read (devname, addr, i, &data)) {
  38. printf ("read error for reg %lx\n", i);
  39. return;
  40. }
  41. printf ("Phy reg %lx ==> %4x\n", i, data);
  42. /* jump to the next set of regs */
  43. if (i == 0x07)
  44. i = 0x0f;
  45. } /* end for loop */
  46. } /* end dump */
  47. /***********************************************************/
  48. /* (Re)start autonegotiation */
  49. /***********************************************************/
  50. int phy_setup_aneg (char *devname, unsigned char addr)
  51. {
  52. u16 bmcr;
  53. #if defined(CONFIG_PHY_DYNAMIC_ANEG)
  54. /*
  55. * Set up advertisement based on capablilities reported by the PHY.
  56. * This should work for both copper and fiber.
  57. */
  58. u16 bmsr;
  59. #if defined(CONFIG_PHY_GIGE)
  60. u16 exsr = 0x0000;
  61. #endif
  62. miiphy_read (devname, addr, MII_BMSR, &bmsr);
  63. #if defined(CONFIG_PHY_GIGE)
  64. if (bmsr & BMSR_ESTATEN)
  65. miiphy_read (devname, addr, MII_ESTATUS, &exsr);
  66. if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) {
  67. /* 1000BASE-X */
  68. u16 anar = 0x0000;
  69. if (exsr & ESTATUS_1000XF)
  70. anar |= ADVERTISE_1000XFULL;
  71. if (exsr & ESTATUS_1000XH)
  72. anar |= ADVERTISE_1000XHALF;
  73. miiphy_write (devname, addr, MII_ADVERTISE, anar);
  74. } else
  75. #endif
  76. {
  77. u16 anar, btcr;
  78. miiphy_read (devname, addr, MII_ADVERTISE, &anar);
  79. anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL |
  80. LPA_100HALF | LPA_10FULL | LPA_10HALF);
  81. miiphy_read (devname, addr, MII_CTRL1000, &btcr);
  82. btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
  83. if (bmsr & BMSR_100BASE4)
  84. anar |= LPA_100BASE4;
  85. if (bmsr & BMSR_100FULL)
  86. anar |= LPA_100FULL;
  87. if (bmsr & BMSR_100HALF)
  88. anar |= LPA_100HALF;
  89. if (bmsr & BMSR_10FULL)
  90. anar |= LPA_10FULL;
  91. if (bmsr & BMSR_10HALF)
  92. anar |= LPA_10HALF;
  93. miiphy_write (devname, addr, MII_ADVERTISE, anar);
  94. #if defined(CONFIG_PHY_GIGE)
  95. if (exsr & ESTATUS_1000_TFULL)
  96. btcr |= PHY_1000BTCR_1000FD;
  97. if (exsr & ESTATUS_1000_THALF)
  98. btcr |= PHY_1000BTCR_1000HD;
  99. miiphy_write (devname, addr, MII_CTRL1000, btcr);
  100. #endif
  101. }
  102. #else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
  103. /*
  104. * Set up standard advertisement
  105. */
  106. u16 adv;
  107. miiphy_read (devname, addr, MII_ADVERTISE, &adv);
  108. adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF |
  109. LPA_10FULL | LPA_10HALF);
  110. miiphy_write (devname, addr, MII_ADVERTISE, adv);
  111. miiphy_read (devname, addr, MII_CTRL1000, &adv);
  112. adv |= (0x0300);
  113. miiphy_write (devname, addr, MII_CTRL1000, adv);
  114. #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
  115. /* Start/Restart aneg */
  116. miiphy_read (devname, addr, MII_BMCR, &bmcr);
  117. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  118. miiphy_write (devname, addr, MII_BMCR, bmcr);
  119. return 0;
  120. }
  121. /***********************************************************/
  122. /* read a phy reg and return the value with a rc */
  123. /***********************************************************/
  124. /* AMCC_TODO:
  125. * Find out of the choice for the emac for MDIO is from the bridges,
  126. * i.e. ZMII or RGMII as approporiate. If the bridges are not used
  127. * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL]
  128. * used? If so, then this routine below does not apply to the 460EX/GT.
  129. *
  130. * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
  131. * return EMAC0 offset here
  132. * vg: For 460EX/460GT if internal GPCS PHY address is specified
  133. * return appropriate EMAC offset
  134. */
  135. unsigned int miiphy_getemac_offset(u8 addr)
  136. {
  137. #if defined(CONFIG_440) && \
  138. !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
  139. !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
  140. unsigned long zmii;
  141. unsigned long eoffset;
  142. /* Need to find out which mdi port we're using */
  143. zmii = in_be32((void *)ZMII0_FER);
  144. if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
  145. /* using port 0 */
  146. eoffset = 0;
  147. else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1)))
  148. /* using port 1 */
  149. eoffset = 0x100;
  150. else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2)))
  151. /* using port 2 */
  152. eoffset = 0x400;
  153. else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3)))
  154. /* using port 3 */
  155. eoffset = 0x600;
  156. else {
  157. /* None of the mdi ports are enabled! */
  158. /* enable port 0 */
  159. zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
  160. out_be32((void *)ZMII0_FER, zmii);
  161. eoffset = 0;
  162. /* need to soft reset port 0 */
  163. zmii = in_be32((void *)EMAC0_MR0);
  164. zmii |= EMAC_MR0_SRST;
  165. out_be32((void *)EMAC0_MR0, zmii);
  166. }
  167. return (eoffset);
  168. #else
  169. #if defined(CONFIG_405EX)
  170. unsigned long rgmii;
  171. int devnum = 1;
  172. rgmii = in_be32((void *)RGMII_FER);
  173. if (rgmii & (1 << (19 - devnum)))
  174. return 0x100;
  175. #endif
  176. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  177. u32 eoffset = 0;
  178. switch (addr) {
  179. #if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
  180. case CONFIG_GPCS_PHY1_ADDR:
  181. if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100)))
  182. eoffset = 0x100;
  183. break;
  184. #endif
  185. #if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
  186. case CONFIG_GPCS_PHY2_ADDR:
  187. if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300)))
  188. eoffset = 0x300;
  189. break;
  190. #endif
  191. #if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
  192. case CONFIG_GPCS_PHY3_ADDR:
  193. if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400)))
  194. eoffset = 0x400;
  195. break;
  196. #endif
  197. default:
  198. eoffset = 0;
  199. break;
  200. }
  201. return eoffset;
  202. #endif
  203. return 0;
  204. #endif
  205. }
  206. static int emac_miiphy_wait(u32 emac_reg)
  207. {
  208. u32 sta_reg;
  209. int i;
  210. /* wait for completion */
  211. i = 0;
  212. do {
  213. sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
  214. if (i++ > 5) {
  215. debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__,
  216. __LINE__, sta_reg);
  217. return -1;
  218. }
  219. udelay(10);
  220. } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK);
  221. return 0;
  222. }
  223. static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
  224. {
  225. u32 emac_reg;
  226. u32 sta_reg;
  227. emac_reg = miiphy_getemac_offset(addr);
  228. /* wait for completion */
  229. if (emac_miiphy_wait(emac_reg) != 0)
  230. return -1;
  231. sta_reg = reg; /* reg address */
  232. /* set clock (50MHz) and read flags */
  233. #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
  234. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  235. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  236. defined(CONFIG_405EX)
  237. #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
  238. sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
  239. #else
  240. sta_reg |= cmd;
  241. #endif
  242. #else
  243. sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
  244. #endif
  245. /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
  246. sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
  247. sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */
  248. sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
  249. if (cmd == EMAC_STACR_WRITE)
  250. memcpy(&sta_reg, &value, 2); /* put in data */
  251. out_be32((void *)EMAC0_STACR + emac_reg, sta_reg);
  252. debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
  253. /* wait for completion */
  254. if (emac_miiphy_wait(emac_reg) != 0)
  255. return -1;
  256. debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
  257. if ((sta_reg & EMAC_STACR_PHYE) != 0)
  258. return -1;
  259. return 0;
  260. }
  261. int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char reg,
  262. unsigned short *value)
  263. {
  264. unsigned long sta_reg;
  265. unsigned long emac_reg;
  266. emac_reg = miiphy_getemac_offset(addr);
  267. if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
  268. return -1;
  269. sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
  270. *value = sta_reg >> 16;
  271. return 0;
  272. }
  273. /***********************************************************/
  274. /* write a phy reg and return the value with a rc */
  275. /***********************************************************/
  276. int emac4xx_miiphy_write (const char *devname, unsigned char addr, unsigned char reg,
  277. unsigned short value)
  278. {
  279. return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value);
  280. }