ls1012aqds.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2021 NXP
  5. */
  6. #ifndef __LS1012AQDS_H__
  7. #define __LS1012AQDS_H__
  8. #include "ls1012a_common.h"
  9. /* DDR */
  10. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  11. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  12. #define CONFIG_SYS_SDRAM_SIZE 0x40000000
  13. /*
  14. * QIXIS Definitions
  15. */
  16. #define CONFIG_FSL_QIXIS
  17. #ifdef CONFIG_FSL_QIXIS
  18. #define CONFIG_QIXIS_I2C_ACCESS
  19. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  20. #define QIXIS_LBMAP_BRDCFG_REG 0x04
  21. #define QIXIS_LBMAP_SWITCH 6
  22. #define QIXIS_LBMAP_MASK 0x08
  23. #define QIXIS_LBMAP_SHIFT 0
  24. #define QIXIS_LBMAP_DFLTBANK 0x00
  25. #define QIXIS_LBMAP_ALTBANK 0x08
  26. #define QIXIS_RST_CTL_RESET 0x31
  27. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  28. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  29. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  30. #endif
  31. /*
  32. * I2C bus multiplexer
  33. */
  34. #define I2C_MUX_PCA_ADDR_PRI 0x77
  35. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  36. #define I2C_RETIMER_ADDR 0x18
  37. #define I2C_MUX_CH_DEFAULT 0x8
  38. #define I2C_MUX_CH_CH7301 0xC
  39. #define I2C_MUX_CH5 0xD
  40. #define I2C_MUX_CH7 0xF
  41. #define I2C_MUX_CH_VOL_MONITOR 0xa
  42. /*
  43. * RTC configuration
  44. */
  45. #define RTC
  46. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  47. /* EEPROM */
  48. #define CONFIG_SYS_I2C_EEPROM_NXID
  49. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  50. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  51. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  52. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  53. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  54. /* Voltage monitor on channel 2*/
  55. #define I2C_VOL_MONITOR_ADDR 0x40
  56. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  57. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  58. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  59. /* DSPI */
  60. #define CONFIG_FSL_DSPI1
  61. #define MMAP_DSPI DSPI1_BASE_ADDR
  62. #define CONFIG_SYS_DSPI_CTAR0 1
  63. #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  64. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  65. DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  66. DSPI_CTAR_DT(0))
  67. #define CONFIG_SPI_FLASH_SST /* cs1 */
  68. #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  69. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  70. DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
  71. DSPI_CTAR_DT(0))
  72. #define CONFIG_SPI_FLASH_STMICRO /* cs2 */
  73. #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  74. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  75. DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  76. DSPI_CTAR_DT(0))
  77. #define CONFIG_SPI_FLASH_EON /* cs3 */
  78. #define CONFIG_PCIE1 /* PCIE controller 1 */
  79. #define CONFIG_PCI_SCAN_SHOW
  80. #undef CONFIG_EXTRA_ENV_SETTINGS
  81. #define CONFIG_EXTRA_ENV_SETTINGS \
  82. "verify=no\0" \
  83. "fdt_addr=0x00f00000\0" \
  84. "kernel_addr=0x01000000\0" \
  85. "kernelheader_addr=0x600000\0" \
  86. "scriptaddr=0x80000000\0" \
  87. "scripthdraddr=0x80080000\0" \
  88. "fdtheader_addr_r=0x80100000\0" \
  89. "kernelheader_addr_r=0x80200000\0" \
  90. "kernel_addr_r=0x96000000\0" \
  91. "fdt_addr_r=0x90000000\0" \
  92. "load_addr=0xa0000000\0" \
  93. "kernel_size=0x2800000\0" \
  94. "kernelheader_size=0x40000\0" \
  95. "console=ttyS0,115200\0" \
  96. BOOTENV \
  97. "boot_scripts=ls1012aqds_boot.scr\0" \
  98. "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \
  99. "scan_dev_for_boot_part=" \
  100. "part list ${devtype} ${devnum} devplist; " \
  101. "env exists devplist || setenv devplist 1; " \
  102. "for distro_bootpart in ${devplist}; do " \
  103. "if fstype ${devtype} " \
  104. "${devnum}:${distro_bootpart} " \
  105. "bootfstype; then " \
  106. "run scan_dev_for_boot; " \
  107. "fi; " \
  108. "done\0" \
  109. "boot_a_script=" \
  110. "load ${devtype} ${devnum}:${distro_bootpart} " \
  111. "${scriptaddr} ${prefix}${script}; " \
  112. "env exists secureboot && load ${devtype} " \
  113. "${devnum}:${distro_bootpart} " \
  114. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  115. "env exists secureboot " \
  116. "&& esbc_validate ${scripthdraddr};" \
  117. "source ${scriptaddr}\0" \
  118. "qspi_bootcmd=echo Trying load from qspi..;" \
  119. "sf probe 0:0 && sf read $load_addr " \
  120. "$kernel_addr $kernel_size; env exists secureboot " \
  121. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  122. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  123. "bootm $load_addr#$board\0"
  124. #undef CONFIG_BOOTCOMMAND
  125. #ifdef CONFIG_TFABOOT
  126. #undef QSPI_NOR_BOOTCOMMAND
  127. #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
  128. "env exists secureboot && esbc_halt;"
  129. #else
  130. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
  131. "env exists secureboot && esbc_halt;"
  132. #endif
  133. #include <asm/fsl_secure_boot.h>
  134. #endif /* __LS1012AQDS_H__ */