corenet_ds.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * Corenet DS style board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #include "../board/freescale/common/ics307_clk.h"
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #ifdef CONFIG_NXP_ESBC
  15. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  16. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  17. #ifdef CONFIG_MTD_RAW_NAND
  18. #define CONFIG_RAMBOOT_NAND
  19. #endif
  20. #define CONFIG_BOOTSCRIPT_COPY_RAM
  21. #else
  22. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  23. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  24. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  25. #if defined(CONFIG_TARGET_P3041DS)
  26. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  27. #elif defined(CONFIG_TARGET_P4080DS)
  28. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  29. #elif defined(CONFIG_TARGET_P5020DS)
  30. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  31. #elif defined(CONFIG_TARGET_P5040DS)
  32. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  33. #endif
  34. #endif
  35. #endif
  36. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  37. /* Set 1M boot space */
  38. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  39. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  40. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  41. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  42. #endif
  43. /* High Level Configuration Options */
  44. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  45. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  47. #endif
  48. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  49. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  50. #define CONFIG_PCIE1 /* PCIE controller 1 */
  51. #define CONFIG_PCIE2 /* PCIE controller 2 */
  52. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  53. #if defined(CONFIG_SPIFLASH)
  54. #elif defined(CONFIG_SDCARD)
  55. #define CONFIG_FSL_FIXED_MMC_LOCATION
  56. #endif
  57. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  58. /*
  59. * These can be toggled for performance analysis, otherwise use default.
  60. */
  61. #define CONFIG_SYS_CACHE_STASHING
  62. #define CONFIG_BACKSIDE_L2_CACHE
  63. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  64. #define CONFIG_BTB /* toggle branch predition */
  65. #define CONFIG_DDR_ECC
  66. #ifdef CONFIG_DDR_ECC
  67. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  68. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  69. #endif
  70. #define CONFIG_ENABLE_36BIT_PHYS
  71. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  72. /*
  73. * Config the L3 Cache as L3 SRAM
  74. */
  75. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  76. #ifdef CONFIG_PHYS_64BIT
  77. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  78. #else
  79. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  80. #endif
  81. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  82. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  83. #ifdef CONFIG_PHYS_64BIT
  84. #define CONFIG_SYS_DCSRBAR 0xf0000000
  85. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  86. #endif
  87. /* EEPROM */
  88. #define CONFIG_SYS_I2C_EEPROM_NXID
  89. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  90. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  91. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  92. /*
  93. * DDR Setup
  94. */
  95. #define CONFIG_VERY_BIG_RAM
  96. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  97. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  98. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  99. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  100. #define CONFIG_DDR_SPD
  101. #define CONFIG_SYS_SPD_BUS_NUM 1
  102. #define SPD_EEPROM_ADDRESS1 0x51
  103. #define SPD_EEPROM_ADDRESS2 0x52
  104. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  105. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  106. /*
  107. * Local Bus Definitions
  108. */
  109. /* Set the local bus clock 1/8 of platform clock */
  110. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  111. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
  112. #ifdef CONFIG_PHYS_64BIT
  113. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  114. #else
  115. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  116. #endif
  117. #define CONFIG_SYS_FLASH_BR_PRELIM \
  118. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
  119. | BR_PS_16 | BR_V)
  120. #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  121. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  122. #define CONFIG_SYS_BR1_PRELIM \
  123. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  124. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  125. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  126. #ifdef CONFIG_PHYS_64BIT
  127. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  128. #else
  129. #define PIXIS_BASE_PHYS PIXIS_BASE
  130. #endif
  131. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  132. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  133. #define PIXIS_LBMAP_SWITCH 7
  134. #define PIXIS_LBMAP_MASK 0xf0
  135. #define PIXIS_LBMAP_SHIFT 4
  136. #define PIXIS_LBMAP_ALTBANK 0x40
  137. #define CONFIG_SYS_FLASH_QUIET_TEST
  138. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  139. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  140. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  141. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  142. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  143. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  144. #if defined(CONFIG_RAMBOOT_PBL)
  145. #define CONFIG_SYS_RAMBOOT
  146. #endif
  147. /* Nand Flash */
  148. #ifdef CONFIG_NAND_FSL_ELBC
  149. #define CONFIG_SYS_NAND_BASE 0xffa00000
  150. #ifdef CONFIG_PHYS_64BIT
  151. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  152. #else
  153. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  154. #endif
  155. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  156. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  157. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  158. /* NAND flash config */
  159. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  160. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  161. | BR_PS_8 /* Port Size = 8 bit */ \
  162. | BR_MS_FCM /* MSEL = FCM */ \
  163. | BR_V) /* valid */
  164. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  165. | OR_FCM_PGS /* Large Page*/ \
  166. | OR_FCM_CSCT \
  167. | OR_FCM_CST \
  168. | OR_FCM_CHT \
  169. | OR_FCM_SCY_1 \
  170. | OR_FCM_TRLX \
  171. | OR_FCM_EHTR)
  172. #ifdef CONFIG_MTD_RAW_NAND
  173. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  174. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  175. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  176. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  177. #else
  178. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  179. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  180. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  181. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  182. #endif
  183. #else
  184. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  185. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  186. #endif /* CONFIG_NAND_FSL_ELBC */
  187. #define CONFIG_SYS_FLASH_EMPTY_INFO
  188. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  189. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  190. #define CONFIG_HWCONFIG
  191. /* define to use L1 as initial stack */
  192. #define CONFIG_L1_INIT_RAM
  193. #define CONFIG_SYS_INIT_RAM_LOCK
  194. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  195. #ifdef CONFIG_PHYS_64BIT
  196. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  197. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  198. /* The assembler doesn't like typecast */
  199. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  200. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  201. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  202. #else
  203. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  204. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  205. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  206. #endif
  207. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  208. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  209. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  210. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  211. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  212. /* Serial Port - controlled on board with jumper J8
  213. * open - index 2
  214. * shorted - index 1
  215. */
  216. #define CONFIG_SYS_NS16550_SERIAL
  217. #define CONFIG_SYS_NS16550_REG_SIZE 1
  218. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  219. #define CONFIG_SYS_BAUDRATE_TABLE \
  220. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  221. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  222. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  223. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  224. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  225. /* I2C */
  226. #if !CONFIG_IS_ENABLED(DM_I2C)
  227. #define CONFIG_SYS_I2C_LEGACY
  228. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  229. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  230. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  231. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  232. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  233. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  234. #else
  235. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  236. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  237. #endif
  238. #define CONFIG_SYS_I2C_FSL
  239. /*
  240. * RapidIO
  241. */
  242. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  243. #ifdef CONFIG_PHYS_64BIT
  244. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  245. #else
  246. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  247. #endif
  248. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  249. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  250. #ifdef CONFIG_PHYS_64BIT
  251. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  252. #else
  253. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  254. #endif
  255. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  256. /*
  257. * for slave u-boot IMAGE instored in master memory space,
  258. * PHYS must be aligned based on the SIZE
  259. */
  260. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  261. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  262. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  263. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  264. /*
  265. * for slave UCODE and ENV instored in master memory space,
  266. * PHYS must be aligned based on the SIZE
  267. */
  268. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  269. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  270. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  271. /* slave core release by master*/
  272. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  273. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  274. /*
  275. * SRIO_PCIE_BOOT - SLAVE
  276. */
  277. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  278. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  279. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  280. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  281. #endif
  282. /*
  283. * eSPI - Enhanced SPI
  284. */
  285. /*
  286. * General PCI
  287. * Memory space is mapped 1-1, but I/O space must start from 0.
  288. */
  289. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  290. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  291. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  292. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  293. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  294. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  295. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  296. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  297. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  298. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  299. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  300. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  301. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  302. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  303. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  304. /* controller 4, Base address 203000 */
  305. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  306. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  307. /* Qman/Bman */
  308. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  309. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  310. #ifdef CONFIG_PHYS_64BIT
  311. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  312. #else
  313. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  314. #endif
  315. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  316. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  317. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  318. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  319. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  320. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  321. CONFIG_SYS_BMAN_CENA_SIZE)
  322. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  323. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  324. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  325. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  326. #ifdef CONFIG_PHYS_64BIT
  327. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  328. #else
  329. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  330. #endif
  331. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  332. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  333. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  334. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  335. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  336. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  337. CONFIG_SYS_QMAN_CENA_SIZE)
  338. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  339. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  340. #define CONFIG_SYS_DPAA_FMAN
  341. #define CONFIG_SYS_DPAA_PME
  342. /* Default address of microcode for the Linux Fman driver */
  343. #if defined(CONFIG_SPIFLASH)
  344. /*
  345. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  346. * env, so we got 0x110000.
  347. */
  348. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  349. #elif defined(CONFIG_SDCARD)
  350. /*
  351. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  352. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  353. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  354. */
  355. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  356. #elif defined(CONFIG_MTD_RAW_NAND)
  357. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  358. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  359. /*
  360. * Slave has no ucode locally, it can fetch this from remote. When implementing
  361. * in two corenet boards, slave's ucode could be stored in master's memory
  362. * space, the address can be mapped from slave TLB->slave LAW->
  363. * slave SRIO or PCIE outbound window->master inbound window->
  364. * master LAW->the ucode address in master's memory space.
  365. */
  366. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  367. #else
  368. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  369. #endif
  370. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  371. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  372. #ifdef CONFIG_PCI
  373. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  374. #endif /* CONFIG_PCI */
  375. /* SATA */
  376. #ifdef CONFIG_FSL_SATA_V2
  377. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  378. #define CONFIG_SATA1
  379. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  380. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  381. #define CONFIG_SATA2
  382. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  383. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  384. #define CONFIG_LBA48
  385. #endif
  386. #ifdef CONFIG_FMAN_ENET
  387. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
  388. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
  389. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
  390. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
  391. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
  392. #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
  393. #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
  394. #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
  395. #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
  396. #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
  397. #define CONFIG_SYS_TBIPA_VALUE 8
  398. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  399. #endif
  400. /*
  401. * Environment
  402. */
  403. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  404. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  405. /*
  406. * USB
  407. */
  408. #define CONFIG_HAS_FSL_DR_USB
  409. #define CONFIG_HAS_FSL_MPH_USB
  410. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  411. #define CONFIG_USB_EHCI_FSL
  412. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  413. #endif
  414. #ifdef CONFIG_MMC
  415. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  416. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  417. #endif
  418. /*
  419. * Miscellaneous configurable options
  420. */
  421. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  422. /*
  423. * For booting Linux, the board info and command line data
  424. * have to be in the first 64 MB of memory, since this is
  425. * the maximum mapped by the Linux kernel during initialization.
  426. */
  427. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  428. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  429. #ifdef CONFIG_CMD_KGDB
  430. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  431. #endif
  432. /*
  433. * Environment Configuration
  434. */
  435. #define CONFIG_ROOTPATH "/opt/nfsroot"
  436. #define CONFIG_BOOTFILE "uImage"
  437. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  438. /* default location for tftp and bootm */
  439. #define CONFIG_LOADADDR 1000000
  440. #ifdef CONFIG_TARGET_P4080DS
  441. #define __USB_PHY_TYPE ulpi
  442. #else
  443. #define __USB_PHY_TYPE utmi
  444. #endif
  445. #define CONFIG_EXTRA_ENV_SETTINGS \
  446. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  447. "bank_intlv=cs0_cs1;" \
  448. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  449. "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  450. "netdev=eth0\0" \
  451. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  452. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  453. "tftpflash=tftpboot $loadaddr $uboot && " \
  454. "protect off $ubootaddr +$filesize && " \
  455. "erase $ubootaddr +$filesize && " \
  456. "cp.b $loadaddr $ubootaddr $filesize && " \
  457. "protect on $ubootaddr +$filesize && " \
  458. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  459. "consoledev=ttyS0\0" \
  460. "ramdiskaddr=2000000\0" \
  461. "ramdiskfile=p4080ds/ramdisk.uboot\0" \
  462. "fdtaddr=1e00000\0" \
  463. "fdtfile=p4080ds/p4080ds.dtb\0" \
  464. "bdev=sda3\0"
  465. #define CONFIG_HDBOOT \
  466. "setenv bootargs root=/dev/$bdev rw " \
  467. "console=$consoledev,$baudrate $othbootargs;" \
  468. "tftp $loadaddr $bootfile;" \
  469. "tftp $fdtaddr $fdtfile;" \
  470. "bootm $loadaddr - $fdtaddr"
  471. #define CONFIG_NFSBOOTCOMMAND \
  472. "setenv bootargs root=/dev/nfs rw " \
  473. "nfsroot=$serverip:$rootpath " \
  474. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  475. "console=$consoledev,$baudrate $othbootargs;" \
  476. "tftp $loadaddr $bootfile;" \
  477. "tftp $fdtaddr $fdtfile;" \
  478. "bootm $loadaddr - $fdtaddr"
  479. #define CONFIG_RAMBOOTCOMMAND \
  480. "setenv bootargs root=/dev/ram rw " \
  481. "console=$consoledev,$baudrate $othbootargs;" \
  482. "tftp $ramdiskaddr $ramdiskfile;" \
  483. "tftp $loadaddr $bootfile;" \
  484. "tftp $fdtaddr $fdtfile;" \
  485. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  486. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  487. #include <asm/fsl_secure_boot.h>
  488. #endif /* __CONFIG_H */