T208xQDS.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020-2021 NXP
  5. */
  6. /*
  7. * T2080/T2081 QDS board configuration file
  8. */
  9. #ifndef __T208xQDS_H
  10. #define __T208xQDS_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #if defined(CONFIG_ARCH_T2080)
  14. #define CONFIG_FSL_SATA_V2
  15. #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
  16. #define CONFIG_SRIO1 /* SRIO port 1 */
  17. #define CONFIG_SRIO2 /* SRIO port 2 */
  18. #endif
  19. /* High Level Configuration Options */
  20. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  21. #define CONFIG_ENABLE_36BIT_PHYS
  22. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  23. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  24. #ifdef CONFIG_RAMBOOT_PBL
  25. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  26. #define CONFIG_SPL_FLUSH_IMAGE
  27. #define CONFIG_SPL_PAD_TO 0x40000
  28. #define CONFIG_SPL_MAX_SIZE 0x28000
  29. #define RESET_VECTOR_OFFSET 0x27FFC
  30. #define BOOT_PAGE_OFFSET 0x27000
  31. #ifdef CONFIG_SPL_BUILD
  32. #define CONFIG_SPL_SKIP_RELOCATE
  33. #define CONFIG_SPL_COMMON_INIT_DDR
  34. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  35. #endif
  36. #ifdef CONFIG_MTD_RAW_NAND
  37. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  38. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  39. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  40. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  41. #if defined(CONFIG_ARCH_T2080)
  42. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  43. #endif
  44. #endif
  45. #ifdef CONFIG_SPIFLASH
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  47. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  48. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  49. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  50. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  51. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  52. #ifndef CONFIG_SPL_BUILD
  53. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54. #endif
  55. #if defined(CONFIG_ARCH_T2080)
  56. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  57. #endif
  58. #endif
  59. #ifdef CONFIG_SDCARD
  60. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  61. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  62. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  63. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  64. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  65. #ifndef CONFIG_SPL_BUILD
  66. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67. #endif
  68. #if defined(CONFIG_ARCH_T2080)
  69. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  70. #endif
  71. #endif
  72. #endif /* CONFIG_RAMBOOT_PBL */
  73. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  74. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  75. /* Set 1M boot space */
  76. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  77. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  78. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  79. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  80. #endif
  81. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  82. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  83. #endif
  84. /*
  85. * These can be toggled for performance analysis, otherwise use default.
  86. */
  87. #define CONFIG_SYS_CACHE_STASHING
  88. #define CONFIG_BTB /* toggle branch predition */
  89. #define CONFIG_DDR_ECC
  90. #ifdef CONFIG_DDR_ECC
  91. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  92. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  93. #endif
  94. #ifndef __ASSEMBLY__
  95. unsigned long get_board_sys_clk(void);
  96. unsigned long get_board_ddr_clk(void);
  97. #endif
  98. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  99. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  100. /*
  101. * Config the L3 Cache as L3 SRAM
  102. */
  103. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  104. #define CONFIG_SYS_L3_SIZE (512 << 10)
  105. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  106. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  107. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  108. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  109. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  110. #define CONFIG_SYS_DCSRBAR 0xf0000000
  111. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  112. /* EEPROM */
  113. #define CONFIG_SYS_I2C_EEPROM_NXID
  114. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  115. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  116. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  117. /*
  118. * DDR Setup
  119. */
  120. #define CONFIG_VERY_BIG_RAM
  121. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  122. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  123. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  124. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  125. #define CONFIG_DDR_SPD
  126. #define CONFIG_SYS_SPD_BUS_NUM 0
  127. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  128. #define SPD_EEPROM_ADDRESS1 0x51
  129. #define SPD_EEPROM_ADDRESS2 0x52
  130. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  131. #define CTRL_INTLV_PREFERED cacheline
  132. /*
  133. * IFC Definitions
  134. */
  135. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  136. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  137. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  138. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  139. + 0x8000000) | \
  140. CSPR_PORT_SIZE_16 | \
  141. CSPR_MSEL_NOR | \
  142. CSPR_V)
  143. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  144. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  145. CSPR_PORT_SIZE_16 | \
  146. CSPR_MSEL_NOR | \
  147. CSPR_V)
  148. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  149. /* NOR Flash Timing Params */
  150. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  151. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  152. FTIM0_NOR_TEADC(0x5) | \
  153. FTIM0_NOR_TEAHC(0x5))
  154. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  155. FTIM1_NOR_TRAD_NOR(0x1A) |\
  156. FTIM1_NOR_TSEQRAD_NOR(0x13))
  157. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  158. FTIM2_NOR_TCH(0x4) | \
  159. FTIM2_NOR_TWPH(0x0E) | \
  160. FTIM2_NOR_TWP(0x1c))
  161. #define CONFIG_SYS_NOR_FTIM3 0x0
  162. #define CONFIG_SYS_FLASH_QUIET_TEST
  163. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  164. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  165. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  166. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  167. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  168. #define CONFIG_SYS_FLASH_EMPTY_INFO
  169. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  170. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  171. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  172. #define QIXIS_BASE 0xffdf0000
  173. #define QIXIS_LBMAP_SWITCH 6
  174. #define QIXIS_LBMAP_MASK 0x0f
  175. #define QIXIS_LBMAP_SHIFT 0
  176. #define QIXIS_LBMAP_DFLTBANK 0x00
  177. #define QIXIS_LBMAP_ALTBANK 0x04
  178. #define QIXIS_LBMAP_NAND 0x09
  179. #define QIXIS_LBMAP_SD 0x00
  180. #define QIXIS_RCW_SRC_NAND 0x104
  181. #define QIXIS_RCW_SRC_SD 0x040
  182. #define QIXIS_RST_CTL_RESET 0x83
  183. #define QIXIS_RST_FORCE_MEM 0x1
  184. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  185. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  186. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  187. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  188. #define CONFIG_SYS_CSPR3_EXT (0xf)
  189. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  190. | CSPR_PORT_SIZE_8 \
  191. | CSPR_MSEL_GPCM \
  192. | CSPR_V)
  193. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  194. #define CONFIG_SYS_CSOR3 0x0
  195. /* QIXIS Timing parameters for IFC CS3 */
  196. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  197. FTIM0_GPCM_TEADC(0x0e) | \
  198. FTIM0_GPCM_TEAHC(0x0e))
  199. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  200. FTIM1_GPCM_TRAD(0x3f))
  201. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  202. FTIM2_GPCM_TCH(0x8) | \
  203. FTIM2_GPCM_TWP(0x1f))
  204. #define CONFIG_SYS_CS3_FTIM3 0x0
  205. /* NAND Flash on IFC */
  206. #define CONFIG_NAND_FSL_IFC
  207. #define CONFIG_SYS_NAND_BASE 0xff800000
  208. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  209. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  210. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  211. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  212. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  213. | CSPR_V)
  214. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  215. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  216. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  217. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  218. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  219. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  220. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  221. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  222. #define CONFIG_SYS_NAND_ONFI_DETECTION
  223. /* ONFI NAND Flash mode0 Timing Params */
  224. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  225. FTIM0_NAND_TWP(0x18) | \
  226. FTIM0_NAND_TWCHT(0x07) | \
  227. FTIM0_NAND_TWH(0x0a))
  228. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  229. FTIM1_NAND_TWBE(0x39) | \
  230. FTIM1_NAND_TRR(0x0e) | \
  231. FTIM1_NAND_TRP(0x18))
  232. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  233. FTIM2_NAND_TREH(0x0a) | \
  234. FTIM2_NAND_TWHRE(0x1e))
  235. #define CONFIG_SYS_NAND_FTIM3 0x0
  236. #define CONFIG_SYS_NAND_DDR_LAW 11
  237. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  238. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  239. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  240. #if defined(CONFIG_MTD_RAW_NAND)
  241. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  242. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  243. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  244. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  245. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  246. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  247. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  248. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  249. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  250. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  251. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  252. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  253. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  254. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  255. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  256. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  257. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  258. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  259. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  260. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  261. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  262. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  263. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  264. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  265. #else
  266. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  267. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  268. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  269. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  270. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  271. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  272. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  273. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  274. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  275. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  276. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  277. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  278. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  279. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  280. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  281. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  282. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  283. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  284. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  285. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  286. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  287. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  288. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  289. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  290. #endif
  291. #if defined(CONFIG_RAMBOOT_PBL)
  292. #define CONFIG_SYS_RAMBOOT
  293. #endif
  294. #ifdef CONFIG_SPL_BUILD
  295. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  296. #else
  297. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  298. #endif
  299. #define CONFIG_HWCONFIG
  300. /* define to use L1 as initial stack */
  301. #define CONFIG_L1_INIT_RAM
  302. #define CONFIG_SYS_INIT_RAM_LOCK
  303. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  304. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  305. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  306. /* The assembler doesn't like typecast */
  307. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  308. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  309. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  310. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  311. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  312. GENERATED_GBL_DATA_SIZE)
  313. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  314. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  315. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  316. /*
  317. * Serial Port
  318. */
  319. #define CONFIG_SYS_NS16550_SERIAL
  320. #define CONFIG_SYS_NS16550_REG_SIZE 1
  321. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  322. #define CONFIG_SYS_BAUDRATE_TABLE \
  323. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  324. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  325. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  326. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  327. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  328. /*
  329. * I2C
  330. */
  331. #if !CONFIG_IS_ENABLED(DM_I2C)
  332. #define CONFIG_SYS_I2C_LEGACY
  333. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  334. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  335. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  336. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  337. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  338. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  339. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  340. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  341. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  342. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  343. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  344. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  345. #endif
  346. #define CONFIG_SYS_I2C_FSL
  347. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  348. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  349. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  350. #define I2C_MUX_CH_DEFAULT 0x8
  351. #define I2C_MUX_CH_VOL_MONITOR 0xa
  352. /* Voltage monitor on channel 2*/
  353. #define I2C_VOL_MONITOR_ADDR 0x40
  354. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  355. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  356. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  357. #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
  358. #ifndef CONFIG_SPL_BUILD
  359. #define CONFIG_VID
  360. #endif
  361. #define CONFIG_VOL_MONITOR_IR36021_SET
  362. #define CONFIG_VOL_MONITOR_IR36021_READ
  363. /* The lowest and highest voltage allowed for T208xQDS */
  364. #define VDD_MV_MIN 819
  365. #define VDD_MV_MAX 1212
  366. /*
  367. * RapidIO
  368. */
  369. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  370. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  371. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  372. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  373. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  374. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  375. /*
  376. * for slave u-boot IMAGE instored in master memory space,
  377. * PHYS must be aligned based on the SIZE
  378. */
  379. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  380. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  381. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  382. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  383. /*
  384. * for slave UCODE and ENV instored in master memory space,
  385. * PHYS must be aligned based on the SIZE
  386. */
  387. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  388. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  389. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  390. /* slave core release by master*/
  391. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  392. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  393. /*
  394. * SRIO_PCIE_BOOT - SLAVE
  395. */
  396. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  397. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  398. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  399. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  400. #endif
  401. /*
  402. * eSPI - Enhanced SPI
  403. */
  404. /*
  405. * General PCI
  406. * Memory space is mapped 1-1, but I/O space must start from 0.
  407. */
  408. #define CONFIG_PCIE1 /* PCIE controller 1 */
  409. #define CONFIG_PCIE2 /* PCIE controller 2 */
  410. #define CONFIG_PCIE3 /* PCIE controller 3 */
  411. #define CONFIG_PCIE4 /* PCIE controller 4 */
  412. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  413. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  414. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  415. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  416. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  417. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  418. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  419. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  420. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  421. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  422. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  423. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  424. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  425. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  426. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  427. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  428. /* controller 4, Base address 203000 */
  429. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  430. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  431. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  432. #ifdef CONFIG_PCI
  433. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  434. #endif
  435. /* Qman/Bman */
  436. #ifndef CONFIG_NOBQFMAN
  437. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  438. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  439. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  440. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  441. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  442. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  443. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  444. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  445. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  446. CONFIG_SYS_BMAN_CENA_SIZE)
  447. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  448. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  449. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  450. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  451. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  452. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  453. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  454. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  455. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  456. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  457. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  458. CONFIG_SYS_QMAN_CENA_SIZE)
  459. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  460. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  461. #define CONFIG_SYS_DPAA_FMAN
  462. #define CONFIG_SYS_DPAA_PME
  463. #define CONFIG_SYS_PMAN
  464. #define CONFIG_SYS_DPAA_DCE
  465. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  466. #define CONFIG_SYS_INTERLAKEN
  467. /* Default address of microcode for the Linux Fman driver */
  468. #if defined(CONFIG_SPIFLASH)
  469. /*
  470. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  471. * env, so we got 0x110000.
  472. */
  473. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  474. #elif defined(CONFIG_SDCARD)
  475. /*
  476. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  477. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  478. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  479. */
  480. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  481. #elif defined(CONFIG_MTD_RAW_NAND)
  482. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  483. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  484. /*
  485. * Slave has no ucode locally, it can fetch this from remote. When implementing
  486. * in two corenet boards, slave's ucode could be stored in master's memory
  487. * space, the address can be mapped from slave TLB->slave LAW->
  488. * slave SRIO or PCIE outbound window->master inbound window->
  489. * master LAW->the ucode address in master's memory space.
  490. */
  491. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  492. #else
  493. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  494. #endif
  495. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  496. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  497. #endif /* CONFIG_NOBQFMAN */
  498. #ifdef CONFIG_SYS_DPAA_FMAN
  499. #define RGMII_PHY1_ADDR 0x1
  500. #define RGMII_PHY2_ADDR 0x2
  501. #define FM1_10GEC1_PHY_ADDR 0x3
  502. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  503. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  504. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  505. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  506. #endif
  507. #ifdef CONFIG_FMAN_ENET
  508. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  509. #endif
  510. /*
  511. * SATA
  512. */
  513. #ifdef CONFIG_FSL_SATA_V2
  514. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  515. #define CONFIG_SATA1
  516. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  517. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  518. #define CONFIG_SATA2
  519. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  520. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  521. #define CONFIG_LBA48
  522. #endif
  523. /*
  524. * USB
  525. */
  526. #ifdef CONFIG_USB_EHCI_HCD
  527. #define CONFIG_USB_EHCI_FSL
  528. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  529. #define CONFIG_HAS_FSL_DR_USB
  530. #endif
  531. /*
  532. * SDHC
  533. */
  534. #ifdef CONFIG_MMC
  535. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  536. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  537. #endif
  538. /*
  539. * Dynamic MTD Partition support with mtdparts
  540. */
  541. /*
  542. * Environment
  543. */
  544. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  545. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  546. /*
  547. * Miscellaneous configurable options
  548. */
  549. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  550. /*
  551. * For booting Linux, the board info and command line data
  552. * have to be in the first 64 MB of memory, since this is
  553. * the maximum mapped by the Linux kernel during initialization.
  554. */
  555. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  556. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  557. #ifdef CONFIG_CMD_KGDB
  558. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  559. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  560. #endif
  561. /*
  562. * Environment Configuration
  563. */
  564. #define CONFIG_ROOTPATH "/opt/nfsroot"
  565. #define CONFIG_BOOTFILE "uImage"
  566. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  567. /* default location for tftp and bootm */
  568. #define CONFIG_LOADADDR 1000000
  569. #define __USB_PHY_TYPE utmi
  570. #define CONFIG_EXTRA_ENV_SETTINGS \
  571. "hwconfig=fsl_ddr:" \
  572. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  573. "bank_intlv=auto;" \
  574. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  575. "netdev=eth0\0" \
  576. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  577. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  578. "tftpflash=tftpboot $loadaddr $uboot && " \
  579. "protect off $ubootaddr +$filesize && " \
  580. "erase $ubootaddr +$filesize && " \
  581. "cp.b $loadaddr $ubootaddr $filesize && " \
  582. "protect on $ubootaddr +$filesize && " \
  583. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  584. "consoledev=ttyS0\0" \
  585. "ramdiskaddr=2000000\0" \
  586. "ramdiskfile=t2080qds/ramdisk.uboot\0" \
  587. "fdtaddr=1e00000\0" \
  588. "fdtfile=t2080qds/t2080qds.dtb\0" \
  589. "bdev=sda3\0"
  590. /*
  591. * For emulation this causes u-boot to jump to the start of the
  592. * proof point app code automatically
  593. */
  594. #define CONFIG_PROOF_POINTS \
  595. "setenv bootargs root=/dev/$bdev rw " \
  596. "console=$consoledev,$baudrate $othbootargs;" \
  597. "cpu 1 release 0x29000000 - - -;" \
  598. "cpu 2 release 0x29000000 - - -;" \
  599. "cpu 3 release 0x29000000 - - -;" \
  600. "cpu 4 release 0x29000000 - - -;" \
  601. "cpu 5 release 0x29000000 - - -;" \
  602. "cpu 6 release 0x29000000 - - -;" \
  603. "cpu 7 release 0x29000000 - - -;" \
  604. "go 0x29000000"
  605. #define CONFIG_HVBOOT \
  606. "setenv bootargs config-addr=0x60000000; " \
  607. "bootm 0x01000000 - 0x00f00000"
  608. #define CONFIG_ALU \
  609. "setenv bootargs root=/dev/$bdev rw " \
  610. "console=$consoledev,$baudrate $othbootargs;" \
  611. "cpu 1 release 0x01000000 - - -;" \
  612. "cpu 2 release 0x01000000 - - -;" \
  613. "cpu 3 release 0x01000000 - - -;" \
  614. "cpu 4 release 0x01000000 - - -;" \
  615. "cpu 5 release 0x01000000 - - -;" \
  616. "cpu 6 release 0x01000000 - - -;" \
  617. "cpu 7 release 0x01000000 - - -;" \
  618. "go 0x01000000"
  619. #define CONFIG_LINUX \
  620. "setenv bootargs root=/dev/ram rw " \
  621. "console=$consoledev,$baudrate $othbootargs;" \
  622. "setenv ramdiskaddr 0x02000000;" \
  623. "setenv fdtaddr 0x00c00000;" \
  624. "setenv loadaddr 0x1000000;" \
  625. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  626. #define CONFIG_HDBOOT \
  627. "setenv bootargs root=/dev/$bdev rw " \
  628. "console=$consoledev,$baudrate $othbootargs;" \
  629. "tftp $loadaddr $bootfile;" \
  630. "tftp $fdtaddr $fdtfile;" \
  631. "bootm $loadaddr - $fdtaddr"
  632. #define CONFIG_NFSBOOTCOMMAND \
  633. "setenv bootargs root=/dev/nfs rw " \
  634. "nfsroot=$serverip:$rootpath " \
  635. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  636. "console=$consoledev,$baudrate $othbootargs;" \
  637. "tftp $loadaddr $bootfile;" \
  638. "tftp $fdtaddr $fdtfile;" \
  639. "bootm $loadaddr - $fdtaddr"
  640. #define CONFIG_RAMBOOTCOMMAND \
  641. "setenv bootargs root=/dev/ram rw " \
  642. "console=$consoledev,$baudrate $othbootargs;" \
  643. "tftp $ramdiskaddr $ramdiskfile;" \
  644. "tftp $loadaddr $bootfile;" \
  645. "tftp $fdtaddr $fdtfile;" \
  646. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  647. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  648. #include <asm/fsl_secure_boot.h>
  649. #endif /* __T208xQDS_H */