Kconfig 24 KB

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  1. menu "mpc85xx CPU"
  2. depends on MPC85xx
  3. config SYS_CPU
  4. default "mpc85xx"
  5. config CMD_ERRATA
  6. bool "Enable the 'errata' command"
  7. depends on MPC85xx
  8. default y
  9. help
  10. This enables the 'errata' command which displays a list of errata
  11. work-arounds which are enabled for the current board.
  12. choice
  13. prompt "Target select"
  14. optional
  15. config TARGET_SOCRATES
  16. bool "Support socrates"
  17. select ARCH_MPC8544
  18. config TARGET_P3041DS
  19. bool "Support P3041DS"
  20. select PHYS_64BIT
  21. select ARCH_P3041
  22. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  23. imply CMD_SATA
  24. imply PANIC_HANG
  25. config TARGET_P4080DS
  26. bool "Support P4080DS"
  27. select PHYS_64BIT
  28. select ARCH_P4080
  29. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  30. imply CMD_SATA
  31. imply PANIC_HANG
  32. config TARGET_P5040DS
  33. bool "Support P5040DS"
  34. select PHYS_64BIT
  35. select ARCH_P5040
  36. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  37. imply CMD_SATA
  38. imply PANIC_HANG
  39. config TARGET_MPC8548CDS
  40. bool "Support MPC8548CDS"
  41. select ARCH_MPC8548
  42. select FSL_VIA
  43. config TARGET_P1010RDB_PA
  44. bool "Support P1010RDB_PA"
  45. select ARCH_P1010
  46. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  47. select SUPPORT_SPL
  48. select SUPPORT_TPL
  49. imply CMD_EEPROM
  50. imply CMD_SATA
  51. imply PANIC_HANG
  52. config TARGET_P1010RDB_PB
  53. bool "Support P1010RDB_PB"
  54. select ARCH_P1010
  55. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  56. select SUPPORT_SPL
  57. select SUPPORT_TPL
  58. imply CMD_EEPROM
  59. imply CMD_SATA
  60. imply PANIC_HANG
  61. config TARGET_P1020RDB_PC
  62. bool "Support P1020RDB-PC"
  63. select SUPPORT_SPL
  64. select SUPPORT_TPL
  65. select ARCH_P1020
  66. imply CMD_EEPROM
  67. imply CMD_SATA
  68. imply PANIC_HANG
  69. config TARGET_P1020RDB_PD
  70. bool "Support P1020RDB-PD"
  71. select SUPPORT_SPL
  72. select SUPPORT_TPL
  73. select ARCH_P1020
  74. imply CMD_EEPROM
  75. imply CMD_SATA
  76. imply PANIC_HANG
  77. config TARGET_P2020RDB
  78. bool "Support P2020RDB-PC"
  79. select SUPPORT_SPL
  80. select SUPPORT_TPL
  81. select ARCH_P2020
  82. imply CMD_EEPROM
  83. imply CMD_SATA
  84. imply SATA_SIL
  85. config TARGET_P2041RDB
  86. bool "Support P2041RDB"
  87. select ARCH_P2041
  88. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  89. select PHYS_64BIT
  90. imply CMD_SATA
  91. imply FSL_SATA
  92. config TARGET_QEMU_PPCE500
  93. bool "Support qemu-ppce500"
  94. select ARCH_QEMU_E500
  95. select PHYS_64BIT
  96. config TARGET_T1024RDB
  97. bool "Support T1024RDB"
  98. select ARCH_T1024
  99. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  100. select SUPPORT_SPL
  101. select PHYS_64BIT
  102. select FSL_DDR_INTERACTIVE
  103. imply CMD_EEPROM
  104. imply PANIC_HANG
  105. config TARGET_T1042RDB
  106. bool "Support T1042RDB"
  107. select ARCH_T1042
  108. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  109. select SUPPORT_SPL
  110. select PHYS_64BIT
  111. config TARGET_T1042D4RDB
  112. bool "Support T1042D4RDB"
  113. select ARCH_T1042
  114. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  115. select SUPPORT_SPL
  116. select PHYS_64BIT
  117. imply PANIC_HANG
  118. config TARGET_T1042RDB_PI
  119. bool "Support T1042RDB_PI"
  120. select ARCH_T1042
  121. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  122. select SUPPORT_SPL
  123. select PHYS_64BIT
  124. imply PANIC_HANG
  125. config TARGET_T2080QDS
  126. bool "Support T2080QDS"
  127. select ARCH_T2080
  128. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  129. select SUPPORT_SPL
  130. select PHYS_64BIT
  131. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  132. select FSL_DDR_INTERACTIVE
  133. imply CMD_SATA
  134. config TARGET_T2080RDB
  135. bool "Support T2080RDB"
  136. select ARCH_T2080
  137. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  138. select SUPPORT_SPL
  139. select PHYS_64BIT
  140. imply CMD_SATA
  141. imply PANIC_HANG
  142. config TARGET_T4240RDB
  143. bool "Support T4240RDB"
  144. select ARCH_T4240
  145. select SUPPORT_SPL
  146. select PHYS_64BIT
  147. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  148. imply CMD_SATA
  149. imply PANIC_HANG
  150. config TARGET_KMP204X
  151. bool "Support kmp204x"
  152. select VENDOR_KM
  153. config TARGET_KMCENT2
  154. bool "Support kmcent2"
  155. select VENDOR_KM
  156. endchoice
  157. config ARCH_B4420
  158. bool
  159. select E500MC
  160. select E6500
  161. select FSL_LAW
  162. select SYS_FSL_DDR_VER_47
  163. select SYS_FSL_ERRATUM_A004477
  164. select SYS_FSL_ERRATUM_A005871
  165. select SYS_FSL_ERRATUM_A006379
  166. select SYS_FSL_ERRATUM_A006384
  167. select SYS_FSL_ERRATUM_A006475
  168. select SYS_FSL_ERRATUM_A006593
  169. select SYS_FSL_ERRATUM_A007075
  170. select SYS_FSL_ERRATUM_A007186
  171. select SYS_FSL_ERRATUM_A007212
  172. select SYS_FSL_ERRATUM_A009942
  173. select SYS_FSL_HAS_DDR3
  174. select SYS_FSL_HAS_SEC
  175. select SYS_FSL_QORIQ_CHASSIS2
  176. select SYS_FSL_SEC_BE
  177. select SYS_FSL_SEC_COMPAT_4
  178. select SYS_PPC64
  179. select FSL_IFC
  180. imply CMD_EEPROM
  181. imply CMD_NAND
  182. imply CMD_REGINFO
  183. config ARCH_B4860
  184. bool
  185. select E500MC
  186. select E6500
  187. select FSL_LAW
  188. select SYS_FSL_DDR_VER_47
  189. select SYS_FSL_ERRATUM_A004477
  190. select SYS_FSL_ERRATUM_A005871
  191. select SYS_FSL_ERRATUM_A006379
  192. select SYS_FSL_ERRATUM_A006384
  193. select SYS_FSL_ERRATUM_A006475
  194. select SYS_FSL_ERRATUM_A006593
  195. select SYS_FSL_ERRATUM_A007075
  196. select SYS_FSL_ERRATUM_A007186
  197. select SYS_FSL_ERRATUM_A007212
  198. select SYS_FSL_ERRATUM_A007907
  199. select SYS_FSL_ERRATUM_A009942
  200. select SYS_FSL_HAS_DDR3
  201. select SYS_FSL_HAS_SEC
  202. select SYS_FSL_QORIQ_CHASSIS2
  203. select SYS_FSL_SEC_BE
  204. select SYS_FSL_SEC_COMPAT_4
  205. select SYS_PPC64
  206. select FSL_IFC
  207. imply CMD_EEPROM
  208. imply CMD_NAND
  209. imply CMD_REGINFO
  210. config ARCH_BSC9131
  211. bool
  212. select FSL_LAW
  213. select SYS_FSL_DDR_VER_44
  214. select SYS_FSL_ERRATUM_A004477
  215. select SYS_FSL_ERRATUM_A005125
  216. select SYS_FSL_ERRATUM_ESDHC111
  217. select SYS_FSL_HAS_DDR3
  218. select SYS_FSL_HAS_SEC
  219. select SYS_FSL_SEC_BE
  220. select SYS_FSL_SEC_COMPAT_4
  221. select FSL_IFC
  222. imply CMD_EEPROM
  223. imply CMD_NAND
  224. imply CMD_REGINFO
  225. config ARCH_BSC9132
  226. bool
  227. select FSL_LAW
  228. select SYS_FSL_DDR_VER_46
  229. select SYS_FSL_ERRATUM_A004477
  230. select SYS_FSL_ERRATUM_A005125
  231. select SYS_FSL_ERRATUM_A005434
  232. select SYS_FSL_ERRATUM_ESDHC111
  233. select SYS_FSL_ERRATUM_I2C_A004447
  234. select SYS_FSL_ERRATUM_IFC_A002769
  235. select FSL_PCIE_RESET
  236. select SYS_FSL_HAS_DDR3
  237. select SYS_FSL_HAS_SEC
  238. select SYS_FSL_SEC_BE
  239. select SYS_FSL_SEC_COMPAT_4
  240. select SYS_PPC_E500_USE_DEBUG_TLB
  241. select FSL_IFC
  242. imply CMD_EEPROM
  243. imply CMD_MTDPARTS
  244. imply CMD_NAND
  245. imply CMD_PCI
  246. imply CMD_REGINFO
  247. config ARCH_C29X
  248. bool
  249. select FSL_LAW
  250. select SYS_FSL_DDR_VER_46
  251. select SYS_FSL_ERRATUM_A005125
  252. select SYS_FSL_ERRATUM_ESDHC111
  253. select FSL_PCIE_RESET
  254. select SYS_FSL_HAS_DDR3
  255. select SYS_FSL_HAS_SEC
  256. select SYS_FSL_SEC_BE
  257. select SYS_FSL_SEC_COMPAT_6
  258. select SYS_PPC_E500_USE_DEBUG_TLB
  259. select FSL_IFC
  260. imply CMD_NAND
  261. imply CMD_PCI
  262. imply CMD_REGINFO
  263. config ARCH_MPC8536
  264. bool
  265. select FSL_LAW
  266. select SYS_FSL_ERRATUM_A004508
  267. select SYS_FSL_ERRATUM_A005125
  268. select FSL_PCIE_RESET
  269. select SYS_FSL_HAS_DDR2
  270. select SYS_FSL_HAS_DDR3
  271. select SYS_FSL_HAS_SEC
  272. select SYS_FSL_SEC_BE
  273. select SYS_FSL_SEC_COMPAT_2
  274. select SYS_PPC_E500_USE_DEBUG_TLB
  275. select FSL_ELBC
  276. imply CMD_NAND
  277. imply CMD_SATA
  278. imply CMD_REGINFO
  279. config ARCH_MPC8540
  280. bool
  281. select FSL_LAW
  282. select SYS_FSL_HAS_DDR1
  283. config ARCH_MPC8544
  284. bool
  285. select FSL_LAW
  286. select SYS_FSL_ERRATUM_A005125
  287. select FSL_PCIE_RESET
  288. select SYS_FSL_HAS_DDR2
  289. select SYS_FSL_HAS_SEC
  290. select SYS_FSL_SEC_BE
  291. select SYS_FSL_SEC_COMPAT_2
  292. select SYS_PPC_E500_USE_DEBUG_TLB
  293. select FSL_ELBC
  294. config ARCH_MPC8548
  295. bool
  296. select FSL_LAW
  297. select SYS_FSL_ERRATUM_A005125
  298. select SYS_FSL_ERRATUM_NMG_DDR120
  299. select SYS_FSL_ERRATUM_NMG_LBC103
  300. select SYS_FSL_ERRATUM_NMG_ETSEC129
  301. select SYS_FSL_ERRATUM_I2C_A004447
  302. select FSL_PCIE_RESET
  303. select SYS_FSL_HAS_DDR2
  304. select SYS_FSL_HAS_DDR1
  305. select SYS_FSL_HAS_SEC
  306. select SYS_FSL_SEC_BE
  307. select SYS_FSL_SEC_COMPAT_2
  308. select SYS_PPC_E500_USE_DEBUG_TLB
  309. imply CMD_REGINFO
  310. config ARCH_MPC8560
  311. bool
  312. select FSL_LAW
  313. select SYS_FSL_HAS_DDR1
  314. config ARCH_P1010
  315. bool
  316. select FSL_LAW
  317. select SYS_FSL_ERRATUM_A004477
  318. select SYS_FSL_ERRATUM_A004508
  319. select SYS_FSL_ERRATUM_A005125
  320. select SYS_FSL_ERRATUM_A005275
  321. select SYS_FSL_ERRATUM_A006261
  322. select SYS_FSL_ERRATUM_A007075
  323. select SYS_FSL_ERRATUM_ESDHC111
  324. select SYS_FSL_ERRATUM_I2C_A004447
  325. select SYS_FSL_ERRATUM_IFC_A002769
  326. select SYS_FSL_ERRATUM_P1010_A003549
  327. select SYS_FSL_ERRATUM_SEC_A003571
  328. select SYS_FSL_ERRATUM_IFC_A003399
  329. select FSL_PCIE_RESET
  330. select SYS_FSL_HAS_DDR3
  331. select SYS_FSL_HAS_SEC
  332. select SYS_FSL_SEC_BE
  333. select SYS_FSL_SEC_COMPAT_4
  334. select SYS_PPC_E500_USE_DEBUG_TLB
  335. select FSL_IFC
  336. imply CMD_EEPROM
  337. imply CMD_MTDPARTS
  338. imply CMD_NAND
  339. imply CMD_SATA
  340. imply CMD_PCI
  341. imply CMD_REGINFO
  342. imply FSL_SATA
  343. config ARCH_P1011
  344. bool
  345. select FSL_LAW
  346. select SYS_FSL_ERRATUM_A004508
  347. select SYS_FSL_ERRATUM_A005125
  348. select SYS_FSL_ERRATUM_ELBC_A001
  349. select SYS_FSL_ERRATUM_ESDHC111
  350. select FSL_PCIE_DISABLE_ASPM
  351. select SYS_FSL_HAS_DDR3
  352. select SYS_FSL_HAS_SEC
  353. select SYS_FSL_SEC_BE
  354. select SYS_FSL_SEC_COMPAT_2
  355. select SYS_PPC_E500_USE_DEBUG_TLB
  356. select FSL_ELBC
  357. config ARCH_P1020
  358. bool
  359. select FSL_LAW
  360. select SYS_FSL_ERRATUM_A004508
  361. select SYS_FSL_ERRATUM_A005125
  362. select SYS_FSL_ERRATUM_ELBC_A001
  363. select SYS_FSL_ERRATUM_ESDHC111
  364. select FSL_PCIE_DISABLE_ASPM
  365. select FSL_PCIE_RESET
  366. select SYS_FSL_HAS_DDR3
  367. select SYS_FSL_HAS_SEC
  368. select SYS_FSL_SEC_BE
  369. select SYS_FSL_SEC_COMPAT_2
  370. select SYS_PPC_E500_USE_DEBUG_TLB
  371. select FSL_ELBC
  372. imply CMD_NAND
  373. imply CMD_SATA
  374. imply CMD_PCI
  375. imply CMD_REGINFO
  376. imply SATA_SIL
  377. config ARCH_P1021
  378. bool
  379. select FSL_LAW
  380. select SYS_FSL_ERRATUM_A004508
  381. select SYS_FSL_ERRATUM_A005125
  382. select SYS_FSL_ERRATUM_ELBC_A001
  383. select SYS_FSL_ERRATUM_ESDHC111
  384. select FSL_PCIE_DISABLE_ASPM
  385. select FSL_PCIE_RESET
  386. select SYS_FSL_HAS_DDR3
  387. select SYS_FSL_HAS_SEC
  388. select SYS_FSL_SEC_BE
  389. select SYS_FSL_SEC_COMPAT_2
  390. select SYS_PPC_E500_USE_DEBUG_TLB
  391. select FSL_ELBC
  392. imply CMD_REGINFO
  393. imply CMD_NAND
  394. imply CMD_SATA
  395. imply CMD_REGINFO
  396. imply SATA_SIL
  397. config ARCH_P1023
  398. bool
  399. select FSL_LAW
  400. select SYS_FSL_ERRATUM_A004508
  401. select SYS_FSL_ERRATUM_A005125
  402. select SYS_FSL_ERRATUM_I2C_A004447
  403. select FSL_PCIE_RESET
  404. select SYS_FSL_HAS_DDR3
  405. select SYS_FSL_HAS_SEC
  406. select SYS_FSL_SEC_BE
  407. select SYS_FSL_SEC_COMPAT_4
  408. select FSL_ELBC
  409. config ARCH_P1024
  410. bool
  411. select FSL_LAW
  412. select SYS_FSL_ERRATUM_A004508
  413. select SYS_FSL_ERRATUM_A005125
  414. select SYS_FSL_ERRATUM_ELBC_A001
  415. select SYS_FSL_ERRATUM_ESDHC111
  416. select FSL_PCIE_DISABLE_ASPM
  417. select FSL_PCIE_RESET
  418. select SYS_FSL_HAS_DDR3
  419. select SYS_FSL_HAS_SEC
  420. select SYS_FSL_SEC_BE
  421. select SYS_FSL_SEC_COMPAT_2
  422. select SYS_PPC_E500_USE_DEBUG_TLB
  423. select FSL_ELBC
  424. imply CMD_EEPROM
  425. imply CMD_NAND
  426. imply CMD_SATA
  427. imply CMD_PCI
  428. imply CMD_REGINFO
  429. imply SATA_SIL
  430. config ARCH_P1025
  431. bool
  432. select FSL_LAW
  433. select SYS_FSL_ERRATUM_A004508
  434. select SYS_FSL_ERRATUM_A005125
  435. select SYS_FSL_ERRATUM_ELBC_A001
  436. select SYS_FSL_ERRATUM_ESDHC111
  437. select FSL_PCIE_DISABLE_ASPM
  438. select FSL_PCIE_RESET
  439. select SYS_FSL_HAS_DDR3
  440. select SYS_FSL_HAS_SEC
  441. select SYS_FSL_SEC_BE
  442. select SYS_FSL_SEC_COMPAT_2
  443. select SYS_PPC_E500_USE_DEBUG_TLB
  444. select FSL_ELBC
  445. imply CMD_SATA
  446. imply CMD_REGINFO
  447. config ARCH_P2020
  448. bool
  449. select FSL_LAW
  450. select SYS_FSL_ERRATUM_A004477
  451. select SYS_FSL_ERRATUM_A004508
  452. select SYS_FSL_ERRATUM_A005125
  453. select SYS_FSL_ERRATUM_ESDHC111
  454. select SYS_FSL_ERRATUM_ESDHC_A001
  455. select FSL_PCIE_RESET
  456. select SYS_FSL_HAS_DDR3
  457. select SYS_FSL_HAS_SEC
  458. select SYS_FSL_SEC_BE
  459. select SYS_FSL_SEC_COMPAT_2
  460. select SYS_PPC_E500_USE_DEBUG_TLB
  461. select FSL_ELBC
  462. imply CMD_EEPROM
  463. imply CMD_NAND
  464. imply CMD_REGINFO
  465. config ARCH_P2041
  466. bool
  467. select E500MC
  468. select FSL_LAW
  469. select SYS_FSL_ERRATUM_A004510
  470. select SYS_FSL_ERRATUM_A004849
  471. select SYS_FSL_ERRATUM_A005275
  472. select SYS_FSL_ERRATUM_A006261
  473. select SYS_FSL_ERRATUM_CPU_A003999
  474. select SYS_FSL_ERRATUM_DDR_A003
  475. select SYS_FSL_ERRATUM_DDR_A003474
  476. select SYS_FSL_ERRATUM_ESDHC111
  477. select SYS_FSL_ERRATUM_I2C_A004447
  478. select SYS_FSL_ERRATUM_NMG_CPU_A011
  479. select SYS_FSL_ERRATUM_SRIO_A004034
  480. select SYS_FSL_ERRATUM_USB14
  481. select SYS_FSL_HAS_DDR3
  482. select SYS_FSL_HAS_SEC
  483. select SYS_FSL_QORIQ_CHASSIS1
  484. select SYS_FSL_SEC_BE
  485. select SYS_FSL_SEC_COMPAT_4
  486. select FSL_ELBC
  487. imply CMD_NAND
  488. config ARCH_P3041
  489. bool
  490. select E500MC
  491. select FSL_LAW
  492. select SYS_FSL_DDR_VER_44
  493. select SYS_FSL_ERRATUM_A004510
  494. select SYS_FSL_ERRATUM_A004849
  495. select SYS_FSL_ERRATUM_A005275
  496. select SYS_FSL_ERRATUM_A005812
  497. select SYS_FSL_ERRATUM_A006261
  498. select SYS_FSL_ERRATUM_CPU_A003999
  499. select SYS_FSL_ERRATUM_DDR_A003
  500. select SYS_FSL_ERRATUM_DDR_A003474
  501. select SYS_FSL_ERRATUM_ESDHC111
  502. select SYS_FSL_ERRATUM_I2C_A004447
  503. select SYS_FSL_ERRATUM_NMG_CPU_A011
  504. select SYS_FSL_ERRATUM_SRIO_A004034
  505. select SYS_FSL_ERRATUM_USB14
  506. select SYS_FSL_HAS_DDR3
  507. select SYS_FSL_HAS_SEC
  508. select SYS_FSL_QORIQ_CHASSIS1
  509. select SYS_FSL_SEC_BE
  510. select SYS_FSL_SEC_COMPAT_4
  511. select FSL_ELBC
  512. imply CMD_NAND
  513. imply CMD_SATA
  514. imply CMD_REGINFO
  515. imply FSL_SATA
  516. config ARCH_P4080
  517. bool
  518. select E500MC
  519. select FSL_LAW
  520. select SYS_FSL_DDR_VER_44
  521. select SYS_FSL_ERRATUM_A004510
  522. select SYS_FSL_ERRATUM_A004580
  523. select SYS_FSL_ERRATUM_A004849
  524. select SYS_FSL_ERRATUM_A005812
  525. select SYS_FSL_ERRATUM_A007075
  526. select SYS_FSL_ERRATUM_CPC_A002
  527. select SYS_FSL_ERRATUM_CPC_A003
  528. select SYS_FSL_ERRATUM_CPU_A003999
  529. select SYS_FSL_ERRATUM_DDR_A003
  530. select SYS_FSL_ERRATUM_DDR_A003474
  531. select SYS_FSL_ERRATUM_ELBC_A001
  532. select SYS_FSL_ERRATUM_ESDHC111
  533. select SYS_FSL_ERRATUM_ESDHC13
  534. select SYS_FSL_ERRATUM_ESDHC135
  535. select SYS_FSL_ERRATUM_I2C_A004447
  536. select SYS_FSL_ERRATUM_NMG_CPU_A011
  537. select SYS_FSL_ERRATUM_SRIO_A004034
  538. select SYS_P4080_ERRATUM_CPU22
  539. select SYS_P4080_ERRATUM_PCIE_A003
  540. select SYS_P4080_ERRATUM_SERDES8
  541. select SYS_P4080_ERRATUM_SERDES9
  542. select SYS_P4080_ERRATUM_SERDES_A001
  543. select SYS_P4080_ERRATUM_SERDES_A005
  544. select SYS_FSL_HAS_DDR3
  545. select SYS_FSL_HAS_SEC
  546. select SYS_FSL_QORIQ_CHASSIS1
  547. select SYS_FSL_SEC_BE
  548. select SYS_FSL_SEC_COMPAT_4
  549. select FSL_ELBC
  550. imply CMD_SATA
  551. imply CMD_REGINFO
  552. imply SATA_SIL
  553. config ARCH_P5040
  554. bool
  555. select E500MC
  556. select FSL_LAW
  557. select SYS_FSL_DDR_VER_44
  558. select SYS_FSL_ERRATUM_A004510
  559. select SYS_FSL_ERRATUM_A004699
  560. select SYS_FSL_ERRATUM_A005275
  561. select SYS_FSL_ERRATUM_A005812
  562. select SYS_FSL_ERRATUM_A006261
  563. select SYS_FSL_ERRATUM_DDR_A003
  564. select SYS_FSL_ERRATUM_DDR_A003474
  565. select SYS_FSL_ERRATUM_ESDHC111
  566. select SYS_FSL_ERRATUM_USB14
  567. select SYS_FSL_HAS_DDR3
  568. select SYS_FSL_HAS_SEC
  569. select SYS_FSL_QORIQ_CHASSIS1
  570. select SYS_FSL_SEC_BE
  571. select SYS_FSL_SEC_COMPAT_4
  572. select SYS_PPC64
  573. select FSL_ELBC
  574. imply CMD_SATA
  575. imply CMD_REGINFO
  576. imply FSL_SATA
  577. config ARCH_QEMU_E500
  578. bool
  579. config ARCH_T1024
  580. bool
  581. select E500MC
  582. select FSL_LAW
  583. select SYS_FSL_DDR_VER_50
  584. select SYS_FSL_ERRATUM_A008378
  585. select SYS_FSL_ERRATUM_A008109
  586. select SYS_FSL_ERRATUM_A009663
  587. select SYS_FSL_ERRATUM_A009942
  588. select SYS_FSL_ERRATUM_ESDHC111
  589. select SYS_FSL_HAS_DDR3
  590. select SYS_FSL_HAS_DDR4
  591. select SYS_FSL_HAS_SEC
  592. select SYS_FSL_QORIQ_CHASSIS2
  593. select SYS_FSL_SEC_BE
  594. select SYS_FSL_SEC_COMPAT_5
  595. select FSL_IFC
  596. imply CMD_EEPROM
  597. imply CMD_NAND
  598. imply CMD_MTDPARTS
  599. imply CMD_REGINFO
  600. config ARCH_T1040
  601. bool
  602. select E500MC
  603. select FSL_LAW
  604. select SYS_FSL_DDR_VER_50
  605. select SYS_FSL_ERRATUM_A008044
  606. select SYS_FSL_ERRATUM_A008378
  607. select SYS_FSL_ERRATUM_A008109
  608. select SYS_FSL_ERRATUM_A009663
  609. select SYS_FSL_ERRATUM_A009942
  610. select SYS_FSL_ERRATUM_ESDHC111
  611. select SYS_FSL_HAS_DDR3
  612. select SYS_FSL_HAS_DDR4
  613. select SYS_FSL_HAS_SEC
  614. select SYS_FSL_QORIQ_CHASSIS2
  615. select SYS_FSL_SEC_BE
  616. select SYS_FSL_SEC_COMPAT_5
  617. select FSL_IFC
  618. imply CMD_MTDPARTS
  619. imply CMD_NAND
  620. imply CMD_REGINFO
  621. config ARCH_T1042
  622. bool
  623. select E500MC
  624. select FSL_LAW
  625. select SYS_FSL_DDR_VER_50
  626. select SYS_FSL_ERRATUM_A008044
  627. select SYS_FSL_ERRATUM_A008378
  628. select SYS_FSL_ERRATUM_A008109
  629. select SYS_FSL_ERRATUM_A009663
  630. select SYS_FSL_ERRATUM_A009942
  631. select SYS_FSL_ERRATUM_ESDHC111
  632. select SYS_FSL_HAS_DDR3
  633. select SYS_FSL_HAS_DDR4
  634. select SYS_FSL_HAS_SEC
  635. select SYS_FSL_QORIQ_CHASSIS2
  636. select SYS_FSL_SEC_BE
  637. select SYS_FSL_SEC_COMPAT_5
  638. select FSL_IFC
  639. imply CMD_MTDPARTS
  640. imply CMD_NAND
  641. imply CMD_REGINFO
  642. config ARCH_T2080
  643. bool
  644. select E500MC
  645. select E6500
  646. select FSL_LAW
  647. select SYS_FSL_DDR_VER_47
  648. select SYS_FSL_ERRATUM_A006379
  649. select SYS_FSL_ERRATUM_A006593
  650. select SYS_FSL_ERRATUM_A007186
  651. select SYS_FSL_ERRATUM_A007212
  652. select SYS_FSL_ERRATUM_A007815
  653. select SYS_FSL_ERRATUM_A007907
  654. select SYS_FSL_ERRATUM_A008109
  655. select SYS_FSL_ERRATUM_A009942
  656. select SYS_FSL_ERRATUM_ESDHC111
  657. select FSL_PCIE_RESET
  658. select SYS_FSL_HAS_DDR3
  659. select SYS_FSL_HAS_SEC
  660. select SYS_FSL_QORIQ_CHASSIS2
  661. select SYS_FSL_SEC_BE
  662. select SYS_FSL_SEC_COMPAT_4
  663. select SYS_PPC64
  664. select FSL_IFC
  665. imply CMD_SATA
  666. imply CMD_NAND
  667. imply CMD_REGINFO
  668. imply FSL_SATA
  669. imply ID_EEPROM
  670. config ARCH_T4240
  671. bool
  672. select E500MC
  673. select E6500
  674. select FSL_LAW
  675. select SYS_FSL_DDR_VER_47
  676. select SYS_FSL_ERRATUM_A004468
  677. select SYS_FSL_ERRATUM_A005871
  678. select SYS_FSL_ERRATUM_A006261
  679. select SYS_FSL_ERRATUM_A006379
  680. select SYS_FSL_ERRATUM_A006593
  681. select SYS_FSL_ERRATUM_A007186
  682. select SYS_FSL_ERRATUM_A007798
  683. select SYS_FSL_ERRATUM_A007815
  684. select SYS_FSL_ERRATUM_A007907
  685. select SYS_FSL_ERRATUM_A008109
  686. select SYS_FSL_ERRATUM_A009942
  687. select SYS_FSL_HAS_DDR3
  688. select SYS_FSL_HAS_SEC
  689. select SYS_FSL_QORIQ_CHASSIS2
  690. select SYS_FSL_SEC_BE
  691. select SYS_FSL_SEC_COMPAT_4
  692. select SYS_PPC64
  693. select FSL_IFC
  694. imply CMD_SATA
  695. imply CMD_NAND
  696. imply CMD_REGINFO
  697. imply FSL_SATA
  698. config MPC85XX_HAVE_RESET_VECTOR
  699. bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
  700. depends on MPC85xx
  701. config BOOKE
  702. bool
  703. default y
  704. config E500
  705. bool
  706. default y
  707. help
  708. Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
  709. config E500MC
  710. bool
  711. imply CMD_PCI
  712. help
  713. Enble PowerPC E500MC core
  714. config E6500
  715. bool
  716. help
  717. Enable PowerPC E6500 core
  718. config FSL_LAW
  719. bool
  720. help
  721. Use Freescale common code for Local Access Window
  722. config NXP_ESBC
  723. bool "NXP_ESBC"
  724. help
  725. Enable Freescale Secure Boot feature. Normally selected
  726. by defconfig. If unsure, do not change.
  727. config MAX_CPUS
  728. int "Maximum number of CPUs permitted for MPC85xx"
  729. default 12 if ARCH_T4240
  730. default 8 if ARCH_P4080
  731. default 4 if ARCH_B4860 || \
  732. ARCH_P2041 || \
  733. ARCH_P3041 || \
  734. ARCH_P5040 || \
  735. ARCH_T1040 || \
  736. ARCH_T1042 || \
  737. ARCH_T2080
  738. default 2 if ARCH_B4420 || \
  739. ARCH_BSC9132 || \
  740. ARCH_P1020 || \
  741. ARCH_P1021 || \
  742. ARCH_P1023 || \
  743. ARCH_P1024 || \
  744. ARCH_P1025 || \
  745. ARCH_P2020 || \
  746. ARCH_T1024
  747. default 1
  748. help
  749. Set this number to the maximum number of possible CPUs in the SoC.
  750. SoCs may have multiple clusters with each cluster may have multiple
  751. ports. If some ports are reserved but higher ports are used for
  752. cores, count the reserved ports. This will allocate enough memory
  753. in spin table to properly handle all cores.
  754. config SYS_CCSRBAR_DEFAULT
  755. hex "Default CCSRBAR address"
  756. default 0xff700000 if ARCH_BSC9131 || \
  757. ARCH_BSC9132 || \
  758. ARCH_C29X || \
  759. ARCH_MPC8536 || \
  760. ARCH_MPC8540 || \
  761. ARCH_MPC8544 || \
  762. ARCH_MPC8548 || \
  763. ARCH_MPC8560 || \
  764. ARCH_P1010 || \
  765. ARCH_P1011 || \
  766. ARCH_P1020 || \
  767. ARCH_P1021 || \
  768. ARCH_P1024 || \
  769. ARCH_P1025 || \
  770. ARCH_P2020
  771. default 0xff600000 if ARCH_P1023
  772. default 0xfe000000 if ARCH_B4420 || \
  773. ARCH_B4860 || \
  774. ARCH_P2041 || \
  775. ARCH_P3041 || \
  776. ARCH_P4080 || \
  777. ARCH_P5040 || \
  778. ARCH_T1024 || \
  779. ARCH_T1040 || \
  780. ARCH_T1042 || \
  781. ARCH_T2080 || \
  782. ARCH_T4240
  783. default 0xe0000000 if ARCH_QEMU_E500
  784. help
  785. Default value of CCSRBAR comes from power-on-reset. It
  786. is fixed on each SoC. Some SoCs can have different value
  787. if changed by pre-boot regime. The value here must match
  788. the current value in SoC. If not sure, do not change.
  789. config SYS_FSL_ERRATUM_A004468
  790. bool
  791. config SYS_FSL_ERRATUM_A004477
  792. bool
  793. config SYS_FSL_ERRATUM_A004508
  794. bool
  795. config SYS_FSL_ERRATUM_A004580
  796. bool
  797. config SYS_FSL_ERRATUM_A004699
  798. bool
  799. config SYS_FSL_ERRATUM_A004849
  800. bool
  801. config SYS_FSL_ERRATUM_A004510
  802. bool
  803. config SYS_FSL_ERRATUM_A004510_SVR_REV
  804. hex
  805. depends on SYS_FSL_ERRATUM_A004510
  806. default 0x20 if ARCH_P4080
  807. default 0x10
  808. config SYS_FSL_ERRATUM_A004510_SVR_REV2
  809. hex
  810. depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
  811. default 0x11
  812. config SYS_FSL_ERRATUM_A005125
  813. bool
  814. config SYS_FSL_ERRATUM_A005434
  815. bool
  816. config SYS_FSL_ERRATUM_A005812
  817. bool
  818. config SYS_FSL_ERRATUM_A005871
  819. bool
  820. config SYS_FSL_ERRATUM_A005275
  821. bool
  822. config SYS_FSL_ERRATUM_A006261
  823. bool
  824. config SYS_FSL_ERRATUM_A006379
  825. bool
  826. config SYS_FSL_ERRATUM_A006384
  827. bool
  828. config SYS_FSL_ERRATUM_A006475
  829. bool
  830. config SYS_FSL_ERRATUM_A006593
  831. bool
  832. config SYS_FSL_ERRATUM_A007075
  833. bool
  834. config SYS_FSL_ERRATUM_A007186
  835. bool
  836. config SYS_FSL_ERRATUM_A007212
  837. bool
  838. config SYS_FSL_ERRATUM_A007815
  839. bool
  840. config SYS_FSL_ERRATUM_A007798
  841. bool
  842. config SYS_FSL_ERRATUM_A007907
  843. bool
  844. config SYS_FSL_ERRATUM_A008044
  845. bool
  846. config SYS_FSL_ERRATUM_CPC_A002
  847. bool
  848. config SYS_FSL_ERRATUM_CPC_A003
  849. bool
  850. config SYS_FSL_ERRATUM_CPU_A003999
  851. bool
  852. config SYS_FSL_ERRATUM_ELBC_A001
  853. bool
  854. config SYS_FSL_ERRATUM_I2C_A004447
  855. bool
  856. config SYS_FSL_A004447_SVR_REV
  857. hex
  858. depends on SYS_FSL_ERRATUM_I2C_A004447
  859. default 0x00 if ARCH_MPC8548
  860. default 0x10 if ARCH_P1010
  861. default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
  862. default 0x20 if ARCH_P3041 || ARCH_P4080
  863. config SYS_FSL_ERRATUM_IFC_A002769
  864. bool
  865. config SYS_FSL_ERRATUM_IFC_A003399
  866. bool
  867. config SYS_FSL_ERRATUM_NMG_CPU_A011
  868. bool
  869. config SYS_FSL_ERRATUM_NMG_ETSEC129
  870. bool
  871. config SYS_FSL_ERRATUM_NMG_LBC103
  872. bool
  873. config SYS_FSL_ERRATUM_P1010_A003549
  874. bool
  875. config SYS_FSL_ERRATUM_SATA_A001
  876. bool
  877. config SYS_FSL_ERRATUM_SEC_A003571
  878. bool
  879. config SYS_FSL_ERRATUM_SRIO_A004034
  880. bool
  881. config SYS_FSL_ERRATUM_USB14
  882. bool
  883. config SYS_P4080_ERRATUM_CPU22
  884. bool
  885. config SYS_P4080_ERRATUM_PCIE_A003
  886. bool
  887. config SYS_P4080_ERRATUM_SERDES8
  888. bool
  889. config SYS_P4080_ERRATUM_SERDES9
  890. bool
  891. config SYS_P4080_ERRATUM_SERDES_A001
  892. bool
  893. config SYS_P4080_ERRATUM_SERDES_A005
  894. bool
  895. config FSL_PCIE_DISABLE_ASPM
  896. bool
  897. config FSL_PCIE_RESET
  898. bool
  899. config SYS_FSL_QORIQ_CHASSIS1
  900. bool
  901. config SYS_FSL_QORIQ_CHASSIS2
  902. bool
  903. config SYS_FSL_NUM_LAWS
  904. int "Number of local access windows"
  905. depends on FSL_LAW
  906. default 32 if ARCH_B4420 || \
  907. ARCH_B4860 || \
  908. ARCH_P2041 || \
  909. ARCH_P3041 || \
  910. ARCH_P4080 || \
  911. ARCH_P5040 || \
  912. ARCH_T2080 || \
  913. ARCH_T4240
  914. default 16 if ARCH_T1024 || \
  915. ARCH_T1040 || \
  916. ARCH_T1042
  917. default 12 if ARCH_BSC9131 || \
  918. ARCH_BSC9132 || \
  919. ARCH_C29X || \
  920. ARCH_MPC8536 || \
  921. ARCH_P1010 || \
  922. ARCH_P1011 || \
  923. ARCH_P1020 || \
  924. ARCH_P1021 || \
  925. ARCH_P1023 || \
  926. ARCH_P1024 || \
  927. ARCH_P1025 || \
  928. ARCH_P2020
  929. default 10 if ARCH_MPC8544 || \
  930. ARCH_MPC8548
  931. default 8 if ARCH_MPC8540 || \
  932. ARCH_MPC8560
  933. help
  934. Number of local access windows. This is fixed per SoC.
  935. If not sure, do not change.
  936. config SYS_FSL_THREADS_PER_CORE
  937. int
  938. default 2 if E6500
  939. default 1
  940. config SYS_NUM_TLBCAMS
  941. int "Number of TLB CAM entries"
  942. default 64 if E500MC
  943. default 16
  944. help
  945. Number of TLB CAM entries for Book-E chips. 64 for E500MC,
  946. 16 for other E500 SoCs.
  947. config SYS_PPC64
  948. bool
  949. config SYS_PPC_E500_USE_DEBUG_TLB
  950. bool
  951. config FSL_IFC
  952. bool
  953. config FSL_ELBC
  954. bool
  955. config SYS_PPC_E500_DEBUG_TLB
  956. int "Temporary TLB entry for external debugger"
  957. depends on SYS_PPC_E500_USE_DEBUG_TLB
  958. default 0 if ARCH_MPC8544 || ARCH_MPC8548
  959. default 1 if ARCH_MPC8536
  960. default 2 if ARCH_P1011 || \
  961. ARCH_P1020 || \
  962. ARCH_P1021 || \
  963. ARCH_P1024 || \
  964. ARCH_P1025 || \
  965. ARCH_P2020
  966. default 3 if ARCH_P1010 || \
  967. ARCH_BSC9132 || \
  968. ARCH_C29X
  969. help
  970. Select a temporary TLB entry to be used during boot to work
  971. around limitations in e500v1 and e500v2 external debugger
  972. support. This reduces the portions of the boot code where
  973. breakpoints and single stepping do not work. The value of this
  974. symbol should be set to the TLB1 entry to be used for this
  975. purpose. If unsure, do not change.
  976. config SYS_FSL_IFC_CLK_DIV
  977. int "Divider of platform clock"
  978. depends on FSL_IFC
  979. default 2 if ARCH_B4420 || \
  980. ARCH_B4860 || \
  981. ARCH_T1024 || \
  982. ARCH_T1040 || \
  983. ARCH_T1042 || \
  984. ARCH_T4240
  985. default 1
  986. help
  987. Defines divider of platform clock(clock input to
  988. IFC controller).
  989. config SYS_FSL_LBC_CLK_DIV
  990. int "Divider of platform clock"
  991. depends on FSL_ELBC || ARCH_MPC8540 || \
  992. ARCH_MPC8548 || \
  993. ARCH_MPC8560
  994. default 2 if ARCH_P2041 || \
  995. ARCH_P3041 || \
  996. ARCH_P4080 || \
  997. ARCH_P5040
  998. default 1
  999. help
  1000. Defines divider of platform clock(clock input to
  1001. eLBC controller).
  1002. config FSL_VIA
  1003. bool
  1004. source "board/emulation/qemu-ppce500/Kconfig"
  1005. source "board/freescale/corenet_ds/Kconfig"
  1006. source "board/freescale/mpc8548cds/Kconfig"
  1007. source "board/freescale/p1010rdb/Kconfig"
  1008. source "board/freescale/p1_p2_rdb_pc/Kconfig"
  1009. source "board/freescale/p2041rdb/Kconfig"
  1010. source "board/freescale/t102xrdb/Kconfig"
  1011. source "board/freescale/t104xrdb/Kconfig"
  1012. source "board/freescale/t208xqds/Kconfig"
  1013. source "board/freescale/t208xrdb/Kconfig"
  1014. source "board/freescale/t4rdb/Kconfig"
  1015. source "board/keymile/Kconfig"
  1016. source "board/socrates/Kconfig"
  1017. endmenu