Kconfig 17 KB

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  1. config ARCH_LS1012A
  2. bool
  3. select ARMV8_SET_SMPEN
  4. select ARM_ERRATA_855873 if !TFABOOT
  5. select FSL_LAYERSCAPE
  6. select FSL_LSCH2
  7. select SYS_FSL_SRDS_1
  8. select SYS_HAS_SERDES
  9. select SYS_FSL_DDR_BE
  10. select SYS_FSL_MMDC
  11. select SYS_FSL_ERRATUM_A010315
  12. select SYS_FSL_ERRATUM_A009798
  13. select SYS_FSL_ERRATUM_A008997
  14. select SYS_FSL_ERRATUM_A009007
  15. select SYS_FSL_ERRATUM_A009008
  16. select ARCH_EARLY_INIT_R
  17. select BOARD_EARLY_INIT_F
  18. select SYS_I2C_MXC
  19. select SYS_I2C_MXC_I2C1 if !DM_I2C
  20. select SYS_I2C_MXC_I2C2 if !DM_I2C
  21. imply PANIC_HANG
  22. config ARCH_LS1028A
  23. bool
  24. select ARMV8_SET_SMPEN
  25. select FSL_LAYERSCAPE
  26. select FSL_LSCH3
  27. select NXP_LSCH3_2
  28. select SYS_FSL_HAS_CCI400
  29. select SYS_FSL_SRDS_1
  30. select SYS_HAS_SERDES
  31. select SYS_FSL_DDR
  32. select SYS_FSL_DDR_LE
  33. select SYS_FSL_DDR_VER_50
  34. select SYS_FSL_HAS_DDR3
  35. select SYS_FSL_HAS_DDR4
  36. select SYS_FSL_HAS_SEC
  37. select SYS_FSL_SEC_COMPAT_5
  38. select SYS_FSL_SEC_LE
  39. select FSL_TZASC_1
  40. select ARCH_EARLY_INIT_R
  41. select BOARD_EARLY_INIT_F
  42. select SYS_I2C_MXC
  43. select SYS_FSL_ERRATUM_A008997
  44. select SYS_FSL_ERRATUM_A009007
  45. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  46. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  47. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  48. select SYS_FSL_ERRATUM_A050382
  49. select SYS_FSL_ERRATUM_A011334
  50. select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
  51. select RESV_RAM if GIC_V3_ITS
  52. imply PANIC_HANG
  53. config ARCH_LS1043A
  54. bool
  55. select ARMV8_SET_SMPEN
  56. select ARM_ERRATA_855873 if !TFABOOT
  57. select FSL_LAYERSCAPE
  58. select FSL_LSCH2
  59. select HAS_FSL_XHCI_USB if USB_HOST
  60. select SYS_FSL_SRDS_1
  61. select SYS_HAS_SERDES
  62. select SYS_FSL_DDR
  63. select SYS_FSL_DDR_BE
  64. select SYS_FSL_DDR_VER_50
  65. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  66. select SYS_FSL_ERRATUM_A008997
  67. select SYS_FSL_ERRATUM_A009007
  68. select SYS_FSL_ERRATUM_A009008
  69. select SYS_FSL_ERRATUM_A009660 if !TFABOOT
  70. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  71. select SYS_FSL_ERRATUM_A009798
  72. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  73. select SYS_FSL_ERRATUM_A010315
  74. select SYS_FSL_ERRATUM_A010539
  75. select SYS_FSL_HAS_DDR3
  76. select SYS_FSL_HAS_DDR4
  77. select ARCH_EARLY_INIT_R
  78. select BOARD_EARLY_INIT_F
  79. select SYS_I2C_MXC
  80. select SYS_I2C_MXC_I2C1 if !DM_I2C
  81. select SYS_I2C_MXC_I2C2 if !DM_I2C
  82. select SYS_I2C_MXC_I2C3 if !DM_I2C
  83. select SYS_I2C_MXC_I2C4 if !DM_I2C
  84. imply CMD_PCI
  85. imply ID_EEPROM
  86. config ARCH_LS1046A
  87. bool
  88. select ARMV8_SET_SMPEN
  89. select FSL_LAYERSCAPE
  90. select FSL_LSCH2
  91. select HAS_FSL_XHCI_USB if USB_HOST
  92. select SYS_FSL_SRDS_1
  93. select SYS_HAS_SERDES
  94. select SYS_FSL_DDR
  95. select SYS_FSL_DDR_BE
  96. select SYS_FSL_DDR_VER_50
  97. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  98. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  99. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  100. select SYS_FSL_ERRATUM_A008997
  101. select SYS_FSL_ERRATUM_A009007
  102. select SYS_FSL_ERRATUM_A009008
  103. select SYS_FSL_ERRATUM_A009798
  104. select SYS_FSL_ERRATUM_A009801
  105. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  106. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  107. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  108. select SYS_FSL_ERRATUM_A010539
  109. select SYS_FSL_HAS_DDR4
  110. select SYS_FSL_SRDS_2
  111. select ARCH_EARLY_INIT_R
  112. select BOARD_EARLY_INIT_F
  113. select SYS_I2C_MXC
  114. select SYS_I2C_MXC_I2C1 if !DM_I2C
  115. select SYS_I2C_MXC_I2C2 if !DM_I2C
  116. select SYS_I2C_MXC_I2C3 if !DM_I2C
  117. select SYS_I2C_MXC_I2C4 if !DM_I2C
  118. imply ID_EEPROM
  119. imply SCSI
  120. imply SCSI_AHCI
  121. config ARCH_LS1088A
  122. bool
  123. select ARMV8_SET_SMPEN
  124. select ARM_ERRATA_855873 if !TFABOOT
  125. select FSL_LAYERSCAPE
  126. select FSL_LSCH3
  127. select SYS_FSL_SRDS_1
  128. select SYS_HAS_SERDES
  129. select SYS_FSL_DDR
  130. select SYS_FSL_DDR_LE
  131. select SYS_FSL_DDR_VER_50
  132. select SYS_FSL_EC1
  133. select SYS_FSL_EC2
  134. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  135. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  136. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  137. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  138. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  139. select SYS_FSL_ERRATUM_A009007
  140. select SYS_FSL_HAS_CCI400
  141. select SYS_FSL_HAS_DDR4
  142. select SYS_FSL_HAS_RGMII
  143. select SYS_FSL_HAS_SEC
  144. select SYS_FSL_SEC_COMPAT_5
  145. select SYS_FSL_SEC_LE
  146. select SYS_FSL_SRDS_1
  147. select SYS_FSL_SRDS_2
  148. select FSL_TZASC_1
  149. select FSL_TZASC_400
  150. select FSL_TZPC_BP147
  151. select ARCH_EARLY_INIT_R
  152. select BOARD_EARLY_INIT_F
  153. select SYS_I2C_MXC
  154. select SYS_I2C_MXC_I2C1 if !TFABOOT
  155. select SYS_I2C_MXC_I2C2 if !TFABOOT
  156. select SYS_I2C_MXC_I2C3 if !TFABOOT
  157. select SYS_I2C_MXC_I2C4 if !TFABOOT
  158. select RESV_RAM if GIC_V3_ITS
  159. imply ID_EEPROM
  160. imply SCSI
  161. imply PANIC_HANG
  162. config ARCH_LS2080A
  163. bool
  164. select ARMV8_SET_SMPEN
  165. select ARM_ERRATA_826974
  166. select ARM_ERRATA_828024
  167. select ARM_ERRATA_829520
  168. select ARM_ERRATA_833471
  169. select FSL_LAYERSCAPE
  170. select FSL_LSCH3
  171. select SYS_FSL_SRDS_1
  172. select SYS_HAS_SERDES
  173. select SYS_FSL_DDR
  174. select SYS_FSL_DDR_LE
  175. select SYS_FSL_DDR_VER_50
  176. select SYS_FSL_HAS_CCN504
  177. select SYS_FSL_HAS_DP_DDR
  178. select SYS_FSL_HAS_SEC
  179. select SYS_FSL_HAS_DDR4
  180. select SYS_FSL_SEC_COMPAT_5
  181. select SYS_FSL_SEC_LE
  182. select SYS_FSL_SRDS_2
  183. select FSL_TZASC_1
  184. select FSL_TZASC_2
  185. select FSL_TZASC_400
  186. select FSL_TZPC_BP147
  187. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  188. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  189. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  190. select SYS_FSL_ERRATUM_A008585
  191. select SYS_FSL_ERRATUM_A008997
  192. select SYS_FSL_ERRATUM_A009007
  193. select SYS_FSL_ERRATUM_A009008
  194. select SYS_FSL_ERRATUM_A009635
  195. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  196. select SYS_FSL_ERRATUM_A009798
  197. select SYS_FSL_ERRATUM_A009801
  198. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  199. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  200. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  201. select SYS_FSL_ERRATUM_A009203
  202. select ARCH_EARLY_INIT_R
  203. select BOARD_EARLY_INIT_F
  204. select SYS_I2C_MXC
  205. select SYS_I2C_MXC_I2C1 if !TFABOOT
  206. select SYS_I2C_MXC_I2C2 if !TFABOOT
  207. select SYS_I2C_MXC_I2C3 if !TFABOOT
  208. select SYS_I2C_MXC_I2C4 if !TFABOOT
  209. select RESV_RAM if GIC_V3_ITS
  210. imply DISTRO_DEFAULTS
  211. imply ID_EEPROM
  212. imply PANIC_HANG
  213. config ARCH_LX2162A
  214. bool
  215. select ARMV8_SET_SMPEN
  216. select FSL_LSCH3
  217. select NXP_LSCH3_2
  218. select SYS_HAS_SERDES
  219. select SYS_FSL_SRDS_1
  220. select SYS_FSL_SRDS_2
  221. select SYS_FSL_DDR
  222. select SYS_FSL_DDR_LE
  223. select SYS_FSL_DDR_VER_50
  224. select SYS_FSL_EC1
  225. select SYS_FSL_EC2
  226. select SYS_FSL_ERRATUM_A050204
  227. select SYS_FSL_ERRATUM_A011334
  228. select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
  229. select SYS_FSL_HAS_RGMII
  230. select SYS_FSL_HAS_SEC
  231. select SYS_FSL_HAS_CCN508
  232. select SYS_FSL_HAS_DDR4
  233. select SYS_FSL_SEC_COMPAT_5
  234. select SYS_FSL_SEC_LE
  235. select ARCH_EARLY_INIT_R
  236. select BOARD_EARLY_INIT_F
  237. select SYS_I2C_MXC
  238. select RESV_RAM if GIC_V3_ITS
  239. imply DISTRO_DEFAULTS
  240. imply PANIC_HANG
  241. imply SCSI
  242. imply SCSI_AHCI
  243. config ARCH_LX2160A
  244. bool
  245. select ARMV8_SET_SMPEN
  246. select FSL_LSCH3
  247. select HAS_FSL_XHCI_USB if USB_HOST
  248. select NXP_LSCH3_2
  249. select SYS_HAS_SERDES
  250. select SYS_FSL_SRDS_1
  251. select SYS_FSL_SRDS_2
  252. select SYS_NXP_SRDS_3
  253. select SYS_FSL_DDR
  254. select SYS_FSL_DDR_LE
  255. select SYS_FSL_DDR_VER_50
  256. select SYS_FSL_EC1
  257. select SYS_FSL_EC2
  258. select SYS_FSL_ERRATUM_A050204
  259. select SYS_FSL_ERRATUM_A011334
  260. select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
  261. select SYS_FSL_HAS_RGMII
  262. select SYS_FSL_HAS_SEC
  263. select SYS_FSL_HAS_CCN508
  264. select SYS_FSL_HAS_DDR4
  265. select SYS_FSL_SEC_COMPAT_5
  266. select SYS_FSL_SEC_LE
  267. select ARCH_EARLY_INIT_R
  268. select BOARD_EARLY_INIT_F
  269. select SYS_I2C_MXC
  270. select RESV_RAM if GIC_V3_ITS
  271. imply DISTRO_DEFAULTS
  272. imply ID_EEPROM
  273. imply PANIC_HANG
  274. imply SCSI
  275. imply SCSI_AHCI
  276. config FSL_LSCH2
  277. bool
  278. select SYS_FSL_HAS_CCI400
  279. select SYS_FSL_HAS_SEC
  280. select SYS_FSL_SEC_COMPAT_5
  281. select SYS_FSL_SEC_BE
  282. config FSL_LSCH3
  283. select ARCH_MISC_INIT
  284. bool
  285. config NXP_LSCH3_2
  286. bool
  287. menu "Layerscape architecture"
  288. depends on FSL_LSCH2 || FSL_LSCH3
  289. config FSL_LAYERSCAPE
  290. bool
  291. config HAS_FEATURE_GIC64K_ALIGN
  292. bool
  293. default y if ARCH_LS1043A
  294. config HAS_FEATURE_ENHANCED_MSI
  295. bool
  296. default y if ARCH_LS1043A
  297. menu "Layerscape PPA"
  298. config FSL_LS_PPA
  299. bool "FSL Layerscape PPA firmware support"
  300. depends on !ARMV8_PSCI
  301. select ARMV8_SEC_FIRMWARE_SUPPORT
  302. select SEC_FIRMWARE_ARMV8_PSCI
  303. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  304. help
  305. The FSL Primary Protected Application (PPA) is a software component
  306. which is loaded during boot stage, and then remains resident in RAM
  307. and runs in the TrustZone after boot.
  308. Say y to enable it.
  309. config SPL_FSL_LS_PPA
  310. bool "FSL Layerscape PPA firmware support for SPL build"
  311. depends on !ARMV8_PSCI
  312. select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  313. select SEC_FIRMWARE_ARMV8_PSCI
  314. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  315. help
  316. The FSL Primary Protected Application (PPA) is a software component
  317. which is loaded during boot stage, and then remains resident in RAM
  318. and runs in the TrustZone after boot. This is to load PPA during SPL
  319. stage instead of the RAM version of U-Boot. Once PPA is initialized,
  320. the rest of U-Boot (including RAM version) runs at EL2.
  321. choice
  322. prompt "FSL Layerscape PPA firmware loading-media select"
  323. depends on FSL_LS_PPA
  324. default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
  325. default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
  326. default SYS_LS_PPA_FW_IN_XIP
  327. config SYS_LS_PPA_FW_IN_XIP
  328. bool "XIP"
  329. help
  330. Say Y here if the PPA firmware locate at XIP flash, such
  331. as NOR or QSPI flash.
  332. config SYS_LS_PPA_FW_IN_MMC
  333. bool "eMMC or SD Card"
  334. help
  335. Say Y here if the PPA firmware locate at eMMC/SD card.
  336. config SYS_LS_PPA_FW_IN_NAND
  337. bool "NAND"
  338. help
  339. Say Y here if the PPA firmware locate at NAND flash.
  340. endchoice
  341. config LS_PPA_ESBC_HDR_SIZE
  342. hex "Length of PPA ESBC header"
  343. depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
  344. default 0x2000
  345. help
  346. Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
  347. NAND to memory to validate PPA image.
  348. endmenu
  349. config SYS_FSL_ERRATUM_A008997
  350. bool "Workaround for USB PHY erratum A008997"
  351. config SYS_FSL_ERRATUM_A009007
  352. bool
  353. help
  354. Workaround for USB PHY erratum A009007
  355. config SYS_FSL_ERRATUM_A009008
  356. bool "Workaround for USB PHY erratum A009008"
  357. config SYS_FSL_ERRATUM_A009798
  358. bool "Workaround for USB PHY erratum A009798"
  359. config SYS_FSL_ERRATUM_A050204
  360. bool "Workaround for USB PHY erratum A050204"
  361. help
  362. USB3.0 Receiver needs to enable fixed equalization
  363. for each of PHY instances in an SOC. This is similar
  364. to erratum A-009007, but this one is for LX2160A and LX2162A,
  365. and the register value is different.
  366. config SYS_FSL_ERRATUM_A010315
  367. bool "Workaround for PCIe erratum A010315"
  368. config SYS_FSL_ERRATUM_A010539
  369. bool "Workaround for PIN MUX erratum A010539"
  370. config MAX_CPUS
  371. int "Maximum number of CPUs permitted for Layerscape"
  372. default 2 if ARCH_LS1028A
  373. default 4 if ARCH_LS1043A
  374. default 4 if ARCH_LS1046A
  375. default 16 if ARCH_LS2080A
  376. default 8 if ARCH_LS1088A
  377. default 16 if ARCH_LX2160A
  378. default 16 if ARCH_LX2162A
  379. default 1
  380. help
  381. Set this number to the maximum number of possible CPUs in the SoC.
  382. SoCs may have multiple clusters with each cluster may have multiple
  383. ports. If some ports are reserved but higher ports are used for
  384. cores, count the reserved ports. This will allocate enough memory
  385. in spin table to properly handle all cores.
  386. config EMC2305
  387. bool "Fan controller"
  388. help
  389. Enable the EMC2305 fan controller for configuration of fan
  390. speed.
  391. config NXP_ESBC
  392. bool "NXP_ESBC"
  393. help
  394. Enable Freescale Secure Boot feature
  395. config QSPI_AHB_INIT
  396. bool "Init the QSPI AHB bus"
  397. help
  398. The default setting for QSPI AHB bus just support 3bytes addressing.
  399. But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
  400. bus for those flashes to support the full QSPI flash size.
  401. config FSPI_AHB_EN_4BYTE
  402. bool "Enable 4-byte Fast Read command for AHB mode"
  403. default n
  404. help
  405. The default setting for FlexSPI AHB bus just supports 3-byte addressing.
  406. But some FlexSPI flash sizes are up to 64MBytes.
  407. This flag enables fast read command for AHB mode and modifies required
  408. LUT to support full FlexSPI flash.
  409. config SYS_CCI400_OFFSET
  410. hex "Offset for CCI400 base"
  411. depends on SYS_FSL_HAS_CCI400
  412. default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
  413. default 0x180000 if FSL_LSCH2
  414. help
  415. Offset for CCI400 base
  416. CCI400 base addr = CCSRBAR + CCI400_OFFSET
  417. config SYS_FSL_IFC_BANK_COUNT
  418. int "Maximum banks of Integrated flash controller"
  419. depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
  420. default 4 if ARCH_LS1043A
  421. default 4 if ARCH_LS1046A
  422. default 8 if ARCH_LS2080A || ARCH_LS1088A
  423. config SYS_FSL_HAS_CCI400
  424. bool
  425. config SYS_FSL_HAS_CCN504
  426. bool
  427. config SYS_FSL_HAS_CCN508
  428. bool
  429. config SYS_FSL_HAS_DP_DDR
  430. bool
  431. config SYS_FSL_SRDS_1
  432. bool
  433. config SYS_FSL_SRDS_2
  434. bool
  435. config SYS_NXP_SRDS_3
  436. bool
  437. config SYS_HAS_SERDES
  438. bool
  439. config FSL_TZASC_1
  440. bool
  441. config FSL_TZASC_2
  442. bool
  443. config FSL_TZASC_400
  444. bool
  445. config FSL_TZPC_BP147
  446. bool
  447. endmenu
  448. menu "Layerscape clock tree configuration"
  449. depends on FSL_LSCH2 || FSL_LSCH3
  450. config SYS_FSL_CLK
  451. bool "Enable clock tree initialization"
  452. default y
  453. config CLUSTER_CLK_FREQ
  454. int "Reference clock of core cluster"
  455. depends on ARCH_LS1012A
  456. default 100000000
  457. help
  458. This number is the reference clock frequency of core PLL.
  459. For most platforms, the core PLL and Platform PLL have the same
  460. reference clock, but for some platforms, LS1012A for instance,
  461. they are provided sepatately.
  462. config SYS_FSL_PCLK_DIV
  463. int "Platform clock divider"
  464. default 1 if ARCH_LS1028A
  465. default 1 if ARCH_LS1043A
  466. default 1 if ARCH_LS1046A
  467. default 1 if ARCH_LS1088A
  468. default 2
  469. help
  470. This is the divider that is used to derive Platform clock from
  471. Platform PLL, in another word:
  472. Platform_clk = Platform_PLL_freq / this_divider
  473. config SYS_FSL_DSPI_CLK_DIV
  474. int "DSPI clock divider"
  475. default 1 if ARCH_LS1043A
  476. default 2
  477. help
  478. This is the divider that is used to derive DSPI clock from Platform
  479. clock, in another word DSPI_clk = Platform_clk / this_divider.
  480. config SYS_FSL_DUART_CLK_DIV
  481. int "DUART clock divider"
  482. default 1 if ARCH_LS1043A
  483. default 4 if ARCH_LX2160A
  484. default 4 if ARCH_LX2162A
  485. default 2
  486. help
  487. This is the divider that is used to derive DUART clock from Platform
  488. clock, in another word DUART_clk = Platform_clk / this_divider.
  489. config SYS_FSL_I2C_CLK_DIV
  490. int "I2C clock divider"
  491. default 1 if ARCH_LS1043A
  492. default 4 if ARCH_LS1012A
  493. default 4 if ARCH_LS1028A
  494. default 8 if ARCH_LX2160A
  495. default 8 if ARCH_LX2162A
  496. default 8 if ARCH_LS1088A
  497. default 2
  498. help
  499. This is the divider that is used to derive I2C clock from Platform
  500. clock, in another word I2C_clk = Platform_clk / this_divider.
  501. config SYS_FSL_IFC_CLK_DIV
  502. int "IFC clock divider"
  503. default 1 if ARCH_LS1043A
  504. default 4 if ARCH_LS1012A
  505. default 4 if ARCH_LS1028A
  506. default 8 if ARCH_LX2160A
  507. default 8 if ARCH_LX2162A
  508. default 8 if ARCH_LS1088A
  509. default 2
  510. help
  511. This is the divider that is used to derive IFC clock from Platform
  512. clock, in another word IFC_clk = Platform_clk / this_divider.
  513. config SYS_FSL_LPUART_CLK_DIV
  514. int "LPUART clock divider"
  515. default 1 if ARCH_LS1043A
  516. default 2
  517. help
  518. This is the divider that is used to derive LPUART clock from Platform
  519. clock, in another word LPUART_clk = Platform_clk / this_divider.
  520. config SYS_FSL_SDHC_CLK_DIV
  521. int "SDHC clock divider"
  522. default 1 if ARCH_LS1043A
  523. default 1 if ARCH_LS1012A
  524. default 2
  525. help
  526. This is the divider that is used to derive SDHC clock from Platform
  527. clock, in another word SDHC_clk = Platform_clk / this_divider.
  528. config SYS_FSL_QMAN_CLK_DIV
  529. int "QMAN clock divider"
  530. default 1 if ARCH_LS1043A
  531. default 2
  532. help
  533. This is the divider that is used to derive QMAN clock from Platform
  534. clock, in another word QMAN_clk = Platform_clk / this_divider.
  535. endmenu
  536. config RESV_RAM
  537. bool
  538. help
  539. Reserve memory from the top, tracked by gd->arch.resv_ram. This
  540. reserved RAM can be used by special driver that resides in memory
  541. after U-Boot exits. It's up to implementation to allocate and allow
  542. access to this reserved memory. For example, the reserved RAM can
  543. be at the high end of physical memory. The reserve RAM may be
  544. excluded from memory bank(s) passed to OS, or marked as reserved.
  545. config SYS_FSL_EC1
  546. bool
  547. help
  548. Ethernet controller 1, this is connected to
  549. MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
  550. Provides DPAA2 capabilities
  551. config SYS_FSL_EC2
  552. bool
  553. help
  554. Ethernet controller 2, this is connected to
  555. MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
  556. Provides DPAA2 capabilities
  557. config SYS_FSL_ERRATUM_A008336
  558. bool
  559. config SYS_FSL_ERRATUM_A008514
  560. bool
  561. config SYS_FSL_ERRATUM_A008585
  562. bool
  563. config SYS_FSL_ERRATUM_A008850
  564. bool
  565. config SYS_FSL_ERRATUM_A009203
  566. bool
  567. config SYS_FSL_ERRATUM_A009635
  568. bool
  569. config SYS_FSL_ERRATUM_A009660
  570. bool
  571. config SYS_FSL_ERRATUM_A050382
  572. bool
  573. config SYS_FSL_HAS_RGMII
  574. bool
  575. depends on SYS_FSL_EC1 || SYS_FSL_EC2
  576. config SPL_LDSCRIPT
  577. default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
  578. config HAS_FSL_XHCI_USB
  579. bool
  580. help
  581. For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
  582. pins, select it when the pins are assigned to USB.
  583. config SYS_FSL_BOOTROM_BASE
  584. hex
  585. depends on FSL_LSCH2
  586. default 0
  587. config SYS_FSL_BOOTROM_SIZE
  588. hex
  589. depends on FSL_LSCH2
  590. default 0x1000000