am654_sdhci.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Texas Instruments' K3 SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <mmc.h>
  12. #include <power-domain.h>
  13. #include <regmap.h>
  14. #include <sdhci.h>
  15. #include <soc.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/err.h>
  19. /* CTL_CFG Registers */
  20. #define CTL_CFG_2 0x14
  21. #define SLOTTYPE_MASK GENMASK(31, 30)
  22. #define SLOTTYPE_EMBEDDED BIT(30)
  23. /* PHY Registers */
  24. #define PHY_CTRL1 0x100
  25. #define PHY_CTRL2 0x104
  26. #define PHY_CTRL3 0x108
  27. #define PHY_CTRL4 0x10C
  28. #define PHY_CTRL5 0x110
  29. #define PHY_CTRL6 0x114
  30. #define PHY_STAT1 0x130
  31. #define PHY_STAT2 0x134
  32. #define IOMUX_ENABLE_SHIFT 31
  33. #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
  34. #define OTAPDLYENA_SHIFT 20
  35. #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
  36. #define OTAPDLYSEL_SHIFT 12
  37. #define OTAPDLYSEL_MASK GENMASK(15, 12)
  38. #define STRBSEL_SHIFT 24
  39. #define STRBSEL_4BIT_MASK GENMASK(27, 24)
  40. #define STRBSEL_8BIT_MASK GENMASK(31, 24)
  41. #define SEL50_SHIFT 8
  42. #define SEL50_MASK BIT(SEL50_SHIFT)
  43. #define SEL100_SHIFT 9
  44. #define SEL100_MASK BIT(SEL100_SHIFT)
  45. #define FREQSEL_SHIFT 8
  46. #define FREQSEL_MASK GENMASK(10, 8)
  47. #define CLKBUFSEL_SHIFT 0
  48. #define CLKBUFSEL_MASK GENMASK(2, 0)
  49. #define DLL_TRIM_ICP_SHIFT 4
  50. #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
  51. #define DR_TY_SHIFT 20
  52. #define DR_TY_MASK GENMASK(22, 20)
  53. #define ENDLL_SHIFT 1
  54. #define ENDLL_MASK BIT(ENDLL_SHIFT)
  55. #define DLLRDY_SHIFT 0
  56. #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
  57. #define PDB_SHIFT 0
  58. #define PDB_MASK BIT(PDB_SHIFT)
  59. #define CALDONE_SHIFT 1
  60. #define CALDONE_MASK BIT(CALDONE_SHIFT)
  61. #define RETRIM_SHIFT 17
  62. #define RETRIM_MASK BIT(RETRIM_SHIFT)
  63. #define SELDLYTXCLK_SHIFT 17
  64. #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
  65. #define SELDLYRXCLK_SHIFT 16
  66. #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
  67. #define ITAPDLYSEL_SHIFT 0
  68. #define ITAPDLYSEL_MASK GENMASK(4, 0)
  69. #define ITAPDLYENA_SHIFT 8
  70. #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
  71. #define ITAPCHGWIN_SHIFT 9
  72. #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
  73. #define DRIVER_STRENGTH_50_OHM 0x0
  74. #define DRIVER_STRENGTH_33_OHM 0x1
  75. #define DRIVER_STRENGTH_66_OHM 0x2
  76. #define DRIVER_STRENGTH_100_OHM 0x3
  77. #define DRIVER_STRENGTH_40_OHM 0x4
  78. #define AM654_SDHCI_MIN_FREQ 400000
  79. #define CLOCK_TOO_SLOW_HZ 50000000
  80. struct am654_sdhci_plat {
  81. struct mmc_config cfg;
  82. struct mmc mmc;
  83. struct regmap *base;
  84. bool non_removable;
  85. u32 otap_del_sel[MMC_MODES_END];
  86. u32 itap_del_sel[MMC_MODES_END];
  87. u32 trm_icp;
  88. u32 drv_strength;
  89. u32 strb_sel;
  90. u32 clkbuf_sel;
  91. u32 flags;
  92. #define DLL_PRESENT BIT(0)
  93. #define IOMUX_PRESENT BIT(1)
  94. #define FREQSEL_2_BIT BIT(2)
  95. #define STRBSEL_4_BIT BIT(3)
  96. #define DLL_CALIB BIT(4)
  97. };
  98. struct timing_data {
  99. const char *otap_binding;
  100. const char *itap_binding;
  101. u32 capability;
  102. };
  103. static const struct timing_data td[] = {
  104. [MMC_LEGACY] = {"ti,otap-del-sel-legacy",
  105. "ti,itap-del-sel-legacy",
  106. 0},
  107. [MMC_HS] = {"ti,otap-del-sel-mmc-hs",
  108. "ti,itap-del-sel-mms-hs",
  109. MMC_CAP(MMC_HS)},
  110. [SD_HS] = {"ti,otap-del-sel-sd-hs",
  111. "ti,itap-del-sel-sd-hs",
  112. MMC_CAP(SD_HS)},
  113. [UHS_SDR12] = {"ti,otap-del-sel-sdr12",
  114. "ti,itap-del-sel-sdr12",
  115. MMC_CAP(UHS_SDR12)},
  116. [UHS_SDR25] = {"ti,otap-del-sel-sdr25",
  117. "ti,itap-del-sel-sdr25",
  118. MMC_CAP(UHS_SDR25)},
  119. [UHS_SDR50] = {"ti,otap-del-sel-sdr50",
  120. NULL,
  121. MMC_CAP(UHS_SDR50)},
  122. [UHS_SDR104] = {"ti,otap-del-sel-sdr104",
  123. NULL,
  124. MMC_CAP(UHS_SDR104)},
  125. [UHS_DDR50] = {"ti,otap-del-sel-ddr50",
  126. NULL,
  127. MMC_CAP(UHS_DDR50)},
  128. [MMC_DDR_52] = {"ti,otap-del-sel-ddr52",
  129. "ti,itap-del-sel-ddr52",
  130. MMC_CAP(MMC_DDR_52)},
  131. [MMC_HS_200] = {"ti,otap-del-sel-hs200",
  132. NULL,
  133. MMC_CAP(MMC_HS_200)},
  134. [MMC_HS_400] = {"ti,otap-del-sel-hs400",
  135. NULL,
  136. MMC_CAP(MMC_HS_400)},
  137. };
  138. struct am654_driver_data {
  139. const struct sdhci_ops *ops;
  140. u32 flags;
  141. };
  142. static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
  143. unsigned int speed)
  144. {
  145. int sel50, sel100, freqsel;
  146. u32 mask, val;
  147. int ret;
  148. /* Disable delay chain mode */
  149. regmap_update_bits(plat->base, PHY_CTRL5,
  150. SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
  151. if (plat->flags & FREQSEL_2_BIT) {
  152. switch (speed) {
  153. case 200000000:
  154. sel50 = 0;
  155. sel100 = 0;
  156. break;
  157. case 100000000:
  158. sel50 = 0;
  159. sel100 = 1;
  160. break;
  161. default:
  162. sel50 = 1;
  163. sel100 = 0;
  164. }
  165. /* Configure PHY DLL frequency */
  166. mask = SEL50_MASK | SEL100_MASK;
  167. val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
  168. regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
  169. } else {
  170. switch (speed) {
  171. case 200000000:
  172. freqsel = 0x0;
  173. break;
  174. default:
  175. freqsel = 0x4;
  176. }
  177. regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
  178. freqsel << FREQSEL_SHIFT);
  179. }
  180. /* Configure DLL TRIM */
  181. mask = DLL_TRIM_ICP_MASK;
  182. val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
  183. /* Configure DLL driver strength */
  184. mask |= DR_TY_MASK;
  185. val |= plat->drv_strength << DR_TY_SHIFT;
  186. regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
  187. /* Enable DLL */
  188. regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
  189. 0x1 << ENDLL_SHIFT);
  190. /*
  191. * Poll for DLL ready. Use a one second timeout.
  192. * Works in all experiments done so far
  193. */
  194. ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
  195. val & DLLRDY_MASK, 1000, 1000000);
  196. return ret;
  197. }
  198. static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat,
  199. u32 itapdly)
  200. {
  201. /* Set ITAPCHGWIN before writing to ITAPDLY */
  202. regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
  203. 1 << ITAPCHGWIN_SHIFT);
  204. regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYSEL_MASK,
  205. itapdly << ITAPDLYSEL_SHIFT);
  206. regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
  207. }
  208. static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat,
  209. int mode)
  210. {
  211. u32 mask, val;
  212. val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
  213. mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
  214. regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
  215. am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]);
  216. }
  217. static int am654_sdhci_set_ios_post(struct sdhci_host *host)
  218. {
  219. struct udevice *dev = host->mmc->dev;
  220. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  221. unsigned int speed = host->mmc->clock;
  222. int mode = host->mmc->selected_mode;
  223. u32 otap_del_sel;
  224. u32 mask, val;
  225. int ret;
  226. /* Reset SD Clock Enable */
  227. val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  228. val &= ~SDHCI_CLOCK_CARD_EN;
  229. sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
  230. regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
  231. /* restart clock */
  232. sdhci_set_clock(host->mmc, speed);
  233. /* switch phy back on */
  234. otap_del_sel = plat->otap_del_sel[mode];
  235. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  236. val = (1 << OTAPDLYENA_SHIFT) |
  237. (otap_del_sel << OTAPDLYSEL_SHIFT);
  238. /* Write to STRBSEL for HS400 speed mode */
  239. if (host->mmc->selected_mode == MMC_HS_400) {
  240. if (plat->flags & STRBSEL_4_BIT)
  241. mask |= STRBSEL_4BIT_MASK;
  242. else
  243. mask |= STRBSEL_8BIT_MASK;
  244. val |= plat->strb_sel << STRBSEL_SHIFT;
  245. }
  246. regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
  247. if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {
  248. ret = am654_sdhci_setup_dll(plat, speed);
  249. if (ret)
  250. return ret;
  251. } else {
  252. am654_sdhci_setup_delay_chain(plat, mode);
  253. }
  254. regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
  255. plat->clkbuf_sel);
  256. return 0;
  257. }
  258. int am654_sdhci_init(struct am654_sdhci_plat *plat)
  259. {
  260. u32 ctl_cfg_2 = 0;
  261. u32 mask, val;
  262. int ret;
  263. /* Reset OTAP to default value */
  264. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  265. regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
  266. if (plat->flags & DLL_CALIB) {
  267. regmap_read(plat->base, PHY_STAT1, &val);
  268. if (~val & CALDONE_MASK) {
  269. /* Calibrate IO lines */
  270. regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
  271. PDB_MASK);
  272. ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
  273. val, val & CALDONE_MASK,
  274. 1, 20);
  275. if (ret)
  276. return ret;
  277. }
  278. }
  279. /* Enable pins by setting IO mux to 0 */
  280. if (plat->flags & IOMUX_PRESENT)
  281. regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
  282. /* Set slot type based on SD or eMMC */
  283. if (plat->non_removable)
  284. ctl_cfg_2 = SLOTTYPE_EMBEDDED;
  285. regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
  286. return 0;
  287. }
  288. #define MAX_SDCD_DEBOUNCE_TIME 2000
  289. static int am654_sdhci_deferred_probe(struct sdhci_host *host)
  290. {
  291. struct udevice *dev = host->mmc->dev;
  292. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  293. unsigned long start;
  294. int val;
  295. /*
  296. * The controller takes about 1 second to debounce the card detect line
  297. * and doesn't let us power on until that time is up. Instead of waiting
  298. * for 1 second at every stage, poll on the CARD_PRESENT bit upto a
  299. * maximum of 2 seconds to be safe..
  300. */
  301. start = get_timer(0);
  302. do {
  303. if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
  304. return -ENOMEDIUM;
  305. val = mmc_getcd(host->mmc);
  306. } while (!val);
  307. am654_sdhci_init(plat);
  308. return sdhci_probe(dev);
  309. }
  310. static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
  311. {
  312. if (reg == SDHCI_HOST_CONTROL) {
  313. switch (host->mmc->selected_mode) {
  314. /*
  315. * According to the data manual, HISPD bit
  316. * should not be set in these speed modes.
  317. */
  318. case SD_HS:
  319. case MMC_HS:
  320. case UHS_SDR12:
  321. case UHS_SDR25:
  322. val &= ~SDHCI_CTRL_HISPD;
  323. default:
  324. break;
  325. }
  326. }
  327. writeb(val, host->ioaddr + reg);
  328. }
  329. #ifdef MMC_SUPPORTS_TUNING
  330. #define ITAP_MAX 32
  331. static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  332. {
  333. struct udevice *dev = mmc->dev;
  334. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  335. int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
  336. u32 itap;
  337. /* Enable ITAPDLY */
  338. regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
  339. 1 << ITAPDLYENA_SHIFT);
  340. for (itap = 0; itap < ITAP_MAX; itap++) {
  341. am654_sdhci_write_itapdly(plat, itap);
  342. cur_val = !mmc_send_tuning(mmc, opcode, NULL);
  343. if (cur_val && !prev_val)
  344. pass_window = itap;
  345. if (!cur_val)
  346. fail_len++;
  347. prev_val = cur_val;
  348. }
  349. /*
  350. * Having determined the length of the failing window and start of
  351. * the passing window calculate the length of the passing window and
  352. * set the final value halfway through it considering the range as a
  353. * circular buffer
  354. */
  355. pass_len = ITAP_MAX - fail_len;
  356. itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
  357. am654_sdhci_write_itapdly(plat, itap);
  358. return 0;
  359. }
  360. #endif
  361. const struct sdhci_ops am654_sdhci_ops = {
  362. #ifdef MMC_SUPPORTS_TUNING
  363. .platform_execute_tuning = am654_sdhci_execute_tuning,
  364. #endif
  365. .deferred_probe = am654_sdhci_deferred_probe,
  366. .set_ios_post = &am654_sdhci_set_ios_post,
  367. .set_control_reg = sdhci_set_control_reg,
  368. .write_b = am654_sdhci_write_b,
  369. };
  370. const struct am654_driver_data am654_drv_data = {
  371. .ops = &am654_sdhci_ops,
  372. .flags = DLL_PRESENT | IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT,
  373. };
  374. const struct am654_driver_data am654_sr1_drv_data = {
  375. .ops = &am654_sdhci_ops,
  376. .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
  377. STRBSEL_4_BIT,
  378. };
  379. const struct am654_driver_data j721e_8bit_drv_data = {
  380. .ops = &am654_sdhci_ops,
  381. .flags = DLL_PRESENT | DLL_CALIB,
  382. };
  383. static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
  384. {
  385. struct udevice *dev = host->mmc->dev;
  386. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  387. u32 otap_del_sel, mask, val;
  388. otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
  389. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  390. val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
  391. regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
  392. regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
  393. plat->clkbuf_sel);
  394. return 0;
  395. }
  396. const struct sdhci_ops j721e_4bit_sdhci_ops = {
  397. #ifdef MMC_SUPPORTS_TUNING
  398. .platform_execute_tuning = am654_sdhci_execute_tuning,
  399. #endif
  400. .deferred_probe = am654_sdhci_deferred_probe,
  401. .set_ios_post = &j721e_4bit_sdhci_set_ios_post,
  402. .set_control_reg = sdhci_set_control_reg,
  403. .write_b = am654_sdhci_write_b,
  404. };
  405. const struct am654_driver_data j721e_4bit_drv_data = {
  406. .ops = &j721e_4bit_sdhci_ops,
  407. .flags = IOMUX_PRESENT,
  408. };
  409. static const struct am654_driver_data sdhci_am64_8bit_drvdata = {
  410. .ops = &am654_sdhci_ops,
  411. .flags = DLL_PRESENT | DLL_CALIB,
  412. };
  413. static const struct am654_driver_data sdhci_am64_4bit_drvdata = {
  414. .ops = &j721e_4bit_sdhci_ops,
  415. .flags = IOMUX_PRESENT,
  416. };
  417. const struct soc_attr am654_sdhci_soc_attr[] = {
  418. { .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
  419. {/* sentinel */}
  420. };
  421. static int sdhci_am654_get_otap_delay(struct udevice *dev,
  422. struct mmc_config *cfg)
  423. {
  424. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  425. int ret;
  426. int i;
  427. /* ti,otap-del-sel-legacy is mandatory */
  428. ret = dev_read_u32(dev, "ti,otap-del-sel-legacy",
  429. &plat->otap_del_sel[0]);
  430. if (ret)
  431. return ret;
  432. /*
  433. * Remove the corresponding capability if an otap-del-sel
  434. * value is not found
  435. */
  436. for (i = MMC_HS; i <= MMC_HS_400; i++) {
  437. ret = dev_read_u32(dev, td[i].otap_binding,
  438. &plat->otap_del_sel[i]);
  439. if (ret) {
  440. dev_dbg(dev, "Couldn't find %s\n", td[i].otap_binding);
  441. /*
  442. * Remove the corresponding capability
  443. * if an otap-del-sel value is not found
  444. */
  445. cfg->host_caps &= ~td[i].capability;
  446. }
  447. if (td[i].itap_binding)
  448. dev_read_u32(dev, td[i].itap_binding,
  449. &plat->itap_del_sel[i]);
  450. }
  451. return 0;
  452. }
  453. static int am654_sdhci_probe(struct udevice *dev)
  454. {
  455. struct am654_driver_data *drv_data =
  456. (struct am654_driver_data *)dev_get_driver_data(dev);
  457. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  458. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  459. struct sdhci_host *host = dev_get_priv(dev);
  460. struct mmc_config *cfg = &plat->cfg;
  461. const struct soc_attr *soc;
  462. const struct am654_driver_data *soc_drv_data;
  463. struct clk clk;
  464. unsigned long clock;
  465. int ret;
  466. ret = clk_get_by_name(dev, "clk_xin", &clk);
  467. if (ret) {
  468. dev_err(dev, "failed to get clock\n");
  469. return ret;
  470. }
  471. clock = clk_get_rate(&clk);
  472. if (IS_ERR_VALUE(clock)) {
  473. dev_err(dev, "failed to get rate\n");
  474. return clock;
  475. }
  476. host->max_clk = clock;
  477. host->mmc = &plat->mmc;
  478. host->mmc->dev = dev;
  479. host->ops = drv_data->ops;
  480. ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
  481. AM654_SDHCI_MIN_FREQ);
  482. if (ret)
  483. return ret;
  484. ret = sdhci_am654_get_otap_delay(dev, cfg);
  485. if (ret)
  486. return ret;
  487. /* Update ops based on SoC revision */
  488. soc = soc_device_match(am654_sdhci_soc_attr);
  489. if (soc && soc->data) {
  490. soc_drv_data = soc->data;
  491. host->ops = soc_drv_data->ops;
  492. }
  493. host->mmc->priv = host;
  494. upriv->mmc = host->mmc;
  495. regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
  496. return 0;
  497. }
  498. static int am654_sdhci_of_to_plat(struct udevice *dev)
  499. {
  500. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  501. struct sdhci_host *host = dev_get_priv(dev);
  502. struct mmc_config *cfg = &plat->cfg;
  503. u32 drv_strength;
  504. int ret;
  505. host->name = dev->name;
  506. host->ioaddr = (void *)dev_read_addr(dev);
  507. plat->non_removable = dev_read_bool(dev, "non-removable");
  508. if (plat->flags & DLL_PRESENT) {
  509. ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
  510. if (ret)
  511. return ret;
  512. ret = dev_read_u32(dev, "ti,driver-strength-ohm",
  513. &drv_strength);
  514. if (ret)
  515. return ret;
  516. switch (drv_strength) {
  517. case 50:
  518. plat->drv_strength = DRIVER_STRENGTH_50_OHM;
  519. break;
  520. case 33:
  521. plat->drv_strength = DRIVER_STRENGTH_33_OHM;
  522. break;
  523. case 66:
  524. plat->drv_strength = DRIVER_STRENGTH_66_OHM;
  525. break;
  526. case 100:
  527. plat->drv_strength = DRIVER_STRENGTH_100_OHM;
  528. break;
  529. case 40:
  530. plat->drv_strength = DRIVER_STRENGTH_40_OHM;
  531. break;
  532. default:
  533. dev_err(dev, "Invalid driver strength\n");
  534. return -EINVAL;
  535. }
  536. }
  537. dev_read_u32(dev, "ti,strobe-sel", &plat->strb_sel);
  538. dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel);
  539. ret = mmc_of_parse(dev, cfg);
  540. if (ret)
  541. return ret;
  542. return 0;
  543. }
  544. static int am654_sdhci_bind(struct udevice *dev)
  545. {
  546. struct am654_driver_data *drv_data =
  547. (struct am654_driver_data *)dev_get_driver_data(dev);
  548. struct am654_sdhci_plat *plat = dev_get_plat(dev);
  549. const struct soc_attr *soc;
  550. const struct am654_driver_data *soc_drv_data;
  551. plat->flags = drv_data->flags;
  552. /* Update flags based on SoC revision */
  553. soc = soc_device_match(am654_sdhci_soc_attr);
  554. if (soc && soc->data) {
  555. soc_drv_data = soc->data;
  556. plat->flags = soc_drv_data->flags;
  557. }
  558. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  559. }
  560. static const struct udevice_id am654_sdhci_ids[] = {
  561. {
  562. .compatible = "ti,am654-sdhci-5.1",
  563. .data = (ulong)&am654_drv_data,
  564. },
  565. {
  566. .compatible = "ti,j721e-sdhci-8bit",
  567. .data = (ulong)&j721e_8bit_drv_data,
  568. },
  569. {
  570. .compatible = "ti,j721e-sdhci-4bit",
  571. .data = (ulong)&j721e_4bit_drv_data,
  572. },
  573. {
  574. .compatible = "ti,am64-sdhci-8bit",
  575. .data = (ulong)&sdhci_am64_8bit_drvdata,
  576. },
  577. {
  578. .compatible = "ti,am64-sdhci-4bit",
  579. .data = (ulong)&sdhci_am64_4bit_drvdata,
  580. },
  581. { }
  582. };
  583. U_BOOT_DRIVER(am654_sdhci_drv) = {
  584. .name = "am654_sdhci",
  585. .id = UCLASS_MMC,
  586. .of_match = am654_sdhci_ids,
  587. .of_to_plat = am654_sdhci_of_to_plat,
  588. .ops = &sdhci_ops,
  589. .bind = am654_sdhci_bind,
  590. .probe = am654_sdhci_probe,
  591. .priv_auto = sizeof(struct sdhci_host),
  592. .plat_auto = sizeof(struct am654_sdhci_plat),
  593. };