ks8851_mll.c 16 KB

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  1. /*
  2. * Micrel KS8851_MLL 16bit Network driver
  3. * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <asm/io.h>
  20. #include <common.h>
  21. #include <command.h>
  22. #include <malloc.h>
  23. #include <net.h>
  24. #include <miiphy.h>
  25. #include "ks8851_mll.h"
  26. #define DRIVERNAME "ks8851_mll"
  27. #define MAX_RECV_FRAMES 32
  28. #define MAX_BUF_SIZE 2048
  29. #define TX_BUF_SIZE 2000
  30. #define RX_BUF_SIZE 2000
  31. static const struct chip_id chip_ids[] = {
  32. {CIDER_ID, "KSZ8851"},
  33. {0, NULL},
  34. };
  35. /*
  36. * union ks_tx_hdr - tx header data
  37. * @txb: The header as bytes
  38. * @txw: The header as 16bit, little-endian words
  39. *
  40. * A dual representation of the tx header data to allow
  41. * access to individual bytes, and to allow 16bit accesses
  42. * with 16bit alignment.
  43. */
  44. union ks_tx_hdr {
  45. u8 txb[4];
  46. __le16 txw[2];
  47. };
  48. /*
  49. * struct ks_net - KS8851 driver private data
  50. * @net_device : The network device we're bound to
  51. * @txh : temporaly buffer to save status/length.
  52. * @frame_head_info : frame header information for multi-pkt rx.
  53. * @statelock : Lock on this structure for tx list.
  54. * @msg_enable : The message flags controlling driver output (see ethtool).
  55. * @frame_cnt : number of frames received.
  56. * @bus_width : i/o bus width.
  57. * @irq : irq number assigned to this device.
  58. * @rc_rxqcr : Cached copy of KS_RXQCR.
  59. * @rc_txcr : Cached copy of KS_TXCR.
  60. * @rc_ier : Cached copy of KS_IER.
  61. * @sharedbus : Multipex(addr and data bus) mode indicator.
  62. * @cmd_reg_cache : command register cached.
  63. * @cmd_reg_cache_int : command register cached. Used in the irq handler.
  64. * @promiscuous : promiscuous mode indicator.
  65. * @all_mcast : mutlicast indicator.
  66. * @mcast_lst_size : size of multicast list.
  67. * @mcast_lst : multicast list.
  68. * @mcast_bits : multicast enabed.
  69. * @mac_addr : MAC address assigned to this device.
  70. * @fid : frame id.
  71. * @extra_byte : number of extra byte prepended rx pkt.
  72. * @enabled : indicator this device works.
  73. */
  74. /* Receive multiplex framer header info */
  75. struct type_frame_head {
  76. u16 sts; /* Frame status */
  77. u16 len; /* Byte count */
  78. } fr_h_i[MAX_RECV_FRAMES];
  79. struct ks_net {
  80. struct net_device *netdev;
  81. union ks_tx_hdr txh;
  82. struct type_frame_head *frame_head_info;
  83. u32 msg_enable;
  84. u32 frame_cnt;
  85. int bus_width;
  86. int irq;
  87. u16 rc_rxqcr;
  88. u16 rc_txcr;
  89. u16 rc_ier;
  90. u16 sharedbus;
  91. u16 cmd_reg_cache;
  92. u16 cmd_reg_cache_int;
  93. u16 promiscuous;
  94. u16 all_mcast;
  95. u16 mcast_lst_size;
  96. u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
  97. u8 mcast_bits[HW_MCAST_SIZE];
  98. u8 mac_addr[6];
  99. u8 fid;
  100. u8 extra_byte;
  101. u8 enabled;
  102. } ks_str, *ks;
  103. #define BE3 0x8000 /* Byte Enable 3 */
  104. #define BE2 0x4000 /* Byte Enable 2 */
  105. #define BE1 0x2000 /* Byte Enable 1 */
  106. #define BE0 0x1000 /* Byte Enable 0 */
  107. static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
  108. {
  109. u8 shift_bit = offset & 0x03;
  110. u8 shift_data = (offset & 1) << 3;
  111. writew(offset | (BE0 << shift_bit), dev->iobase + 2);
  112. return (u8)(readw(dev->iobase) >> shift_data);
  113. }
  114. static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
  115. {
  116. writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
  117. return readw(dev->iobase);
  118. }
  119. static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val)
  120. {
  121. u8 shift_bit = (offset & 0x03);
  122. u16 value_write = (u16)(val << ((offset & 1) << 3));
  123. writew(offset | (BE0 << shift_bit), dev->iobase + 2);
  124. writew(value_write, dev->iobase);
  125. }
  126. static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
  127. {
  128. writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
  129. writew(val, dev->iobase);
  130. }
  131. /*
  132. * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
  133. * enabled.
  134. * @ks: The chip state
  135. * @wptr: buffer address to save data
  136. * @len: length in byte to read
  137. */
  138. static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
  139. {
  140. len >>= 1;
  141. while (len--)
  142. *wptr++ = readw(dev->iobase);
  143. }
  144. /*
  145. * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
  146. * @ks: The chip information
  147. * @wptr: buffer address
  148. * @len: length in byte to write
  149. */
  150. static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
  151. {
  152. len >>= 1;
  153. while (len--)
  154. writew(*wptr++, dev->iobase);
  155. }
  156. static void ks_enable_int(struct eth_device *dev)
  157. {
  158. ks_wrreg16(dev, KS_IER, ks->rc_ier);
  159. }
  160. static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
  161. {
  162. unsigned pmecr;
  163. ks_rdreg16(dev, KS_GRR);
  164. pmecr = ks_rdreg16(dev, KS_PMECR);
  165. pmecr &= ~PMECR_PM_MASK;
  166. pmecr |= pwrmode;
  167. ks_wrreg16(dev, KS_PMECR, pmecr);
  168. }
  169. /*
  170. * ks_read_config - read chip configuration of bus width.
  171. * @ks: The chip information
  172. */
  173. static void ks_read_config(struct eth_device *dev)
  174. {
  175. u16 reg_data = 0;
  176. /* Regardless of bus width, 8 bit read should always work. */
  177. reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
  178. reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
  179. /* addr/data bus are multiplexed */
  180. ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
  181. /*
  182. * There are garbage data when reading data from QMU,
  183. * depending on bus-width.
  184. */
  185. if (reg_data & CCR_8BIT) {
  186. ks->bus_width = ENUM_BUS_8BIT;
  187. ks->extra_byte = 1;
  188. } else if (reg_data & CCR_16BIT) {
  189. ks->bus_width = ENUM_BUS_16BIT;
  190. ks->extra_byte = 2;
  191. } else {
  192. ks->bus_width = ENUM_BUS_32BIT;
  193. ks->extra_byte = 4;
  194. }
  195. }
  196. /*
  197. * ks_soft_reset - issue one of the soft reset to the device
  198. * @ks: The device state.
  199. * @op: The bit(s) to set in the GRR
  200. *
  201. * Issue the relevant soft-reset command to the device's GRR register
  202. * specified by @op.
  203. *
  204. * Note, the delays are in there as a caution to ensure that the reset
  205. * has time to take effect and then complete. Since the datasheet does
  206. * not currently specify the exact sequence, we have chosen something
  207. * that seems to work with our device.
  208. */
  209. static void ks_soft_reset(struct eth_device *dev, unsigned op)
  210. {
  211. /* Disable interrupt first */
  212. ks_wrreg16(dev, KS_IER, 0x0000);
  213. ks_wrreg16(dev, KS_GRR, op);
  214. mdelay(10); /* wait a short time to effect reset */
  215. ks_wrreg16(dev, KS_GRR, 0);
  216. mdelay(1); /* wait for condition to clear */
  217. }
  218. void ks_enable_qmu(struct eth_device *dev)
  219. {
  220. u16 w;
  221. w = ks_rdreg16(dev, KS_TXCR);
  222. /* Enables QMU Transmit (TXCR). */
  223. ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
  224. /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
  225. w = ks_rdreg16(dev, KS_RXQCR);
  226. ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
  227. /* Enables QMU Receive (RXCR1). */
  228. w = ks_rdreg16(dev, KS_RXCR1);
  229. ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
  230. }
  231. static void ks_disable_qmu(struct eth_device *dev)
  232. {
  233. u16 w;
  234. w = ks_rdreg16(dev, KS_TXCR);
  235. /* Disables QMU Transmit (TXCR). */
  236. w &= ~TXCR_TXE;
  237. ks_wrreg16(dev, KS_TXCR, w);
  238. /* Disables QMU Receive (RXCR1). */
  239. w = ks_rdreg16(dev, KS_RXCR1);
  240. w &= ~RXCR1_RXE;
  241. ks_wrreg16(dev, KS_RXCR1, w);
  242. }
  243. static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
  244. {
  245. u32 r = ks->extra_byte & 0x1;
  246. u32 w = ks->extra_byte - r;
  247. /* 1. set sudo DMA mode */
  248. ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
  249. ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
  250. /*
  251. * 2. read prepend data
  252. *
  253. * read 4 + extra bytes and discard them.
  254. * extra bytes for dummy, 2 for status, 2 for len
  255. */
  256. if (r)
  257. ks_rdreg8(dev, 0);
  258. ks_inblk(dev, buf, w + 2 + 2);
  259. /* 3. read pkt data */
  260. ks_inblk(dev, buf, ALIGN(len, 4));
  261. /* 4. reset sudo DMA Mode */
  262. ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
  263. }
  264. static void ks_rcv(struct eth_device *dev, uchar **pv_data)
  265. {
  266. struct type_frame_head *frame_hdr = ks->frame_head_info;
  267. int i;
  268. ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
  269. /* read all header information */
  270. for (i = 0; i < ks->frame_cnt; i++) {
  271. /* Checking Received packet status */
  272. frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
  273. /* Get packet len from hardware */
  274. frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR);
  275. frame_hdr++;
  276. }
  277. frame_hdr = ks->frame_head_info;
  278. while (ks->frame_cnt--) {
  279. if ((frame_hdr->sts & RXFSHR_RXFV) &&
  280. (frame_hdr->len < RX_BUF_SIZE) &&
  281. frame_hdr->len) {
  282. /* read data block including CRC 4 bytes */
  283. ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len);
  284. /* NetRxPackets buffer size is ok (*pv_data pointer) */
  285. NetReceive(*pv_data, frame_hdr->len);
  286. pv_data++;
  287. } else {
  288. ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
  289. printf(DRIVERNAME ": bad packet\n");
  290. }
  291. frame_hdr++;
  292. }
  293. }
  294. /*
  295. * ks_read_selftest - read the selftest memory info.
  296. * @ks: The device state
  297. *
  298. * Read and check the TX/RX memory selftest information.
  299. */
  300. static int ks_read_selftest(struct eth_device *dev)
  301. {
  302. u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
  303. u16 mbir;
  304. int ret = 0;
  305. mbir = ks_rdreg16(dev, KS_MBIR);
  306. if ((mbir & both_done) != both_done) {
  307. printf(DRIVERNAME ": Memory selftest not finished\n");
  308. return 0;
  309. }
  310. if (mbir & MBIR_TXMBFA) {
  311. printf(DRIVERNAME ": TX memory selftest fails\n");
  312. ret |= 1;
  313. }
  314. if (mbir & MBIR_RXMBFA) {
  315. printf(DRIVERNAME ": RX memory selftest fails\n");
  316. ret |= 2;
  317. }
  318. debug(DRIVERNAME ": the selftest passes\n");
  319. return ret;
  320. }
  321. static void ks_setup(struct eth_device *dev)
  322. {
  323. u16 w;
  324. /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
  325. ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
  326. /* Setup Receive Frame Data Pointer Auto-Increment */
  327. ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
  328. /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
  329. ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
  330. /* Setup RxQ Command Control (RXQCR) */
  331. ks->rc_rxqcr = RXQCR_CMD_CNTL;
  332. ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);
  333. /*
  334. * set the force mode to half duplex, default is full duplex
  335. * because if the auto-negotiation fails, most switch uses
  336. * half-duplex.
  337. */
  338. w = ks_rdreg16(dev, KS_P1MBCR);
  339. w &= ~P1MBCR_FORCE_FDX;
  340. ks_wrreg16(dev, KS_P1MBCR, w);
  341. w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
  342. ks_wrreg16(dev, KS_TXCR, w);
  343. w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
  344. /* Normal mode */
  345. w |= RXCR1_RXPAFMA;
  346. ks_wrreg16(dev, KS_RXCR1, w);
  347. }
  348. static void ks_setup_int(struct eth_device *dev)
  349. {
  350. ks->rc_ier = 0x00;
  351. /* Clear the interrupts status of the hardware. */
  352. ks_wrreg16(dev, KS_ISR, 0xffff);
  353. /* Enables the interrupts of the hardware. */
  354. ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
  355. }
  356. static int ks8851_mll_detect_chip(struct eth_device *dev)
  357. {
  358. unsigned short val, i;
  359. ks_read_config(dev);
  360. val = ks_rdreg16(dev, KS_CIDER);
  361. if (val == 0xffff) {
  362. /* Special case -- no chip present */
  363. printf(DRIVERNAME ": is chip mounted ?\n");
  364. return -1;
  365. } else if ((val & 0xfff0) != CIDER_ID) {
  366. printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
  367. return -1;
  368. }
  369. debug("Read back KS8851 id 0x%x\n", val);
  370. /* only one entry in the table */
  371. val &= 0xfff0;
  372. for (i = 0; chip_ids[i].id != 0; i++) {
  373. if (chip_ids[i].id == val)
  374. break;
  375. }
  376. if (!chip_ids[i].id) {
  377. printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
  378. return -1;
  379. }
  380. dev->priv = (void *)&chip_ids[i];
  381. return 0;
  382. }
  383. static void ks8851_mll_reset(struct eth_device *dev)
  384. {
  385. /* wake up powermode to normal mode */
  386. ks_set_powermode(dev, PMECR_PM_NORMAL);
  387. mdelay(1); /* wait for normal mode to take effect */
  388. /* Disable interrupt and reset */
  389. ks_soft_reset(dev, GRR_GSR);
  390. /* turn off the IRQs and ack any outstanding */
  391. ks_wrreg16(dev, KS_IER, 0x0000);
  392. ks_wrreg16(dev, KS_ISR, 0xffff);
  393. /* shutdown RX/TX QMU */
  394. ks_disable_qmu(dev);
  395. }
  396. static void ks8851_mll_phy_configure(struct eth_device *dev)
  397. {
  398. u16 data;
  399. ks_setup(dev);
  400. ks_setup_int(dev);
  401. /* Probing the phy */
  402. data = ks_rdreg16(dev, KS_OBCR);
  403. ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
  404. debug(DRIVERNAME ": phy initialized\n");
  405. }
  406. static void ks8851_mll_enable(struct eth_device *dev)
  407. {
  408. ks_wrreg16(dev, KS_ISR, 0xffff);
  409. ks_enable_int(dev);
  410. ks_enable_qmu(dev);
  411. }
  412. static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
  413. {
  414. struct chip_id *id = dev->priv;
  415. debug(DRIVERNAME ": detected %s controller\n", id->name);
  416. if (ks_read_selftest(dev)) {
  417. printf(DRIVERNAME ": Selftest failed\n");
  418. return -1;
  419. }
  420. ks8851_mll_reset(dev);
  421. /* Configure the PHY, initialize the link state */
  422. ks8851_mll_phy_configure(dev);
  423. /* static allocation of private informations */
  424. ks->frame_head_info = fr_h_i;
  425. /* Turn on Tx + Rx */
  426. ks8851_mll_enable(dev);
  427. return 0;
  428. }
  429. static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
  430. {
  431. /* start header at txb[0] to align txw entries */
  432. ks->txh.txw[0] = 0;
  433. ks->txh.txw[1] = cpu_to_le16(len);
  434. /* 1. set sudo-DMA mode */
  435. ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
  436. ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
  437. /* 2. write status/lenth info */
  438. ks_outblk(dev, ks->txh.txw, 4);
  439. /* 3. write pkt data */
  440. ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
  441. /* 4. reset sudo-DMA mode */
  442. ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
  443. /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
  444. ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
  445. /* 6. wait until TXQCR_METFE is auto-cleared */
  446. do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
  447. }
  448. static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
  449. {
  450. u8 *data = (u8 *)packet;
  451. u16 tmplen = (u16)length;
  452. u16 retv;
  453. /*
  454. * Extra space are required:
  455. * 4 byte for alignment, 4 for status/length, 4 for CRC
  456. */
  457. retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
  458. if (retv >= tmplen + 12) {
  459. ks_write_qmu(dev, data, tmplen);
  460. return 0;
  461. } else {
  462. printf(DRIVERNAME ": failed to send packet: No buffer\n");
  463. return -1;
  464. }
  465. }
  466. static void ks8851_mll_halt(struct eth_device *dev)
  467. {
  468. ks8851_mll_reset(dev);
  469. }
  470. /*
  471. * Maximum receive ring size; that is, the number of packets
  472. * we can buffer before overflow happens. Basically, this just
  473. * needs to be enough to prevent a packet being discarded while
  474. * we are processing the previous one.
  475. */
  476. static int ks8851_mll_recv(struct eth_device *dev)
  477. {
  478. u16 status;
  479. status = ks_rdreg16(dev, KS_ISR);
  480. ks_wrreg16(dev, KS_ISR, status);
  481. if ((status & IRQ_RXI))
  482. ks_rcv(dev, (uchar **)NetRxPackets);
  483. if ((status & IRQ_LDI)) {
  484. u16 pmecr = ks_rdreg16(dev, KS_PMECR);
  485. pmecr &= ~PMECR_WKEVT_MASK;
  486. ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
  487. }
  488. return 0;
  489. }
  490. static int ks8851_mll_write_hwaddr(struct eth_device *dev)
  491. {
  492. u16 addrl, addrm, addrh;
  493. addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
  494. addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
  495. addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
  496. ks_wrreg16(dev, KS_MARH, addrh);
  497. ks_wrreg16(dev, KS_MARM, addrm);
  498. ks_wrreg16(dev, KS_MARL, addrl);
  499. return 0;
  500. }
  501. int ks8851_mll_initialize(u8 dev_num, int base_addr)
  502. {
  503. struct eth_device *dev;
  504. dev = malloc(sizeof(*dev));
  505. if (!dev) {
  506. printf("Error: Failed to allocate memory\n");
  507. return -1;
  508. }
  509. memset(dev, 0, sizeof(*dev));
  510. dev->iobase = base_addr;
  511. ks = &ks_str;
  512. /* Try to detect chip. Will fail if not present. */
  513. if (ks8851_mll_detect_chip(dev)) {
  514. free(dev);
  515. return -1;
  516. }
  517. dev->init = ks8851_mll_init;
  518. dev->halt = ks8851_mll_halt;
  519. dev->send = ks8851_mll_send;
  520. dev->recv = ks8851_mll_recv;
  521. dev->write_hwaddr = ks8851_mll_write_hwaddr;
  522. sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
  523. eth_register(dev);
  524. return 0;
  525. }