board.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Birdland Audio BAV335x Network Processor
  6. *
  7. * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <serial.h>
  15. #include <spl.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/omap.h>
  19. #include <asm/arch/ddr_defs.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/mmc_host_def.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/arch/mem.h>
  25. #include <asm/io.h>
  26. #include <asm/emif.h>
  27. #include <asm/gpio.h>
  28. #include <i2c.h>
  29. #include <miiphy.h>
  30. #include <cpsw.h>
  31. #include <power/tps65217.h>
  32. #include <power/tps65910.h>
  33. #include <env_internal.h>
  34. #include <watchdog.h>
  35. #include "board.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. /* GPIO that controls power to DDR on EVM-SK */
  38. #define GPIO_DDR_VTT_EN 7
  39. static __maybe_unused struct ctrl_dev *cdev =
  40. (struct ctrl_dev *)CTRL_DEVICE_BASE;
  41. /*
  42. * Read header information from EEPROM into global structure.
  43. */
  44. static int read_eeprom(struct board_eeconfig *header)
  45. {
  46. /* Check if baseboard eeprom is available */
  47. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
  48. return -ENODEV;
  49. /* read the eeprom using i2c */
  50. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  51. sizeof(struct board_eeconfig)))
  52. return -EIO;
  53. if (header->magic != BOARD_MAGIC) {
  54. /* read the i2c eeprom again using only a 1 byte address */
  55. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  56. sizeof(struct board_eeconfig)))
  57. return -EIO;
  58. if (header->magic != BOARD_MAGIC)
  59. return -EINVAL;
  60. }
  61. return 0;
  62. }
  63. enum board_type get_board_type(bool debug)
  64. {
  65. int ecode;
  66. struct board_eeconfig header;
  67. ecode = read_eeprom(&header);
  68. if (ecode == 0) {
  69. if (header.version[1] == 'A') {
  70. if (debug)
  71. puts("=== Detected Board model BAV335x Rev.A");
  72. return BAV335A;
  73. } else if (header.version[1] == 'B') {
  74. if (debug)
  75. puts("=== Detected Board model BAV335x Rev.B");
  76. return BAV335B;
  77. } else if (debug) {
  78. puts("### Un-known board model in serial-EE\n");
  79. }
  80. } else if (debug) {
  81. switch (ecode) {
  82. case -ENODEV:
  83. puts("### Board doesn't have a serial-EE\n");
  84. break;
  85. case -EINVAL:
  86. puts("### Board serial-EE signature is incorrect.\n");
  87. break;
  88. default:
  89. puts("### IO Error reading serial-EE.\n");
  90. break;
  91. }
  92. }
  93. #if (CONFIG_BAV_VERSION == 1)
  94. if (debug)
  95. puts("### Selecting BAV335A as per config\n");
  96. return BAV335A;
  97. #elif (CONFIG_BAV_VERSION == 2)
  98. if (debug)
  99. puts("### Selecting BAV335B as per config\n");
  100. return BAV335B;
  101. #endif
  102. #if (NOT_DEFINED == 2)
  103. #error "SHOULD NEVER DISPLAY THIS"
  104. #endif
  105. if (debug)
  106. puts("### Defaulting to model BAV335x Rev.B\n");
  107. return BAV335B;
  108. }
  109. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  110. static const struct ddr_data ddr3_bav335x_data = {
  111. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  112. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  113. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  114. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  115. };
  116. static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
  117. .cmd0csratio = MT41K256M16HA125E_RATIO,
  118. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  119. .cmd1csratio = MT41K256M16HA125E_RATIO,
  120. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  121. .cmd2csratio = MT41K256M16HA125E_RATIO,
  122. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  123. };
  124. static struct emif_regs ddr3_bav335x_emif_reg_data = {
  125. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  126. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  127. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  128. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  129. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  130. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  131. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  132. };
  133. #ifdef CONFIG_SPL_OS_BOOT
  134. int spl_start_uboot(void)
  135. {
  136. /* break into full u-boot on 'c' */
  137. if (serial_tstc() && serial_getc() == 'c')
  138. return 1;
  139. #ifdef CONFIG_SPL_ENV_SUPPORT
  140. env_init();
  141. env_load();
  142. if (env_get_yesno("boot_os") != 1)
  143. return 1;
  144. #endif
  145. return 0;
  146. }
  147. #endif
  148. #define OSC (V_OSCK/1000000)
  149. const struct dpll_params dpll_ddr = {
  150. 266, OSC-1, 1, -1, -1, -1, -1};
  151. const struct dpll_params dpll_ddr_evm_sk = {
  152. 303, OSC-1, 1, -1, -1, -1, -1};
  153. const struct dpll_params dpll_ddr_bone_black = {
  154. 400, OSC-1, 1, -1, -1, -1, -1};
  155. void am33xx_spl_board_init(void)
  156. {
  157. /* debug print detect status */
  158. (void)get_board_type(true);
  159. /* Get the frequency */
  160. /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
  161. dpll_mpu_opp100.m = MPUPLL_M_1000;
  162. if (i2c_probe(TPS65217_CHIP_PM))
  163. return;
  164. /* Set the USB Current Limit */
  165. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
  166. TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
  167. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  168. puts("! tps65217_reg_write: could not set USB limit\n");
  169. /* Set the Core Voltage (DCDC3) to 1.125V */
  170. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  171. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  172. puts("! tps65217_reg_write: could not set Core Voltage\n");
  173. return;
  174. }
  175. /* Set CORE Frequencies to OPP100 */
  176. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  177. /* Set the MPU Voltage (DCDC2) */
  178. if (tps65217_voltage_update(TPS65217_DEFDCDC2,
  179. TPS65217_DCDC_VOLT_SEL_1325MV)) {
  180. puts("! tps65217_reg_write: could not set MPU Voltage\n");
  181. return;
  182. }
  183. /*
  184. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  185. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  186. */
  187. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
  188. TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
  189. puts("! tps65217_reg_write: could not set LDO3\n");
  190. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
  191. TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
  192. puts("! tps65217_reg_write: could not set LDO4\n");
  193. /* Set MPU Frequency to what we detected now that voltages are set */
  194. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  195. }
  196. const struct dpll_params *get_dpll_ddr_params(void)
  197. {
  198. enable_i2c0_pin_mux();
  199. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  200. return &dpll_ddr_bone_black;
  201. }
  202. void set_uart_mux_conf(void)
  203. {
  204. #if CONFIG_CONS_INDEX == 1
  205. enable_uart0_pin_mux();
  206. #elif CONFIG_CONS_INDEX == 2
  207. enable_uart1_pin_mux();
  208. #elif CONFIG_CONS_INDEX == 3
  209. enable_uart2_pin_mux();
  210. #elif CONFIG_CONS_INDEX == 4
  211. enable_uart3_pin_mux();
  212. #elif CONFIG_CONS_INDEX == 5
  213. enable_uart4_pin_mux();
  214. #elif CONFIG_CONS_INDEX == 6
  215. enable_uart5_pin_mux();
  216. #endif
  217. }
  218. void set_mux_conf_regs(void)
  219. {
  220. enum board_type board;
  221. board = get_board_type(false);
  222. enable_board_pin_mux(board);
  223. }
  224. const struct ctrl_ioregs ioregs_bonelt = {
  225. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  226. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  227. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  228. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  229. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  230. };
  231. void sdram_init(void)
  232. {
  233. config_ddr(400, &ioregs_bonelt,
  234. &ddr3_bav335x_data,
  235. &ddr3_bav335x_cmd_ctrl_data,
  236. &ddr3_bav335x_emif_reg_data, 0);
  237. }
  238. #endif
  239. /*
  240. * Basic board specific setup. Pinmux has been handled already.
  241. */
  242. int board_init(void)
  243. {
  244. #if defined(CONFIG_HW_WATCHDOG)
  245. hw_watchdog_init();
  246. #endif
  247. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  248. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  249. gpmc_init();
  250. #endif
  251. return 0;
  252. }
  253. #ifdef CONFIG_BOARD_LATE_INIT
  254. int board_late_init(void)
  255. {
  256. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  257. env_set("board_name", "BAV335xB");
  258. env_set("board_rev", "B"); /* Fix me, but why bother.. */
  259. #endif
  260. return 0;
  261. }
  262. #endif
  263. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  264. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  265. static void cpsw_control(int enabled)
  266. {
  267. /* VTP can be added here */
  268. return;
  269. }
  270. static struct cpsw_slave_data cpsw_slaves[] = {
  271. {
  272. .slave_reg_ofs = 0x208,
  273. .sliver_reg_ofs = 0xd80,
  274. .phy_addr = 0,
  275. },
  276. {
  277. .slave_reg_ofs = 0x308,
  278. .sliver_reg_ofs = 0xdc0,
  279. .phy_addr = 1,
  280. },
  281. };
  282. static struct cpsw_platform_data cpsw_data = {
  283. .mdio_base = CPSW_MDIO_BASE,
  284. .cpsw_base = CPSW_BASE,
  285. .mdio_div = 0xff,
  286. .channels = 8,
  287. .cpdma_reg_ofs = 0x800,
  288. .slaves = 1,
  289. .slave_data = cpsw_slaves,
  290. .ale_reg_ofs = 0xd00,
  291. .ale_entries = 1024,
  292. .host_port_reg_ofs = 0x108,
  293. .hw_stats_reg_ofs = 0x900,
  294. .bd_ram_ofs = 0x2000,
  295. .mac_control = (1 << 5),
  296. .control = cpsw_control,
  297. .host_port_num = 0,
  298. .version = CPSW_CTRL_VERSION_2,
  299. };
  300. #endif
  301. /*
  302. * This function will:
  303. * Perform fixups to the PHY present on certain boards. We only need this
  304. * function in:
  305. * - SPL with either CPSW or USB ethernet support
  306. * - Full U-Boot, with either CPSW or USB ethernet
  307. * Build in only these cases to avoid warnings about unused variables
  308. * when we build an SPL that has neither option but full U-Boot will.
  309. */
  310. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
  311. defined(CONFIG_SPL_BUILD)) || \
  312. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  313. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  314. !defined(CONFIG_SPL_BUILD))
  315. int board_eth_init(bd_t *bis)
  316. {
  317. int ecode, rv, n;
  318. uint8_t mac_addr[6];
  319. struct board_eeconfig header;
  320. __maybe_unused enum board_type board;
  321. /* Default manufacturing address; used when no EE or invalid */
  322. n = 0;
  323. mac_addr[0] = 0;
  324. mac_addr[1] = 0x20;
  325. mac_addr[2] = 0x18;
  326. mac_addr[3] = 0x1C;
  327. mac_addr[4] = 0x00;
  328. mac_addr[5] = 0x01;
  329. ecode = read_eeprom(&header);
  330. /* if we have a valid EE, get mac address from there */
  331. if ((ecode == 0) &&
  332. is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
  333. memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
  334. }
  335. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  336. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  337. if (!env_get("ethaddr")) {
  338. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  339. if (is_valid_ethaddr(mac_addr))
  340. eth_env_set_enetaddr("ethaddr", mac_addr);
  341. }
  342. #ifdef CONFIG_DRIVER_TI_CPSW
  343. board = get_board_type(false);
  344. /* Rev.A uses 10/100 PHY in mii mode */
  345. if (board == BAV335A) {
  346. writel(MII_MODE_ENABLE, &cdev->miisel);
  347. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
  348. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
  349. }
  350. /* Rev.B (default) uses GB PHY in rmii mode */
  351. else {
  352. writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
  353. cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
  354. = PHY_INTERFACE_MODE_RGMII;
  355. }
  356. rv = cpsw_register(&cpsw_data);
  357. if (rv < 0)
  358. printf("Error %d registering CPSW switch\n", rv);
  359. else
  360. n += rv;
  361. #endif
  362. #endif
  363. return n;
  364. }
  365. #endif