clk_zynqmp.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ZynqMP clock driver
  4. *
  5. * Copyright (C) 2016 Xilinx, Inc.
  6. */
  7. #include <common.h>
  8. #include <linux/bitops.h>
  9. #include <clk-uclass.h>
  10. #include <clk.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <dm.h>
  13. static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
  14. static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
  15. /* Full power domain clocks */
  16. #define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
  17. #define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
  18. #define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
  19. #define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
  20. #define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
  21. #define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
  22. #define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
  23. /* Peripheral clocks */
  24. #define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
  25. #define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
  26. #define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
  27. #define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
  28. #define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
  29. #define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
  30. #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
  31. #define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
  32. #define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
  33. #define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
  34. #define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
  35. #define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
  36. #define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
  37. #define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
  38. #define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
  39. #define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
  40. /* Low power domain clocks */
  41. #define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
  42. #define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
  43. #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
  44. #define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
  45. #define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
  46. /* Peripheral clocks */
  47. #define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
  48. #define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
  49. #define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
  50. #define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
  51. #define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
  52. #define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
  53. #define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
  54. #define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
  55. #define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
  56. #define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
  57. #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
  58. #define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
  59. #define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
  60. #define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
  61. #define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
  62. #define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
  63. #define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
  64. #define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
  65. #define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
  66. #define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
  67. #define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
  68. #define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
  69. #define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
  70. #define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
  71. #define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
  72. #define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
  73. #define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
  74. #define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
  75. #define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
  76. #define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
  77. #define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
  78. #define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
  79. #define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
  80. #define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
  81. #define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
  82. #define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
  83. #define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
  84. #define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
  85. #define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
  86. #define ZYNQ_CLK_MAXDIV 0x3f
  87. #define CLK_CTRL_DIV1_SHIFT 16
  88. #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  89. #define CLK_CTRL_DIV0_SHIFT 8
  90. #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  91. #define CLK_CTRL_SRCSEL_SHIFT 0
  92. #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
  93. #define PLLCTRL_FBDIV_MASK 0x7f00
  94. #define PLLCTRL_FBDIV_SHIFT 8
  95. #define PLLCTRL_RESET_MASK 1
  96. #define PLLCTRL_RESET_SHIFT 0
  97. #define PLLCTRL_BYPASS_MASK 0x8
  98. #define PLLCTRL_BYPASS_SHFT 3
  99. #define PLLCTRL_POST_SRC_SHFT 24
  100. #define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
  101. #define NUM_MIO_PINS 77
  102. enum zynqmp_clk {
  103. iopll, rpll,
  104. apll, dpll, vpll,
  105. iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
  106. acpu, acpu_half,
  107. dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
  108. dp_video_ref, dp_audio_ref,
  109. dp_stc_ref, gdma_ref, dpdma_ref,
  110. ddr_ref, sata_ref, pcie_ref,
  111. gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
  112. topsw_main, topsw_lsbus,
  113. gtgref0_ref,
  114. lpd_switch, lpd_lsbus,
  115. usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
  116. cpu_r5, cpu_r5_core,
  117. csu_spb, csu_pll, pcap,
  118. iou_switch,
  119. gem_tsu_ref, gem_tsu,
  120. gem0_ref, gem1_ref, gem2_ref, gem3_ref,
  121. gem0_rx, gem1_rx, gem2_rx, gem3_rx,
  122. qspi_ref,
  123. sdio0_ref, sdio1_ref,
  124. uart0_ref, uart1_ref,
  125. spi0_ref, spi1_ref,
  126. nand_ref,
  127. i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
  128. dll_ref,
  129. adma_ref,
  130. timestamp_ref,
  131. ams_ref,
  132. pl0, pl1, pl2, pl3,
  133. wdt,
  134. clk_max,
  135. };
  136. static const char * const clk_names[clk_max] = {
  137. "iopll", "rpll", "apll", "dpll",
  138. "vpll", "iopll_to_fpd", "rpll_to_fpd",
  139. "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
  140. "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
  141. "dbg_trace", "dbg_tstmp", "dp_video_ref",
  142. "dp_audio_ref", "dp_stc_ref", "gdma_ref",
  143. "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
  144. "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
  145. "topsw_main", "topsw_lsbus", "gtgref0_ref",
  146. "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
  147. "usb1_bus_ref", "usb3_dual_ref", "usb0",
  148. "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
  149. "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
  150. "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
  151. "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
  152. "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
  153. "uart0_ref", "uart1_ref", "spi0_ref",
  154. "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
  155. "can0_ref", "can1_ref", "can0", "can1",
  156. "dll_ref", "adma_ref", "timestamp_ref",
  157. "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
  158. };
  159. struct zynqmp_clk_priv {
  160. unsigned long ps_clk_freq;
  161. unsigned long video_clk;
  162. unsigned long pss_alt_ref_clk;
  163. unsigned long gt_crx_ref_clk;
  164. unsigned long aux_ref_clk;
  165. };
  166. static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
  167. {
  168. switch (id) {
  169. case iopll:
  170. return CRL_APB_IOPLL_CTRL;
  171. case rpll:
  172. return CRL_APB_RPLL_CTRL;
  173. case apll:
  174. return CRF_APB_APLL_CTRL;
  175. case dpll:
  176. return CRF_APB_DPLL_CTRL;
  177. case vpll:
  178. return CRF_APB_VPLL_CTRL;
  179. case acpu:
  180. return CRF_APB_ACPU_CTRL;
  181. case ddr_ref:
  182. return CRF_APB_DDR_CTRL;
  183. case qspi_ref:
  184. return CRL_APB_QSPI_REF_CTRL;
  185. case gem0_ref:
  186. return CRL_APB_GEM0_REF_CTRL;
  187. case gem1_ref:
  188. return CRL_APB_GEM1_REF_CTRL;
  189. case gem2_ref:
  190. return CRL_APB_GEM2_REF_CTRL;
  191. case gem3_ref:
  192. return CRL_APB_GEM3_REF_CTRL;
  193. case uart0_ref:
  194. return CRL_APB_UART0_REF_CTRL;
  195. case uart1_ref:
  196. return CRL_APB_UART1_REF_CTRL;
  197. case sdio0_ref:
  198. return CRL_APB_SDIO0_REF_CTRL;
  199. case sdio1_ref:
  200. return CRL_APB_SDIO1_REF_CTRL;
  201. case spi0_ref:
  202. return CRL_APB_SPI0_REF_CTRL;
  203. case spi1_ref:
  204. return CRL_APB_SPI1_REF_CTRL;
  205. case nand_ref:
  206. return CRL_APB_NAND_REF_CTRL;
  207. case i2c0_ref:
  208. return CRL_APB_I2C0_REF_CTRL;
  209. case i2c1_ref:
  210. return CRL_APB_I2C1_REF_CTRL;
  211. case can0_ref:
  212. return CRL_APB_CAN0_REF_CTRL;
  213. case can1_ref:
  214. return CRL_APB_CAN1_REF_CTRL;
  215. case pl0:
  216. return CRL_APB_PL0_REF_CTRL;
  217. case pl1:
  218. return CRL_APB_PL1_REF_CTRL;
  219. case pl2:
  220. return CRL_APB_PL2_REF_CTRL;
  221. case pl3:
  222. return CRL_APB_PL3_REF_CTRL;
  223. case wdt:
  224. return CRF_APB_TOPSW_LSBUS_CTRL;
  225. case iopll_to_fpd:
  226. return CRL_APB_IOPLL_TO_FPD_CTRL;
  227. default:
  228. debug("Invalid clk id%d\n", id);
  229. }
  230. return 0;
  231. }
  232. static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
  233. {
  234. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  235. CLK_CTRL_SRCSEL_SHIFT;
  236. switch (srcsel) {
  237. case 2:
  238. return dpll;
  239. case 3:
  240. return vpll;
  241. case 0 ... 1:
  242. default:
  243. return apll;
  244. }
  245. }
  246. static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
  247. {
  248. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  249. CLK_CTRL_SRCSEL_SHIFT;
  250. switch (srcsel) {
  251. case 1:
  252. return vpll;
  253. case 0:
  254. default:
  255. return dpll;
  256. }
  257. }
  258. static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
  259. {
  260. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  261. CLK_CTRL_SRCSEL_SHIFT;
  262. switch (srcsel) {
  263. case 2:
  264. return rpll;
  265. case 3:
  266. return dpll;
  267. case 0 ... 1:
  268. default:
  269. return iopll;
  270. }
  271. }
  272. static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
  273. {
  274. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  275. CLK_CTRL_SRCSEL_SHIFT;
  276. switch (srcsel) {
  277. case 2:
  278. return iopll_to_fpd;
  279. case 3:
  280. return dpll;
  281. case 0 ... 1:
  282. default:
  283. return apll;
  284. }
  285. }
  286. static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
  287. struct zynqmp_clk_priv *priv,
  288. bool is_pre_src)
  289. {
  290. u32 src_sel;
  291. if (is_pre_src)
  292. src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
  293. PLLCTRL_POST_SRC_SHFT;
  294. else
  295. src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
  296. PLLCTRL_POST_SRC_SHFT;
  297. switch (src_sel) {
  298. case 4:
  299. return priv->video_clk;
  300. case 5:
  301. return priv->pss_alt_ref_clk;
  302. case 6:
  303. return priv->aux_ref_clk;
  304. case 7:
  305. return priv->gt_crx_ref_clk;
  306. case 0 ... 3:
  307. default:
  308. return priv->ps_clk_freq;
  309. }
  310. }
  311. static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
  312. enum zynqmp_clk id)
  313. {
  314. u32 clk_ctrl, reset, mul;
  315. ulong freq;
  316. int ret;
  317. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  318. if (ret) {
  319. printf("%s mio read fail\n", __func__);
  320. return -EIO;
  321. }
  322. if (clk_ctrl & PLLCTRL_BYPASS_MASK)
  323. freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
  324. else
  325. freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
  326. reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
  327. if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
  328. return 0;
  329. mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
  330. freq *= mul;
  331. if (clk_ctrl & (1 << 16))
  332. freq /= 2;
  333. return freq;
  334. }
  335. static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
  336. enum zynqmp_clk id)
  337. {
  338. u32 clk_ctrl, div;
  339. enum zynqmp_clk pll;
  340. int ret;
  341. unsigned long pllrate;
  342. ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
  343. if (ret) {
  344. printf("%s mio read fail\n", __func__);
  345. return -EIO;
  346. }
  347. div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  348. pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
  349. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  350. if (IS_ERR_VALUE(pllrate))
  351. return pllrate;
  352. return DIV_ROUND_CLOSEST(pllrate, div);
  353. }
  354. static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
  355. {
  356. u32 clk_ctrl, div;
  357. enum zynqmp_clk pll;
  358. int ret;
  359. ulong pllrate;
  360. ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
  361. if (ret) {
  362. printf("%s mio read fail\n", __func__);
  363. return -EIO;
  364. }
  365. div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  366. pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
  367. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  368. if (IS_ERR_VALUE(pllrate))
  369. return pllrate;
  370. return DIV_ROUND_CLOSEST(pllrate, div);
  371. }
  372. static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
  373. enum zynqmp_clk id, bool two_divs)
  374. {
  375. enum zynqmp_clk pll;
  376. u32 clk_ctrl, div0;
  377. u32 div1 = 1;
  378. int ret;
  379. ulong pllrate;
  380. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  381. if (ret) {
  382. printf("%s mio read fail\n", __func__);
  383. return -EIO;
  384. }
  385. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  386. if (!div0)
  387. div0 = 1;
  388. if (two_divs) {
  389. div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
  390. if (!div1)
  391. div1 = 1;
  392. }
  393. pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
  394. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  395. if (IS_ERR_VALUE(pllrate))
  396. return pllrate;
  397. return
  398. DIV_ROUND_CLOSEST(
  399. DIV_ROUND_CLOSEST(pllrate, div0), div1);
  400. }
  401. static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
  402. enum zynqmp_clk id, bool two_divs)
  403. {
  404. enum zynqmp_clk pll;
  405. u32 clk_ctrl, div0;
  406. u32 div1 = 1;
  407. int ret;
  408. ulong pllrate;
  409. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  410. if (ret) {
  411. printf("%d %s mio read fail\n", __LINE__, __func__);
  412. return -EIO;
  413. }
  414. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  415. if (!div0)
  416. div0 = 1;
  417. pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
  418. if (two_divs) {
  419. ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
  420. if (ret) {
  421. printf("%d %s mio read fail\n", __LINE__, __func__);
  422. return -EIO;
  423. }
  424. div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  425. if (!div1)
  426. div1 = 1;
  427. }
  428. if (pll == iopll_to_fpd)
  429. pll = iopll;
  430. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  431. if (IS_ERR_VALUE(pllrate))
  432. return pllrate;
  433. return
  434. DIV_ROUND_CLOSEST(
  435. DIV_ROUND_CLOSEST(pllrate, div0), div1);
  436. }
  437. static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
  438. ulong pll_rate,
  439. u32 *div0, u32 *div1)
  440. {
  441. long new_err, best_err = (long)(~0UL >> 1);
  442. ulong new_rate, best_rate = 0;
  443. u32 d0, d1;
  444. for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
  445. for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
  446. new_rate = DIV_ROUND_CLOSEST(
  447. DIV_ROUND_CLOSEST(pll_rate, d0), d1);
  448. new_err = abs(new_rate - rate);
  449. if (new_err < best_err) {
  450. *div0 = d0;
  451. *div1 = d1;
  452. best_err = new_err;
  453. best_rate = new_rate;
  454. }
  455. }
  456. }
  457. return best_rate;
  458. }
  459. static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
  460. enum zynqmp_clk id, ulong rate,
  461. bool two_divs)
  462. {
  463. enum zynqmp_clk pll;
  464. u32 clk_ctrl, div0 = 0, div1 = 0;
  465. ulong pll_rate, new_rate;
  466. u32 reg;
  467. int ret;
  468. u32 mask;
  469. reg = zynqmp_clk_get_register(id);
  470. ret = zynqmp_mmio_read(reg, &clk_ctrl);
  471. if (ret) {
  472. printf("%s mio read fail\n", __func__);
  473. return -EIO;
  474. }
  475. pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
  476. pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
  477. if (IS_ERR_VALUE(pll_rate))
  478. return pll_rate;
  479. clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
  480. if (two_divs) {
  481. clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
  482. new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
  483. &div0, &div1);
  484. clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
  485. } else {
  486. div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
  487. if (div0 > ZYNQ_CLK_MAXDIV)
  488. div0 = ZYNQ_CLK_MAXDIV;
  489. new_rate = DIV_ROUND_CLOSEST(rate, div0);
  490. }
  491. clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
  492. mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
  493. (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
  494. ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
  495. if (ret) {
  496. printf("%s mio write fail\n", __func__);
  497. return -EIO;
  498. }
  499. return new_rate;
  500. }
  501. static ulong zynqmp_clk_get_rate(struct clk *clk)
  502. {
  503. struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
  504. enum zynqmp_clk id = clk->id;
  505. bool two_divs = false;
  506. switch (id) {
  507. case iopll ... vpll:
  508. return zynqmp_clk_get_pll_rate(priv, id);
  509. case acpu:
  510. return zynqmp_clk_get_cpu_rate(priv, id);
  511. case ddr_ref:
  512. return zynqmp_clk_get_ddr_rate(priv);
  513. case gem0_ref ... gem3_ref:
  514. case qspi_ref ... can1_ref:
  515. case pl0 ... pl3:
  516. two_divs = true;
  517. return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
  518. case wdt:
  519. two_divs = true;
  520. return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
  521. default:
  522. return -ENXIO;
  523. }
  524. }
  525. static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
  526. {
  527. struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
  528. enum zynqmp_clk id = clk->id;
  529. bool two_divs = true;
  530. switch (id) {
  531. case gem0_ref ... gem3_ref:
  532. case qspi_ref ... can1_ref:
  533. return zynqmp_clk_set_peripheral_rate(priv, id,
  534. rate, two_divs);
  535. default:
  536. return -ENXIO;
  537. }
  538. }
  539. int soc_clk_dump(void)
  540. {
  541. struct udevice *dev;
  542. int i, ret;
  543. ret = uclass_get_device_by_driver(UCLASS_CLK,
  544. DM_GET_DRIVER(zynqmp_clk), &dev);
  545. if (ret)
  546. return ret;
  547. printf("clk\t\tfrequency\n");
  548. for (i = 0; i < clk_max; i++) {
  549. const char *name = clk_names[i];
  550. if (name) {
  551. struct clk clk;
  552. unsigned long rate;
  553. clk.id = i;
  554. ret = clk_request(dev, &clk);
  555. if (ret < 0)
  556. return ret;
  557. rate = clk_get_rate(&clk);
  558. clk_free(&clk);
  559. if ((rate == (unsigned long)-ENOSYS) ||
  560. (rate == (unsigned long)-ENXIO) ||
  561. (rate == (unsigned long)-EIO))
  562. printf("%10s%20s\n", name, "unknown");
  563. else
  564. printf("%10s%20lu\n", name, rate);
  565. }
  566. }
  567. return 0;
  568. }
  569. static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
  570. {
  571. struct clk clk;
  572. int ret;
  573. ret = clk_get_by_name(dev, name, &clk);
  574. if (ret < 0) {
  575. dev_err(dev, "failed to get %s\n", name);
  576. return ret;
  577. }
  578. *freq = clk_get_rate(&clk);
  579. if (IS_ERR_VALUE(*freq)) {
  580. dev_err(dev, "failed to get rate %s\n", name);
  581. return -EINVAL;
  582. }
  583. return 0;
  584. }
  585. static int zynqmp_clk_probe(struct udevice *dev)
  586. {
  587. int ret;
  588. struct zynqmp_clk_priv *priv = dev_get_priv(dev);
  589. debug("%s\n", __func__);
  590. ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
  591. if (ret < 0)
  592. return -EINVAL;
  593. ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
  594. if (ret < 0)
  595. return -EINVAL;
  596. ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
  597. &priv->pss_alt_ref_clk);
  598. if (ret < 0)
  599. return -EINVAL;
  600. ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
  601. if (ret < 0)
  602. return -EINVAL;
  603. ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
  604. &priv->gt_crx_ref_clk);
  605. if (ret < 0)
  606. return -EINVAL;
  607. return 0;
  608. }
  609. static struct clk_ops zynqmp_clk_ops = {
  610. .set_rate = zynqmp_clk_set_rate,
  611. .get_rate = zynqmp_clk_get_rate,
  612. };
  613. static const struct udevice_id zynqmp_clk_ids[] = {
  614. { .compatible = "xlnx,zynqmp-clk" },
  615. { .compatible = "xlnx,zynqmp-clkc" },
  616. { }
  617. };
  618. U_BOOT_DRIVER(zynqmp_clk) = {
  619. .name = "zynqmp-clk",
  620. .id = UCLASS_CLK,
  621. .of_match = zynqmp_clk_ids,
  622. .probe = zynqmp_clk_probe,
  623. .ops = &zynqmp_clk_ops,
  624. .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
  625. };