clk_stm32mp1.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <div64.h>
  8. #include <dm.h>
  9. #include <regmap.h>
  10. #include <spl.h>
  11. #include <syscon.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <dt-bindings/clock/stm32mp1-clks.h>
  15. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  16. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  17. /* activate clock tree initialization in the driver */
  18. #define STM32MP1_CLOCK_TREE_INIT
  19. #endif
  20. #define MAX_HSI_HZ 64000000
  21. /* TIMEOUT */
  22. #define TIMEOUT_200MS 200000
  23. #define TIMEOUT_1S 1000000
  24. /* STGEN registers */
  25. #define STGENC_CNTCR 0x00
  26. #define STGENC_CNTSR 0x04
  27. #define STGENC_CNTCVL 0x08
  28. #define STGENC_CNTCVU 0x0C
  29. #define STGENC_CNTFID0 0x20
  30. #define STGENC_CNTCR_EN BIT(0)
  31. /* RCC registers */
  32. #define RCC_OCENSETR 0x0C
  33. #define RCC_OCENCLRR 0x10
  34. #define RCC_HSICFGR 0x18
  35. #define RCC_MPCKSELR 0x20
  36. #define RCC_ASSCKSELR 0x24
  37. #define RCC_RCK12SELR 0x28
  38. #define RCC_MPCKDIVR 0x2C
  39. #define RCC_AXIDIVR 0x30
  40. #define RCC_APB4DIVR 0x3C
  41. #define RCC_APB5DIVR 0x40
  42. #define RCC_RTCDIVR 0x44
  43. #define RCC_MSSCKSELR 0x48
  44. #define RCC_PLL1CR 0x80
  45. #define RCC_PLL1CFGR1 0x84
  46. #define RCC_PLL1CFGR2 0x88
  47. #define RCC_PLL1FRACR 0x8C
  48. #define RCC_PLL1CSGR 0x90
  49. #define RCC_PLL2CR 0x94
  50. #define RCC_PLL2CFGR1 0x98
  51. #define RCC_PLL2CFGR2 0x9C
  52. #define RCC_PLL2FRACR 0xA0
  53. #define RCC_PLL2CSGR 0xA4
  54. #define RCC_I2C46CKSELR 0xC0
  55. #define RCC_CPERCKSELR 0xD0
  56. #define RCC_STGENCKSELR 0xD4
  57. #define RCC_DDRITFCR 0xD8
  58. #define RCC_BDCR 0x140
  59. #define RCC_RDLSICR 0x144
  60. #define RCC_MP_APB4ENSETR 0x200
  61. #define RCC_MP_APB5ENSETR 0x208
  62. #define RCC_MP_AHB5ENSETR 0x210
  63. #define RCC_MP_AHB6ENSETR 0x218
  64. #define RCC_OCRDYR 0x808
  65. #define RCC_DBGCFGR 0x80C
  66. #define RCC_RCK3SELR 0x820
  67. #define RCC_RCK4SELR 0x824
  68. #define RCC_MCUDIVR 0x830
  69. #define RCC_APB1DIVR 0x834
  70. #define RCC_APB2DIVR 0x838
  71. #define RCC_APB3DIVR 0x83C
  72. #define RCC_PLL3CR 0x880
  73. #define RCC_PLL3CFGR1 0x884
  74. #define RCC_PLL3CFGR2 0x888
  75. #define RCC_PLL3FRACR 0x88C
  76. #define RCC_PLL3CSGR 0x890
  77. #define RCC_PLL4CR 0x894
  78. #define RCC_PLL4CFGR1 0x898
  79. #define RCC_PLL4CFGR2 0x89C
  80. #define RCC_PLL4FRACR 0x8A0
  81. #define RCC_PLL4CSGR 0x8A4
  82. #define RCC_I2C12CKSELR 0x8C0
  83. #define RCC_I2C35CKSELR 0x8C4
  84. #define RCC_UART6CKSELR 0x8E4
  85. #define RCC_UART24CKSELR 0x8E8
  86. #define RCC_UART35CKSELR 0x8EC
  87. #define RCC_UART78CKSELR 0x8F0
  88. #define RCC_SDMMC12CKSELR 0x8F4
  89. #define RCC_SDMMC3CKSELR 0x8F8
  90. #define RCC_ETHCKSELR 0x8FC
  91. #define RCC_QSPICKSELR 0x900
  92. #define RCC_FMCCKSELR 0x904
  93. #define RCC_USBCKSELR 0x91C
  94. #define RCC_MP_APB1ENSETR 0xA00
  95. #define RCC_MP_APB2ENSETR 0XA08
  96. #define RCC_MP_AHB2ENSETR 0xA18
  97. #define RCC_MP_AHB4ENSETR 0xA28
  98. /* used for most of SELR register */
  99. #define RCC_SELR_SRC_MASK GENMASK(2, 0)
  100. #define RCC_SELR_SRCRDY BIT(31)
  101. /* Values of RCC_MPCKSELR register */
  102. #define RCC_MPCKSELR_HSI 0
  103. #define RCC_MPCKSELR_HSE 1
  104. #define RCC_MPCKSELR_PLL 2
  105. #define RCC_MPCKSELR_PLL_MPUDIV 3
  106. /* Values of RCC_ASSCKSELR register */
  107. #define RCC_ASSCKSELR_HSI 0
  108. #define RCC_ASSCKSELR_HSE 1
  109. #define RCC_ASSCKSELR_PLL 2
  110. /* Values of RCC_MSSCKSELR register */
  111. #define RCC_MSSCKSELR_HSI 0
  112. #define RCC_MSSCKSELR_HSE 1
  113. #define RCC_MSSCKSELR_CSI 2
  114. #define RCC_MSSCKSELR_PLL 3
  115. /* Values of RCC_CPERCKSELR register */
  116. #define RCC_CPERCKSELR_HSI 0
  117. #define RCC_CPERCKSELR_CSI 1
  118. #define RCC_CPERCKSELR_HSE 2
  119. /* used for most of DIVR register : max div for RTC */
  120. #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
  121. #define RCC_DIVR_DIVRDY BIT(31)
  122. /* Masks for specific DIVR registers */
  123. #define RCC_APBXDIV_MASK GENMASK(2, 0)
  124. #define RCC_MPUDIV_MASK GENMASK(2, 0)
  125. #define RCC_AXIDIV_MASK GENMASK(2, 0)
  126. #define RCC_MCUDIV_MASK GENMASK(3, 0)
  127. /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
  128. #define RCC_MP_ENCLRR_OFFSET 4
  129. /* Fields of RCC_BDCR register */
  130. #define RCC_BDCR_LSEON BIT(0)
  131. #define RCC_BDCR_LSEBYP BIT(1)
  132. #define RCC_BDCR_LSERDY BIT(2)
  133. #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
  134. #define RCC_BDCR_LSEDRV_SHIFT 4
  135. #define RCC_BDCR_LSECSSON BIT(8)
  136. #define RCC_BDCR_RTCCKEN BIT(20)
  137. #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
  138. #define RCC_BDCR_RTCSRC_SHIFT 16
  139. /* Fields of RCC_RDLSICR register */
  140. #define RCC_RDLSICR_LSION BIT(0)
  141. #define RCC_RDLSICR_LSIRDY BIT(1)
  142. /* used for ALL PLLNCR registers */
  143. #define RCC_PLLNCR_PLLON BIT(0)
  144. #define RCC_PLLNCR_PLLRDY BIT(1)
  145. #define RCC_PLLNCR_DIVPEN BIT(4)
  146. #define RCC_PLLNCR_DIVQEN BIT(5)
  147. #define RCC_PLLNCR_DIVREN BIT(6)
  148. #define RCC_PLLNCR_DIVEN_SHIFT 4
  149. /* used for ALL PLLNCFGR1 registers */
  150. #define RCC_PLLNCFGR1_DIVM_SHIFT 16
  151. #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
  152. #define RCC_PLLNCFGR1_DIVN_SHIFT 0
  153. #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
  154. /* only for PLL3 and PLL4 */
  155. #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
  156. #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
  157. /* used for ALL PLLNCFGR2 registers */
  158. #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
  159. #define RCC_PLLNCFGR2_DIVP_SHIFT 0
  160. #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
  161. #define RCC_PLLNCFGR2_DIVQ_SHIFT 8
  162. #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
  163. #define RCC_PLLNCFGR2_DIVR_SHIFT 16
  164. #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
  165. /* used for ALL PLLNFRACR registers */
  166. #define RCC_PLLNFRACR_FRACV_SHIFT 3
  167. #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
  168. #define RCC_PLLNFRACR_FRACLE BIT(16)
  169. /* used for ALL PLLNCSGR registers */
  170. #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
  171. #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
  172. #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
  173. #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
  174. #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
  175. #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
  176. /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
  177. #define RCC_OCENR_HSION BIT(0)
  178. #define RCC_OCENR_CSION BIT(4)
  179. #define RCC_OCENR_HSEON BIT(8)
  180. #define RCC_OCENR_HSEBYP BIT(10)
  181. #define RCC_OCENR_HSECSSON BIT(11)
  182. /* Fields of RCC_OCRDYR register */
  183. #define RCC_OCRDYR_HSIRDY BIT(0)
  184. #define RCC_OCRDYR_HSIDIVRDY BIT(2)
  185. #define RCC_OCRDYR_CSIRDY BIT(4)
  186. #define RCC_OCRDYR_HSERDY BIT(8)
  187. /* Fields of DDRITFCR register */
  188. #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
  189. #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
  190. #define RCC_DDRITFCR_DDRCKMOD_SSR 0
  191. /* Fields of RCC_HSICFGR register */
  192. #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
  193. /* used for MCO related operations */
  194. #define RCC_MCOCFG_MCOON BIT(12)
  195. #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
  196. #define RCC_MCOCFG_MCODIV_SHIFT 4
  197. #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
  198. enum stm32mp1_parent_id {
  199. /*
  200. * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
  201. * they are used as index in osc[] as entry point
  202. */
  203. _HSI,
  204. _HSE,
  205. _CSI,
  206. _LSI,
  207. _LSE,
  208. _I2S_CKIN,
  209. _USB_PHY_48,
  210. NB_OSC,
  211. /* other parent source */
  212. _HSI_KER = NB_OSC,
  213. _HSE_KER,
  214. _HSE_KER_DIV2,
  215. _CSI_KER,
  216. _PLL1_P,
  217. _PLL1_Q,
  218. _PLL1_R,
  219. _PLL2_P,
  220. _PLL2_Q,
  221. _PLL2_R,
  222. _PLL3_P,
  223. _PLL3_Q,
  224. _PLL3_R,
  225. _PLL4_P,
  226. _PLL4_Q,
  227. _PLL4_R,
  228. _ACLK,
  229. _PCLK1,
  230. _PCLK2,
  231. _PCLK3,
  232. _PCLK4,
  233. _PCLK5,
  234. _HCLK6,
  235. _HCLK2,
  236. _CK_PER,
  237. _CK_MPU,
  238. _CK_MCU,
  239. _PARENT_NB,
  240. _UNKNOWN_ID = 0xff,
  241. };
  242. enum stm32mp1_parent_sel {
  243. _I2C12_SEL,
  244. _I2C35_SEL,
  245. _I2C46_SEL,
  246. _UART6_SEL,
  247. _UART24_SEL,
  248. _UART35_SEL,
  249. _UART78_SEL,
  250. _SDMMC12_SEL,
  251. _SDMMC3_SEL,
  252. _ETH_SEL,
  253. _QSPI_SEL,
  254. _FMC_SEL,
  255. _USBPHY_SEL,
  256. _USBO_SEL,
  257. _STGEN_SEL,
  258. _PARENT_SEL_NB,
  259. _UNKNOWN_SEL = 0xff,
  260. };
  261. enum stm32mp1_pll_id {
  262. _PLL1,
  263. _PLL2,
  264. _PLL3,
  265. _PLL4,
  266. _PLL_NB
  267. };
  268. enum stm32mp1_div_id {
  269. _DIV_P,
  270. _DIV_Q,
  271. _DIV_R,
  272. _DIV_NB,
  273. };
  274. enum stm32mp1_clksrc_id {
  275. CLKSRC_MPU,
  276. CLKSRC_AXI,
  277. CLKSRC_MCU,
  278. CLKSRC_PLL12,
  279. CLKSRC_PLL3,
  280. CLKSRC_PLL4,
  281. CLKSRC_RTC,
  282. CLKSRC_MCO1,
  283. CLKSRC_MCO2,
  284. CLKSRC_NB
  285. };
  286. enum stm32mp1_clkdiv_id {
  287. CLKDIV_MPU,
  288. CLKDIV_AXI,
  289. CLKDIV_MCU,
  290. CLKDIV_APB1,
  291. CLKDIV_APB2,
  292. CLKDIV_APB3,
  293. CLKDIV_APB4,
  294. CLKDIV_APB5,
  295. CLKDIV_RTC,
  296. CLKDIV_MCO1,
  297. CLKDIV_MCO2,
  298. CLKDIV_NB
  299. };
  300. enum stm32mp1_pllcfg {
  301. PLLCFG_M,
  302. PLLCFG_N,
  303. PLLCFG_P,
  304. PLLCFG_Q,
  305. PLLCFG_R,
  306. PLLCFG_O,
  307. PLLCFG_NB
  308. };
  309. enum stm32mp1_pllcsg {
  310. PLLCSG_MOD_PER,
  311. PLLCSG_INC_STEP,
  312. PLLCSG_SSCG_MODE,
  313. PLLCSG_NB
  314. };
  315. enum stm32mp1_plltype {
  316. PLL_800,
  317. PLL_1600,
  318. PLL_TYPE_NB
  319. };
  320. struct stm32mp1_pll {
  321. u8 refclk_min;
  322. u8 refclk_max;
  323. u8 divn_max;
  324. };
  325. struct stm32mp1_clk_gate {
  326. u16 offset;
  327. u8 bit;
  328. u8 index;
  329. u8 set_clr;
  330. u8 sel;
  331. u8 fixed;
  332. };
  333. struct stm32mp1_clk_sel {
  334. u16 offset;
  335. u8 src;
  336. u8 msk;
  337. u8 nb_parent;
  338. const u8 *parent;
  339. };
  340. #define REFCLK_SIZE 4
  341. struct stm32mp1_clk_pll {
  342. enum stm32mp1_plltype plltype;
  343. u16 rckxselr;
  344. u16 pllxcfgr1;
  345. u16 pllxcfgr2;
  346. u16 pllxfracr;
  347. u16 pllxcr;
  348. u16 pllxcsgr;
  349. u8 refclk[REFCLK_SIZE];
  350. };
  351. struct stm32mp1_clk_data {
  352. const struct stm32mp1_clk_gate *gate;
  353. const struct stm32mp1_clk_sel *sel;
  354. const struct stm32mp1_clk_pll *pll;
  355. const int nb_gate;
  356. };
  357. struct stm32mp1_clk_priv {
  358. fdt_addr_t base;
  359. const struct stm32mp1_clk_data *data;
  360. ulong osc[NB_OSC];
  361. struct udevice *osc_dev[NB_OSC];
  362. };
  363. #define STM32MP1_CLK(off, b, idx, s) \
  364. { \
  365. .offset = (off), \
  366. .bit = (b), \
  367. .index = (idx), \
  368. .set_clr = 0, \
  369. .sel = (s), \
  370. .fixed = _UNKNOWN_ID, \
  371. }
  372. #define STM32MP1_CLK_F(off, b, idx, f) \
  373. { \
  374. .offset = (off), \
  375. .bit = (b), \
  376. .index = (idx), \
  377. .set_clr = 0, \
  378. .sel = _UNKNOWN_SEL, \
  379. .fixed = (f), \
  380. }
  381. #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
  382. { \
  383. .offset = (off), \
  384. .bit = (b), \
  385. .index = (idx), \
  386. .set_clr = 1, \
  387. .sel = (s), \
  388. .fixed = _UNKNOWN_ID, \
  389. }
  390. #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
  391. { \
  392. .offset = (off), \
  393. .bit = (b), \
  394. .index = (idx), \
  395. .set_clr = 1, \
  396. .sel = _UNKNOWN_SEL, \
  397. .fixed = (f), \
  398. }
  399. #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
  400. [(idx)] = { \
  401. .offset = (off), \
  402. .src = (s), \
  403. .msk = (m), \
  404. .parent = (p), \
  405. .nb_parent = ARRAY_SIZE((p)) \
  406. }
  407. #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
  408. p1, p2, p3, p4) \
  409. [(idx)] = { \
  410. .plltype = (type), \
  411. .rckxselr = (off1), \
  412. .pllxcfgr1 = (off2), \
  413. .pllxcfgr2 = (off3), \
  414. .pllxfracr = (off4), \
  415. .pllxcr = (off5), \
  416. .pllxcsgr = (off6), \
  417. .refclk[0] = (p1), \
  418. .refclk[1] = (p2), \
  419. .refclk[2] = (p3), \
  420. .refclk[3] = (p4), \
  421. }
  422. static const u8 stm32mp1_clks[][2] = {
  423. {CK_PER, _CK_PER},
  424. {CK_MPU, _CK_MPU},
  425. {CK_AXI, _ACLK},
  426. {CK_MCU, _CK_MCU},
  427. {CK_HSE, _HSE},
  428. {CK_CSI, _CSI},
  429. {CK_LSI, _LSI},
  430. {CK_LSE, _LSE},
  431. {CK_HSI, _HSI},
  432. {CK_HSE_DIV2, _HSE_KER_DIV2},
  433. };
  434. static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
  435. STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
  436. STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
  437. STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
  438. STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
  439. STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
  440. STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
  441. STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
  442. STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
  443. STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
  444. STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
  445. STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
  446. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
  447. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
  448. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
  449. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
  450. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
  451. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
  452. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
  453. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
  454. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
  455. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
  456. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
  457. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
  458. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
  459. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
  460. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
  461. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
  462. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
  463. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
  464. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
  465. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
  466. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
  467. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
  468. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
  469. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
  470. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
  471. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
  472. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
  473. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
  474. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
  475. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
  476. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
  477. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
  478. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
  479. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
  480. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
  481. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
  482. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
  483. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
  484. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
  485. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
  486. STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
  487. };
  488. static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  489. static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  490. static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
  491. static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  492. _HSE_KER};
  493. static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  494. _HSE_KER};
  495. static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  496. _HSE_KER};
  497. static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  498. _HSE_KER};
  499. static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
  500. static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
  501. static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
  502. static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  503. static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  504. static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
  505. static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
  506. static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
  507. static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
  508. STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
  509. STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
  510. STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
  511. STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
  512. STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
  513. uart24_parents),
  514. STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
  515. uart35_parents),
  516. STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
  517. uart78_parents),
  518. STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
  519. sdmmc12_parents),
  520. STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
  521. sdmmc3_parents),
  522. STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
  523. STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
  524. STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
  525. STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
  526. STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
  527. STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
  528. };
  529. #ifdef STM32MP1_CLOCK_TREE_INIT
  530. /* define characteristic of PLL according type */
  531. #define DIVN_MIN 24
  532. static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
  533. [PLL_800] = {
  534. .refclk_min = 4,
  535. .refclk_max = 16,
  536. .divn_max = 99,
  537. },
  538. [PLL_1600] = {
  539. .refclk_min = 8,
  540. .refclk_max = 16,
  541. .divn_max = 199,
  542. },
  543. };
  544. #endif /* STM32MP1_CLOCK_TREE_INIT */
  545. static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
  546. STM32MP1_CLK_PLL(_PLL1, PLL_1600,
  547. RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
  548. RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
  549. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  550. STM32MP1_CLK_PLL(_PLL2, PLL_1600,
  551. RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
  552. RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
  553. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  554. STM32MP1_CLK_PLL(_PLL3, PLL_800,
  555. RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
  556. RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
  557. _HSI, _HSE, _CSI, _UNKNOWN_ID),
  558. STM32MP1_CLK_PLL(_PLL4, PLL_800,
  559. RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
  560. RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
  561. _HSI, _HSE, _CSI, _I2S_CKIN),
  562. };
  563. /* Prescaler table lookups for clock computation */
  564. /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
  565. static const u8 stm32mp1_mcu_div[16] = {
  566. 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
  567. };
  568. /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
  569. #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
  570. #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
  571. static const u8 stm32mp1_mpu_apbx_div[8] = {
  572. 0, 1, 2, 3, 4, 4, 4, 4
  573. };
  574. /* div = /1 /2 /3 /4 */
  575. static const u8 stm32mp1_axi_div[8] = {
  576. 1, 2, 3, 4, 4, 4, 4, 4
  577. };
  578. #ifdef DEBUG
  579. static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
  580. [_HSI] = "HSI",
  581. [_HSE] = "HSE",
  582. [_CSI] = "CSI",
  583. [_LSI] = "LSI",
  584. [_LSE] = "LSE",
  585. [_I2S_CKIN] = "I2S_CKIN",
  586. [_HSI_KER] = "HSI_KER",
  587. [_HSE_KER] = "HSE_KER",
  588. [_HSE_KER_DIV2] = "HSE_KER_DIV2",
  589. [_CSI_KER] = "CSI_KER",
  590. [_PLL1_P] = "PLL1_P",
  591. [_PLL1_Q] = "PLL1_Q",
  592. [_PLL1_R] = "PLL1_R",
  593. [_PLL2_P] = "PLL2_P",
  594. [_PLL2_Q] = "PLL2_Q",
  595. [_PLL2_R] = "PLL2_R",
  596. [_PLL3_P] = "PLL3_P",
  597. [_PLL3_Q] = "PLL3_Q",
  598. [_PLL3_R] = "PLL3_R",
  599. [_PLL4_P] = "PLL4_P",
  600. [_PLL4_Q] = "PLL4_Q",
  601. [_PLL4_R] = "PLL4_R",
  602. [_ACLK] = "ACLK",
  603. [_PCLK1] = "PCLK1",
  604. [_PCLK2] = "PCLK2",
  605. [_PCLK3] = "PCLK3",
  606. [_PCLK4] = "PCLK4",
  607. [_PCLK5] = "PCLK5",
  608. [_HCLK6] = "KCLK6",
  609. [_HCLK2] = "HCLK2",
  610. [_CK_PER] = "CK_PER",
  611. [_CK_MPU] = "CK_MPU",
  612. [_CK_MCU] = "CK_MCU",
  613. [_USB_PHY_48] = "USB_PHY_48"
  614. };
  615. static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
  616. [_I2C12_SEL] = "I2C12",
  617. [_I2C35_SEL] = "I2C35",
  618. [_I2C46_SEL] = "I2C46",
  619. [_UART6_SEL] = "UART6",
  620. [_UART24_SEL] = "UART24",
  621. [_UART35_SEL] = "UART35",
  622. [_UART78_SEL] = "UART78",
  623. [_SDMMC12_SEL] = "SDMMC12",
  624. [_SDMMC3_SEL] = "SDMMC3",
  625. [_ETH_SEL] = "ETH",
  626. [_QSPI_SEL] = "QSPI",
  627. [_FMC_SEL] = "FMC",
  628. [_USBPHY_SEL] = "USBPHY",
  629. [_USBO_SEL] = "USBO",
  630. [_STGEN_SEL] = "STGEN"
  631. };
  632. #endif
  633. static const struct stm32mp1_clk_data stm32mp1_data = {
  634. .gate = stm32mp1_clk_gate,
  635. .sel = stm32mp1_clk_sel,
  636. .pll = stm32mp1_clk_pll,
  637. .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
  638. };
  639. static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
  640. {
  641. if (idx >= NB_OSC) {
  642. debug("%s: clk id %d not found\n", __func__, idx);
  643. return 0;
  644. }
  645. debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
  646. (u32)priv->osc[idx], priv->osc[idx] / 1000);
  647. return priv->osc[idx];
  648. }
  649. static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
  650. {
  651. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  652. int i, nb_clks = priv->data->nb_gate;
  653. for (i = 0; i < nb_clks; i++) {
  654. if (gate[i].index == id)
  655. break;
  656. }
  657. if (i == nb_clks) {
  658. printf("%s: clk id %d not found\n", __func__, (u32)id);
  659. return -EINVAL;
  660. }
  661. return i;
  662. }
  663. static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
  664. int i)
  665. {
  666. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  667. if (gate[i].sel > _PARENT_SEL_NB) {
  668. printf("%s: parents for clk id %d not found\n",
  669. __func__, i);
  670. return -EINVAL;
  671. }
  672. return gate[i].sel;
  673. }
  674. static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
  675. int i)
  676. {
  677. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  678. if (gate[i].fixed == _UNKNOWN_ID)
  679. return -ENOENT;
  680. return gate[i].fixed;
  681. }
  682. static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
  683. unsigned long id)
  684. {
  685. const struct stm32mp1_clk_sel *sel = priv->data->sel;
  686. int i;
  687. int s, p;
  688. for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
  689. if (stm32mp1_clks[i][0] == id)
  690. return stm32mp1_clks[i][1];
  691. i = stm32mp1_clk_get_id(priv, id);
  692. if (i < 0)
  693. return i;
  694. p = stm32mp1_clk_get_fixed_parent(priv, i);
  695. if (p >= 0 && p < _PARENT_NB)
  696. return p;
  697. s = stm32mp1_clk_get_sel(priv, i);
  698. if (s < 0)
  699. return s;
  700. p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
  701. if (p < sel[s].nb_parent) {
  702. #ifdef DEBUG
  703. debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
  704. stm32mp1_clk_parent_name[sel[s].parent[p]],
  705. stm32mp1_clk_parent_sel_name[s],
  706. (u32)id);
  707. #endif
  708. return sel[s].parent[p];
  709. }
  710. pr_err("%s: no parents defined for clk id %d\n",
  711. __func__, (u32)id);
  712. return -EINVAL;
  713. }
  714. static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
  715. int pll_id, int div_id)
  716. {
  717. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  718. int divm, divn, divy, src;
  719. ulong refclk, dfout;
  720. u32 selr, cfgr1, cfgr2, fracr;
  721. const u8 shift[_DIV_NB] = {
  722. [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
  723. [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
  724. [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
  725. debug("%s(%d, %d)\n", __func__, pll_id, div_id);
  726. if (div_id > _DIV_NB)
  727. return 0;
  728. selr = readl(priv->base + pll[pll_id].rckxselr);
  729. cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
  730. cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
  731. fracr = readl(priv->base + pll[pll_id].pllxfracr);
  732. debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
  733. pll_id, selr, cfgr1, cfgr2, fracr);
  734. divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
  735. divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
  736. divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
  737. debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
  738. src = selr & RCC_SELR_SRC_MASK;
  739. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
  740. debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
  741. /*
  742. * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
  743. * So same final result than PLL2 et 4
  744. * with FRACV :
  745. * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
  746. * / (DIVM + 1) * (DIVy + 1)
  747. * without FRACV
  748. * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
  749. */
  750. if (fracr & RCC_PLLNFRACR_FRACLE) {
  751. u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
  752. >> RCC_PLLNFRACR_FRACV_SHIFT;
  753. dfout = (ulong)lldiv((unsigned long long)refclk *
  754. (((divn + 1) << 13) + fracv),
  755. ((unsigned long long)(divm + 1) *
  756. (divy + 1)) << 13);
  757. } else {
  758. dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
  759. }
  760. debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
  761. return dfout;
  762. }
  763. static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
  764. {
  765. u32 reg;
  766. ulong clock = 0;
  767. switch (p) {
  768. case _CK_MPU:
  769. /* MPU sub system */
  770. reg = readl(priv->base + RCC_MPCKSELR);
  771. switch (reg & RCC_SELR_SRC_MASK) {
  772. case RCC_MPCKSELR_HSI:
  773. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  774. break;
  775. case RCC_MPCKSELR_HSE:
  776. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  777. break;
  778. case RCC_MPCKSELR_PLL:
  779. case RCC_MPCKSELR_PLL_MPUDIV:
  780. clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
  781. if (p == RCC_MPCKSELR_PLL_MPUDIV) {
  782. reg = readl(priv->base + RCC_MPCKDIVR);
  783. clock /= stm32mp1_mpu_div[reg &
  784. RCC_MPUDIV_MASK];
  785. }
  786. break;
  787. }
  788. break;
  789. /* AXI sub system */
  790. case _ACLK:
  791. case _HCLK2:
  792. case _HCLK6:
  793. case _PCLK4:
  794. case _PCLK5:
  795. reg = readl(priv->base + RCC_ASSCKSELR);
  796. switch (reg & RCC_SELR_SRC_MASK) {
  797. case RCC_ASSCKSELR_HSI:
  798. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  799. break;
  800. case RCC_ASSCKSELR_HSE:
  801. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  802. break;
  803. case RCC_ASSCKSELR_PLL:
  804. clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
  805. break;
  806. }
  807. /* System clock divider */
  808. reg = readl(priv->base + RCC_AXIDIVR);
  809. clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
  810. switch (p) {
  811. case _PCLK4:
  812. reg = readl(priv->base + RCC_APB4DIVR);
  813. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  814. break;
  815. case _PCLK5:
  816. reg = readl(priv->base + RCC_APB5DIVR);
  817. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  818. break;
  819. default:
  820. break;
  821. }
  822. break;
  823. /* MCU sub system */
  824. case _CK_MCU:
  825. case _PCLK1:
  826. case _PCLK2:
  827. case _PCLK3:
  828. reg = readl(priv->base + RCC_MSSCKSELR);
  829. switch (reg & RCC_SELR_SRC_MASK) {
  830. case RCC_MSSCKSELR_HSI:
  831. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  832. break;
  833. case RCC_MSSCKSELR_HSE:
  834. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  835. break;
  836. case RCC_MSSCKSELR_CSI:
  837. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  838. break;
  839. case RCC_MSSCKSELR_PLL:
  840. clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
  841. break;
  842. }
  843. /* MCU clock divider */
  844. reg = readl(priv->base + RCC_MCUDIVR);
  845. clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
  846. switch (p) {
  847. case _PCLK1:
  848. reg = readl(priv->base + RCC_APB1DIVR);
  849. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  850. break;
  851. case _PCLK2:
  852. reg = readl(priv->base + RCC_APB2DIVR);
  853. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  854. break;
  855. case _PCLK3:
  856. reg = readl(priv->base + RCC_APB3DIVR);
  857. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  858. break;
  859. case _CK_MCU:
  860. default:
  861. break;
  862. }
  863. break;
  864. case _CK_PER:
  865. reg = readl(priv->base + RCC_CPERCKSELR);
  866. switch (reg & RCC_SELR_SRC_MASK) {
  867. case RCC_CPERCKSELR_HSI:
  868. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  869. break;
  870. case RCC_CPERCKSELR_HSE:
  871. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  872. break;
  873. case RCC_CPERCKSELR_CSI:
  874. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  875. break;
  876. }
  877. break;
  878. case _HSI:
  879. case _HSI_KER:
  880. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  881. break;
  882. case _CSI:
  883. case _CSI_KER:
  884. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  885. break;
  886. case _HSE:
  887. case _HSE_KER:
  888. case _HSE_KER_DIV2:
  889. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  890. if (p == _HSE_KER_DIV2)
  891. clock >>= 1;
  892. break;
  893. case _LSI:
  894. clock = stm32mp1_clk_get_fixed(priv, _LSI);
  895. break;
  896. case _LSE:
  897. clock = stm32mp1_clk_get_fixed(priv, _LSE);
  898. break;
  899. /* PLL */
  900. case _PLL1_P:
  901. case _PLL1_Q:
  902. case _PLL1_R:
  903. clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
  904. break;
  905. case _PLL2_P:
  906. case _PLL2_Q:
  907. case _PLL2_R:
  908. clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
  909. break;
  910. case _PLL3_P:
  911. case _PLL3_Q:
  912. case _PLL3_R:
  913. clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
  914. break;
  915. case _PLL4_P:
  916. case _PLL4_Q:
  917. case _PLL4_R:
  918. clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
  919. break;
  920. /* other */
  921. case _USB_PHY_48:
  922. clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
  923. break;
  924. default:
  925. break;
  926. }
  927. debug("%s(%d) clock = %lx : %ld kHz\n",
  928. __func__, p, clock, clock / 1000);
  929. return clock;
  930. }
  931. static int stm32mp1_clk_enable(struct clk *clk)
  932. {
  933. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  934. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  935. int i = stm32mp1_clk_get_id(priv, clk->id);
  936. if (i < 0)
  937. return i;
  938. if (gate[i].set_clr)
  939. writel(BIT(gate[i].bit), priv->base + gate[i].offset);
  940. else
  941. setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  942. debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
  943. return 0;
  944. }
  945. static int stm32mp1_clk_disable(struct clk *clk)
  946. {
  947. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  948. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  949. int i = stm32mp1_clk_get_id(priv, clk->id);
  950. if (i < 0)
  951. return i;
  952. if (gate[i].set_clr)
  953. writel(BIT(gate[i].bit),
  954. priv->base + gate[i].offset
  955. + RCC_MP_ENCLRR_OFFSET);
  956. else
  957. clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  958. debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
  959. return 0;
  960. }
  961. static ulong stm32mp1_clk_get_rate(struct clk *clk)
  962. {
  963. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  964. int p = stm32mp1_clk_get_parent(priv, clk->id);
  965. ulong rate;
  966. if (p < 0)
  967. return 0;
  968. rate = stm32mp1_clk_get(priv, p);
  969. #ifdef DEBUG
  970. debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
  971. __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
  972. #endif
  973. return rate;
  974. }
  975. #ifdef STM32MP1_CLOCK_TREE_INIT
  976. static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
  977. u32 mask_on)
  978. {
  979. u32 address = rcc + offset;
  980. if (enable)
  981. setbits_le32(address, mask_on);
  982. else
  983. clrbits_le32(address, mask_on);
  984. }
  985. static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
  986. {
  987. if (enable)
  988. setbits_le32(rcc + RCC_OCENSETR, mask_on);
  989. else
  990. setbits_le32(rcc + RCC_OCENCLRR, mask_on);
  991. }
  992. static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
  993. u32 mask_rdy)
  994. {
  995. u32 mask_test = 0;
  996. u32 address = rcc + offset;
  997. u32 val;
  998. int ret;
  999. if (enable)
  1000. mask_test = mask_rdy;
  1001. ret = readl_poll_timeout(address, val,
  1002. (val & mask_rdy) == mask_test,
  1003. TIMEOUT_1S);
  1004. if (ret)
  1005. pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
  1006. mask_rdy, address, enable, readl(address));
  1007. return ret;
  1008. }
  1009. static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
  1010. {
  1011. u32 value;
  1012. if (bypass)
  1013. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
  1014. /*
  1015. * warning: not recommended to switch directly from "high drive"
  1016. * to "medium low drive", and vice-versa.
  1017. */
  1018. value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
  1019. >> RCC_BDCR_LSEDRV_SHIFT;
  1020. while (value != lsedrv) {
  1021. if (value > lsedrv)
  1022. value--;
  1023. else
  1024. value++;
  1025. clrsetbits_le32(rcc + RCC_BDCR,
  1026. RCC_BDCR_LSEDRV_MASK,
  1027. value << RCC_BDCR_LSEDRV_SHIFT);
  1028. }
  1029. stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
  1030. }
  1031. static void stm32mp1_lse_wait(fdt_addr_t rcc)
  1032. {
  1033. stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
  1034. }
  1035. static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
  1036. {
  1037. stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
  1038. stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
  1039. }
  1040. static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
  1041. {
  1042. if (bypass)
  1043. setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
  1044. stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
  1045. stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
  1046. if (css)
  1047. setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
  1048. }
  1049. static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
  1050. {
  1051. stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
  1052. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
  1053. }
  1054. static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
  1055. {
  1056. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
  1057. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
  1058. }
  1059. static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
  1060. {
  1061. u32 address = rcc + RCC_OCRDYR;
  1062. u32 val;
  1063. int ret;
  1064. clrsetbits_le32(rcc + RCC_HSICFGR,
  1065. RCC_HSICFGR_HSIDIV_MASK,
  1066. RCC_HSICFGR_HSIDIV_MASK & hsidiv);
  1067. ret = readl_poll_timeout(address, val,
  1068. val & RCC_OCRDYR_HSIDIVRDY,
  1069. TIMEOUT_200MS);
  1070. if (ret)
  1071. pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
  1072. address, readl(address));
  1073. return ret;
  1074. }
  1075. static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
  1076. {
  1077. u8 hsidiv;
  1078. u32 hsidivfreq = MAX_HSI_HZ;
  1079. for (hsidiv = 0; hsidiv < 4; hsidiv++,
  1080. hsidivfreq = hsidivfreq / 2)
  1081. if (hsidivfreq == hsifreq)
  1082. break;
  1083. if (hsidiv == 4) {
  1084. pr_err("clk-hsi frequency invalid");
  1085. return -1;
  1086. }
  1087. if (hsidiv > 0)
  1088. return stm32mp1_set_hsidiv(rcc, hsidiv);
  1089. return 0;
  1090. }
  1091. static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
  1092. {
  1093. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1094. writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
  1095. }
  1096. static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
  1097. {
  1098. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1099. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1100. u32 val;
  1101. int ret;
  1102. ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
  1103. TIMEOUT_200MS);
  1104. if (ret) {
  1105. pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
  1106. pll_id, pllxcr, readl(pllxcr));
  1107. return ret;
  1108. }
  1109. /* start the requested output */
  1110. setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
  1111. return 0;
  1112. }
  1113. static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
  1114. {
  1115. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1116. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1117. u32 val;
  1118. /* stop all output */
  1119. clrbits_le32(pllxcr,
  1120. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
  1121. /* stop PLL */
  1122. clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
  1123. /* wait PLL stopped */
  1124. return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
  1125. TIMEOUT_200MS);
  1126. }
  1127. static void pll_config_output(struct stm32mp1_clk_priv *priv,
  1128. int pll_id, u32 *pllcfg)
  1129. {
  1130. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1131. fdt_addr_t rcc = priv->base;
  1132. u32 value;
  1133. value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
  1134. & RCC_PLLNCFGR2_DIVP_MASK;
  1135. value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
  1136. & RCC_PLLNCFGR2_DIVQ_MASK;
  1137. value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
  1138. & RCC_PLLNCFGR2_DIVR_MASK;
  1139. writel(value, rcc + pll[pll_id].pllxcfgr2);
  1140. }
  1141. static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
  1142. u32 *pllcfg, u32 fracv)
  1143. {
  1144. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1145. fdt_addr_t rcc = priv->base;
  1146. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1147. int src;
  1148. ulong refclk;
  1149. u8 ifrge = 0;
  1150. u32 value;
  1151. src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
  1152. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
  1153. (pllcfg[PLLCFG_M] + 1);
  1154. if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
  1155. refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
  1156. debug("invalid refclk = %x\n", (u32)refclk);
  1157. return -EINVAL;
  1158. }
  1159. if (type == PLL_800 && refclk >= 8000000)
  1160. ifrge = 1;
  1161. value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
  1162. & RCC_PLLNCFGR1_DIVN_MASK;
  1163. value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
  1164. & RCC_PLLNCFGR1_DIVM_MASK;
  1165. value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
  1166. & RCC_PLLNCFGR1_IFRGE_MASK;
  1167. writel(value, rcc + pll[pll_id].pllxcfgr1);
  1168. /* fractional configuration: load sigma-delta modulator (SDM) */
  1169. /* Write into FRACV the new fractional value , and FRACLE to 0 */
  1170. writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
  1171. rcc + pll[pll_id].pllxfracr);
  1172. /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
  1173. setbits_le32(rcc + pll[pll_id].pllxfracr,
  1174. RCC_PLLNFRACR_FRACLE);
  1175. pll_config_output(priv, pll_id, pllcfg);
  1176. return 0;
  1177. }
  1178. static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
  1179. {
  1180. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1181. u32 pllxcsg;
  1182. pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
  1183. RCC_PLLNCSGR_MOD_PER_MASK) |
  1184. ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
  1185. RCC_PLLNCSGR_INC_STEP_MASK) |
  1186. ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
  1187. RCC_PLLNCSGR_SSCG_MODE_MASK);
  1188. writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
  1189. }
  1190. static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
  1191. {
  1192. u32 address = priv->base + (clksrc >> 4);
  1193. u32 val;
  1194. int ret;
  1195. clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
  1196. ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
  1197. TIMEOUT_200MS);
  1198. if (ret)
  1199. pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
  1200. clksrc, address, readl(address));
  1201. return ret;
  1202. }
  1203. static void stgen_config(struct stm32mp1_clk_priv *priv)
  1204. {
  1205. int p;
  1206. u32 stgenc, cntfid0;
  1207. ulong rate;
  1208. stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
  1209. cntfid0 = readl(stgenc + STGENC_CNTFID0);
  1210. p = stm32mp1_clk_get_parent(priv, STGEN_K);
  1211. rate = stm32mp1_clk_get(priv, p);
  1212. if (cntfid0 != rate) {
  1213. pr_debug("System Generic Counter (STGEN) update\n");
  1214. clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1215. writel(0x0, stgenc + STGENC_CNTCVL);
  1216. writel(0x0, stgenc + STGENC_CNTCVU);
  1217. writel(rate, stgenc + STGENC_CNTFID0);
  1218. setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1219. __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
  1220. /* need to update gd->arch.timer_rate_hz with new frequency */
  1221. timer_init();
  1222. pr_debug("gd->arch.timer_rate_hz = %x\n",
  1223. (u32)gd->arch.timer_rate_hz);
  1224. pr_debug("Tick = %x\n", (u32)(get_ticks()));
  1225. }
  1226. }
  1227. static int set_clkdiv(unsigned int clkdiv, u32 address)
  1228. {
  1229. u32 val;
  1230. int ret;
  1231. clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
  1232. ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
  1233. TIMEOUT_200MS);
  1234. if (ret)
  1235. pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
  1236. clkdiv, address, readl(address));
  1237. return ret;
  1238. }
  1239. static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
  1240. u32 clksrc, u32 clkdiv)
  1241. {
  1242. u32 address = priv->base + (clksrc >> 4);
  1243. /*
  1244. * binding clksrc : bit15-4 offset
  1245. * bit3: disable
  1246. * bit2-0: MCOSEL[2:0]
  1247. */
  1248. if (clksrc & 0x8) {
  1249. clrbits_le32(address, RCC_MCOCFG_MCOON);
  1250. } else {
  1251. clrsetbits_le32(address,
  1252. RCC_MCOCFG_MCOSRC_MASK,
  1253. clksrc & RCC_MCOCFG_MCOSRC_MASK);
  1254. clrsetbits_le32(address,
  1255. RCC_MCOCFG_MCODIV_MASK,
  1256. clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
  1257. setbits_le32(address, RCC_MCOCFG_MCOON);
  1258. }
  1259. }
  1260. static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
  1261. unsigned int clksrc,
  1262. int lse_css)
  1263. {
  1264. u32 address = priv->base + RCC_BDCR;
  1265. if (readl(address) & RCC_BDCR_RTCCKEN)
  1266. goto skip_rtc;
  1267. if (clksrc == CLK_RTC_DISABLED)
  1268. goto skip_rtc;
  1269. clrsetbits_le32(address,
  1270. RCC_BDCR_RTCSRC_MASK,
  1271. clksrc << RCC_BDCR_RTCSRC_SHIFT);
  1272. setbits_le32(address, RCC_BDCR_RTCCKEN);
  1273. skip_rtc:
  1274. if (lse_css)
  1275. setbits_le32(address, RCC_BDCR_LSECSSON);
  1276. }
  1277. static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
  1278. {
  1279. u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
  1280. u32 value = pkcs & 0xF;
  1281. u32 mask = 0xF;
  1282. if (pkcs & BIT(31)) {
  1283. mask <<= 4;
  1284. value <<= 4;
  1285. }
  1286. clrsetbits_le32(address, mask, value);
  1287. }
  1288. static int stm32mp1_clktree(struct udevice *dev)
  1289. {
  1290. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1291. fdt_addr_t rcc = priv->base;
  1292. unsigned int clksrc[CLKSRC_NB];
  1293. unsigned int clkdiv[CLKDIV_NB];
  1294. unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
  1295. ofnode plloff[_PLL_NB];
  1296. int ret;
  1297. int i, len;
  1298. int lse_css = 0;
  1299. const u32 *pkcs_cell;
  1300. /* check mandatory field */
  1301. ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
  1302. if (ret < 0) {
  1303. debug("field st,clksrc invalid: error %d\n", ret);
  1304. return -FDT_ERR_NOTFOUND;
  1305. }
  1306. ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
  1307. if (ret < 0) {
  1308. debug("field st,clkdiv invalid: error %d\n", ret);
  1309. return -FDT_ERR_NOTFOUND;
  1310. }
  1311. /* check mandatory field in each pll */
  1312. for (i = 0; i < _PLL_NB; i++) {
  1313. char name[12];
  1314. sprintf(name, "st,pll@%d", i);
  1315. plloff[i] = dev_read_subnode(dev, name);
  1316. if (!ofnode_valid(plloff[i]))
  1317. continue;
  1318. ret = ofnode_read_u32_array(plloff[i], "cfg",
  1319. pllcfg[i], PLLCFG_NB);
  1320. if (ret < 0) {
  1321. debug("field cfg invalid: error %d\n", ret);
  1322. return -FDT_ERR_NOTFOUND;
  1323. }
  1324. }
  1325. debug("configuration MCO\n");
  1326. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
  1327. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
  1328. debug("switch ON osillator\n");
  1329. /*
  1330. * switch ON oscillator found in device-tree,
  1331. * HSI already ON after bootrom
  1332. */
  1333. if (priv->osc[_LSI])
  1334. stm32mp1_lsi_set(rcc, 1);
  1335. if (priv->osc[_LSE]) {
  1336. int bypass;
  1337. int lsedrv;
  1338. struct udevice *dev = priv->osc_dev[_LSE];
  1339. bypass = dev_read_bool(dev, "st,bypass");
  1340. lse_css = dev_read_bool(dev, "st,css");
  1341. lsedrv = dev_read_u32_default(dev, "st,drive",
  1342. LSEDRV_MEDIUM_HIGH);
  1343. stm32mp1_lse_enable(rcc, bypass, lsedrv);
  1344. }
  1345. if (priv->osc[_HSE]) {
  1346. int bypass, css;
  1347. struct udevice *dev = priv->osc_dev[_HSE];
  1348. bypass = dev_read_bool(dev, "st,bypass");
  1349. css = dev_read_bool(dev, "st,css");
  1350. stm32mp1_hse_enable(rcc, bypass, css);
  1351. }
  1352. /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
  1353. * => switch on CSI even if node is not present in device tree
  1354. */
  1355. stm32mp1_csi_set(rcc, 1);
  1356. /* come back to HSI */
  1357. debug("come back to HSI\n");
  1358. set_clksrc(priv, CLK_MPU_HSI);
  1359. set_clksrc(priv, CLK_AXI_HSI);
  1360. set_clksrc(priv, CLK_MCU_HSI);
  1361. debug("pll stop\n");
  1362. for (i = 0; i < _PLL_NB; i++)
  1363. pll_stop(priv, i);
  1364. /* configure HSIDIV */
  1365. debug("configure HSIDIV\n");
  1366. if (priv->osc[_HSI]) {
  1367. stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
  1368. stgen_config(priv);
  1369. }
  1370. /* select DIV */
  1371. debug("select DIV\n");
  1372. /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
  1373. writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
  1374. set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
  1375. set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
  1376. set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
  1377. set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
  1378. set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
  1379. set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
  1380. set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
  1381. /* no ready bit for RTC */
  1382. writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
  1383. /* configure PLLs source */
  1384. debug("configure PLLs source\n");
  1385. set_clksrc(priv, clksrc[CLKSRC_PLL12]);
  1386. set_clksrc(priv, clksrc[CLKSRC_PLL3]);
  1387. set_clksrc(priv, clksrc[CLKSRC_PLL4]);
  1388. /* configure and start PLLs */
  1389. debug("configure PLLs\n");
  1390. for (i = 0; i < _PLL_NB; i++) {
  1391. u32 fracv;
  1392. u32 csg[PLLCSG_NB];
  1393. debug("configure PLL %d @ %d\n", i,
  1394. ofnode_to_offset(plloff[i]));
  1395. if (!ofnode_valid(plloff[i]))
  1396. continue;
  1397. fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
  1398. pll_config(priv, i, pllcfg[i], fracv);
  1399. ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
  1400. if (!ret) {
  1401. pll_csg(priv, i, csg);
  1402. } else if (ret != -FDT_ERR_NOTFOUND) {
  1403. debug("invalid csg node for pll@%d res=%d\n", i, ret);
  1404. return ret;
  1405. }
  1406. pll_start(priv, i);
  1407. }
  1408. /* wait and start PLLs ouptut when ready */
  1409. for (i = 0; i < _PLL_NB; i++) {
  1410. if (!ofnode_valid(plloff[i]))
  1411. continue;
  1412. debug("output PLL %d\n", i);
  1413. pll_output(priv, i, pllcfg[i][PLLCFG_O]);
  1414. }
  1415. /* wait LSE ready before to use it */
  1416. if (priv->osc[_LSE])
  1417. stm32mp1_lse_wait(rcc);
  1418. /* configure with expected clock source */
  1419. debug("CLKSRC\n");
  1420. set_clksrc(priv, clksrc[CLKSRC_MPU]);
  1421. set_clksrc(priv, clksrc[CLKSRC_AXI]);
  1422. set_clksrc(priv, clksrc[CLKSRC_MCU]);
  1423. set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
  1424. /* configure PKCK */
  1425. debug("PKCK\n");
  1426. pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
  1427. if (pkcs_cell) {
  1428. bool ckper_disabled = false;
  1429. for (i = 0; i < len / sizeof(u32); i++) {
  1430. u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
  1431. if (pkcs == CLK_CKPER_DISABLED) {
  1432. ckper_disabled = true;
  1433. continue;
  1434. }
  1435. pkcs_config(priv, pkcs);
  1436. }
  1437. /* CKPER is source for some peripheral clock
  1438. * (FMC-NAND / QPSI-NOR) and switching source is allowed
  1439. * only if previous clock is still ON
  1440. * => deactivated CKPER only after switching clock
  1441. */
  1442. if (ckper_disabled)
  1443. pkcs_config(priv, CLK_CKPER_DISABLED);
  1444. }
  1445. /* STGEN clock source can change with CLK_STGEN_XXX */
  1446. stgen_config(priv);
  1447. debug("oscillator off\n");
  1448. /* switch OFF HSI if not found in device-tree */
  1449. if (!priv->osc[_HSI])
  1450. stm32mp1_hsi_set(rcc, 0);
  1451. /* Software Self-Refresh mode (SSR) during DDR initilialization */
  1452. clrsetbits_le32(priv->base + RCC_DDRITFCR,
  1453. RCC_DDRITFCR_DDRCKMOD_MASK,
  1454. RCC_DDRITFCR_DDRCKMOD_SSR <<
  1455. RCC_DDRITFCR_DDRCKMOD_SHIFT);
  1456. return 0;
  1457. }
  1458. #endif /* STM32MP1_CLOCK_TREE_INIT */
  1459. static void stm32mp1_osc_clk_init(const char *name,
  1460. struct stm32mp1_clk_priv *priv,
  1461. int index)
  1462. {
  1463. struct clk clk;
  1464. struct udevice *dev = NULL;
  1465. priv->osc[index] = 0;
  1466. clk.id = 0;
  1467. if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
  1468. if (clk_request(dev, &clk))
  1469. pr_err("%s request", name);
  1470. else
  1471. priv->osc[index] = clk_get_rate(&clk);
  1472. }
  1473. priv->osc_dev[index] = dev;
  1474. }
  1475. static void stm32mp1_osc_init(struct udevice *dev)
  1476. {
  1477. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1478. int i;
  1479. const char *name[NB_OSC] = {
  1480. [_LSI] = "clk-lsi",
  1481. [_LSE] = "clk-lse",
  1482. [_HSI] = "clk-hsi",
  1483. [_HSE] = "clk-hse",
  1484. [_CSI] = "clk-csi",
  1485. [_I2S_CKIN] = "i2s_ckin",
  1486. [_USB_PHY_48] = "ck_usbo_48m"};
  1487. for (i = 0; i < NB_OSC; i++) {
  1488. stm32mp1_osc_clk_init(name[i], priv, i);
  1489. debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
  1490. }
  1491. }
  1492. static int stm32mp1_clk_probe(struct udevice *dev)
  1493. {
  1494. int result = 0;
  1495. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1496. priv->base = dev_read_addr(dev->parent);
  1497. if (priv->base == FDT_ADDR_T_NONE)
  1498. return -EINVAL;
  1499. priv->data = (void *)&stm32mp1_data;
  1500. if (!priv->data->gate || !priv->data->sel ||
  1501. !priv->data->pll)
  1502. return -EINVAL;
  1503. stm32mp1_osc_init(dev);
  1504. #ifdef STM32MP1_CLOCK_TREE_INIT
  1505. /* clock tree init is done only one time, before relocation */
  1506. if (!(gd->flags & GD_FLG_RELOC))
  1507. result = stm32mp1_clktree(dev);
  1508. #endif
  1509. return result;
  1510. }
  1511. static const struct clk_ops stm32mp1_clk_ops = {
  1512. .enable = stm32mp1_clk_enable,
  1513. .disable = stm32mp1_clk_disable,
  1514. .get_rate = stm32mp1_clk_get_rate,
  1515. };
  1516. static const struct udevice_id stm32mp1_clk_ids[] = {
  1517. { .compatible = "st,stm32mp1-rcc-clk" },
  1518. { }
  1519. };
  1520. U_BOOT_DRIVER(stm32mp1_clock) = {
  1521. .name = "stm32mp1_clk",
  1522. .id = UCLASS_CLK,
  1523. .of_match = stm32mp1_clk_ids,
  1524. .ops = &stm32mp1_clk_ops,
  1525. .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
  1526. .probe = stm32mp1_clk_probe,
  1527. };