clk_stm32f.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <stm32_rcc.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/stm32.h>
  12. #include <asm/arch/stm32_pwr.h>
  13. #include <dt-bindings/mfd/stm32f7-rcc.h>
  14. #define RCC_CR_HSION BIT(0)
  15. #define RCC_CR_HSEON BIT(16)
  16. #define RCC_CR_HSERDY BIT(17)
  17. #define RCC_CR_HSEBYP BIT(18)
  18. #define RCC_CR_CSSON BIT(19)
  19. #define RCC_CR_PLLON BIT(24)
  20. #define RCC_CR_PLLRDY BIT(25)
  21. #define RCC_CR_PLLSAION BIT(28)
  22. #define RCC_CR_PLLSAIRDY BIT(29)
  23. #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
  24. #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
  25. #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
  26. #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
  27. #define RCC_PLLCFGR_PLLSRC BIT(22)
  28. #define RCC_PLLCFGR_PLLM_SHIFT 0
  29. #define RCC_PLLCFGR_PLLN_SHIFT 6
  30. #define RCC_PLLCFGR_PLLP_SHIFT 16
  31. #define RCC_PLLCFGR_PLLQ_SHIFT 24
  32. #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
  33. #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
  34. #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
  35. #define RCC_CFGR_SW0 BIT(0)
  36. #define RCC_CFGR_SW1 BIT(1)
  37. #define RCC_CFGR_SW_MASK GENMASK(1, 0)
  38. #define RCC_CFGR_SW_HSI 0
  39. #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
  40. #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
  41. #define RCC_CFGR_SWS0 BIT(2)
  42. #define RCC_CFGR_SWS1 BIT(3)
  43. #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
  44. #define RCC_CFGR_SWS_HSI 0
  45. #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
  46. #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
  47. #define RCC_CFGR_HPRE_SHIFT 4
  48. #define RCC_CFGR_PPRE1_SHIFT 10
  49. #define RCC_CFGR_PPRE2_SHIFT 13
  50. #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
  51. #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
  52. #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
  53. #define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
  54. #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
  55. #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
  56. #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
  57. #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
  58. #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
  59. #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
  60. #define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
  61. #define RCC_DCKCFGRX_TIMPRE BIT(24)
  62. #define RCC_DCKCFGRX_CK48MSEL BIT(27)
  63. #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
  64. #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
  65. #define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
  66. #define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
  67. #define RCC_DCKCFGR_PLLSAIDIVR_2 0
  68. /*
  69. * RCC AHB1ENR specific definitions
  70. */
  71. #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
  72. #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
  73. #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
  74. /*
  75. * RCC APB1ENR specific definitions
  76. */
  77. #define RCC_APB1ENR_TIM2EN BIT(0)
  78. #define RCC_APB1ENR_PWREN BIT(28)
  79. /*
  80. * RCC APB2ENR specific definitions
  81. */
  82. #define RCC_APB2ENR_SYSCFGEN BIT(14)
  83. #define RCC_APB2ENR_SAI1EN BIT(22)
  84. enum pllsai_div {
  85. PLLSAIP,
  86. PLLSAIQ,
  87. PLLSAIR,
  88. };
  89. static const struct stm32_clk_info stm32f4_clk_info = {
  90. /* 180 MHz */
  91. .sys_pll_psc = {
  92. .pll_n = 360,
  93. .pll_p = 2,
  94. .pll_q = 8,
  95. .ahb_psc = AHB_PSC_1,
  96. .apb1_psc = APB_PSC_4,
  97. .apb2_psc = APB_PSC_2,
  98. },
  99. .has_overdrive = false,
  100. .v2 = false,
  101. };
  102. static const struct stm32_clk_info stm32f7_clk_info = {
  103. /* 200 MHz */
  104. .sys_pll_psc = {
  105. .pll_n = 400,
  106. .pll_p = 2,
  107. .pll_q = 8,
  108. .ahb_psc = AHB_PSC_1,
  109. .apb1_psc = APB_PSC_4,
  110. .apb2_psc = APB_PSC_2,
  111. },
  112. .has_overdrive = true,
  113. .v2 = true,
  114. };
  115. struct stm32_clk {
  116. struct stm32_rcc_regs *base;
  117. struct stm32_pwr_regs *pwr_regs;
  118. struct stm32_clk_info info;
  119. unsigned long hse_rate;
  120. };
  121. #ifdef CONFIG_VIDEO_STM32
  122. static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
  123. #endif
  124. static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
  125. static int configure_clocks(struct udevice *dev)
  126. {
  127. struct stm32_clk *priv = dev_get_priv(dev);
  128. struct stm32_rcc_regs *regs = priv->base;
  129. struct stm32_pwr_regs *pwr = priv->pwr_regs;
  130. struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
  131. /* Reset RCC configuration */
  132. setbits_le32(&regs->cr, RCC_CR_HSION);
  133. writel(0, &regs->cfgr); /* Reset CFGR */
  134. clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
  135. | RCC_CR_PLLON | RCC_CR_PLLSAION));
  136. writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
  137. clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
  138. writel(0, &regs->cir); /* Disable all interrupts */
  139. /* Configure for HSE+PLL operation */
  140. setbits_le32(&regs->cr, RCC_CR_HSEON);
  141. while (!(readl(&regs->cr) & RCC_CR_HSERDY))
  142. ;
  143. setbits_le32(&regs->cfgr, ((
  144. sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
  145. | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
  146. | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
  147. /* Configure the main PLL */
  148. setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
  149. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
  150. sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
  151. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
  152. sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
  153. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
  154. ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
  155. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
  156. sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
  157. /* configure SDMMC clock */
  158. if (priv->info.v2) { /*stm32f7 case */
  159. /* select PLLQ as 48MHz clock source */
  160. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
  161. /* select 48MHz as SDMMC1 clock source */
  162. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
  163. /* select 48MHz as SDMMC2 clock source */
  164. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
  165. } else { /* stm32f4 case */
  166. /* select PLLQ as 48MHz clock source */
  167. clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
  168. /* select 48MHz as SDMMC1 clock source */
  169. clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
  170. }
  171. #ifdef CONFIG_VIDEO_STM32
  172. /*
  173. * Configure the SAI PLL to generate LTDC pixel clock
  174. */
  175. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
  176. RCC_PLLSAICFGR_PLLSAIR_3);
  177. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
  178. 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
  179. clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
  180. RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
  181. #endif
  182. /* Enable the main PLL */
  183. setbits_le32(&regs->cr, RCC_CR_PLLON);
  184. while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
  185. ;
  186. #ifdef CONFIG_VIDEO_STM32
  187. /* Enable the SAI PLL */
  188. setbits_le32(&regs->cr, RCC_CR_PLLSAION);
  189. while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
  190. ;
  191. #endif
  192. setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
  193. if (priv->info.has_overdrive) {
  194. /*
  195. * Enable high performance mode
  196. * System frequency up to 200 MHz
  197. */
  198. setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
  199. /* Infinite wait! */
  200. while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
  201. ;
  202. /* Enable the Over-drive switch */
  203. setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
  204. /* Infinite wait! */
  205. while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
  206. ;
  207. }
  208. stm32_flash_latency_cfg(5);
  209. clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
  210. setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
  211. while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
  212. RCC_CFGR_SWS_PLL)
  213. ;
  214. #ifdef CONFIG_ETH_DESIGNWARE
  215. /* gate the SYSCFG clock, needed to set RMII ethernet interface */
  216. setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
  217. #endif
  218. return 0;
  219. }
  220. static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
  221. {
  222. struct stm32_rcc_regs *regs = priv->base;
  223. if (priv->info.v2) /*stm32f7 case */
  224. return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
  225. else
  226. return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
  227. }
  228. static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
  229. {
  230. struct stm32_rcc_regs *regs = priv->base;
  231. u16 pllm, pllsain;
  232. pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
  233. pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
  234. >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
  235. return ((priv->hse_rate / pllm) * pllsain);
  236. }
  237. static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
  238. enum pllsai_div output)
  239. {
  240. struct stm32_rcc_regs *regs = priv->base;
  241. u16 pll_div_output;
  242. switch (output) {
  243. case PLLSAIP:
  244. pll_div_output = ((((readl(&regs->pllsaicfgr)
  245. & RCC_PLLSAICFGR_PLLSAIP_MASK)
  246. >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
  247. break;
  248. case PLLSAIQ:
  249. pll_div_output = (readl(&regs->pllsaicfgr)
  250. & RCC_PLLSAICFGR_PLLSAIQ_MASK)
  251. >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
  252. break;
  253. case PLLSAIR:
  254. pll_div_output = (readl(&regs->pllsaicfgr)
  255. & RCC_PLLSAICFGR_PLLSAIR_MASK)
  256. >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
  257. break;
  258. default:
  259. pr_err("incorrect PLLSAI output %d\n", output);
  260. return -EINVAL;
  261. }
  262. return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
  263. }
  264. static bool stm32_get_timpre(struct stm32_clk *priv)
  265. {
  266. struct stm32_rcc_regs *regs = priv->base;
  267. u32 val;
  268. if (priv->info.v2) /*stm32f7 case */
  269. val = readl(&regs->dckcfgr2);
  270. else
  271. val = readl(&regs->dckcfgr);
  272. /* get timer prescaler */
  273. return !!(val & RCC_DCKCFGRX_TIMPRE);
  274. }
  275. static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
  276. {
  277. u8 shift;
  278. /* Prescaler table lookups for clock computation */
  279. u8 ahb_psc_table[16] = {
  280. 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
  281. };
  282. shift = ahb_psc_table[(
  283. (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
  284. >> RCC_CFGR_HPRE_SHIFT)];
  285. return sysclk >> shift;
  286. };
  287. static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
  288. {
  289. /* Prescaler table lookups for clock computation */
  290. u8 apb_psc_table[8] = {
  291. 0, 0, 0, 0, 1, 2, 3, 4
  292. };
  293. if (apb == APB1)
  294. return apb_psc_table[(
  295. (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
  296. >> RCC_CFGR_PPRE1_SHIFT)];
  297. else /* APB2 */
  298. return apb_psc_table[(
  299. (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
  300. >> RCC_CFGR_PPRE2_SHIFT)];
  301. };
  302. static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
  303. enum apb apb)
  304. {
  305. struct stm32_rcc_regs *regs = priv->base;
  306. u8 shift = stm32_get_apb_shift(regs, apb);
  307. if (stm32_get_timpre(priv))
  308. /*
  309. * if APB prescaler is configured to a
  310. * division factor of 1, 2 or 4
  311. */
  312. switch (shift) {
  313. case 0:
  314. case 1:
  315. case 2:
  316. return stm32_get_hclk_rate(regs, sysclk);
  317. default:
  318. return (sysclk >> shift) * 4;
  319. }
  320. else
  321. /*
  322. * if APB prescaler is configured to a
  323. * division factor of 1
  324. */
  325. if (shift == 0)
  326. return sysclk;
  327. else
  328. return (sysclk >> shift) * 2;
  329. };
  330. static ulong stm32_clk_get_rate(struct clk *clk)
  331. {
  332. struct stm32_clk *priv = dev_get_priv(clk->dev);
  333. struct stm32_rcc_regs *regs = priv->base;
  334. u32 sysclk = 0;
  335. u32 vco;
  336. u32 sdmmcxsel_bit;
  337. u32 saidivr;
  338. u32 pllsai_rate;
  339. u16 pllm, plln, pllp, pllq;
  340. if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
  341. RCC_CFGR_SWS_PLL) {
  342. pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
  343. plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
  344. >> RCC_PLLCFGR_PLLN_SHIFT);
  345. pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
  346. >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
  347. pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
  348. >> RCC_PLLCFGR_PLLQ_SHIFT);
  349. vco = (priv->hse_rate / pllm) * plln;
  350. sysclk = vco / pllp;
  351. } else {
  352. return -EINVAL;
  353. }
  354. switch (clk->id) {
  355. /*
  356. * AHB CLOCK: 3 x 32 bits consecutive registers are used :
  357. * AHB1, AHB2 and AHB3
  358. */
  359. case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
  360. return stm32_get_hclk_rate(regs, sysclk);
  361. /* APB1 CLOCK */
  362. case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
  363. /* For timer clock, an additionnal prescaler is used*/
  364. switch (clk->id) {
  365. case STM32F7_APB1_CLOCK(TIM2):
  366. case STM32F7_APB1_CLOCK(TIM3):
  367. case STM32F7_APB1_CLOCK(TIM4):
  368. case STM32F7_APB1_CLOCK(TIM5):
  369. case STM32F7_APB1_CLOCK(TIM6):
  370. case STM32F7_APB1_CLOCK(TIM7):
  371. case STM32F7_APB1_CLOCK(TIM12):
  372. case STM32F7_APB1_CLOCK(TIM13):
  373. case STM32F7_APB1_CLOCK(TIM14):
  374. return stm32_get_timer_rate(priv, sysclk, APB1);
  375. }
  376. return (sysclk >> stm32_get_apb_shift(regs, APB1));
  377. /* APB2 CLOCK */
  378. case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
  379. switch (clk->id) {
  380. /*
  381. * particular case for SDMMC1 and SDMMC2 :
  382. * 48Mhz source clock can be from main PLL or from
  383. * PLLSAIP
  384. */
  385. case STM32F7_APB2_CLOCK(SDMMC1):
  386. case STM32F7_APB2_CLOCK(SDMMC2):
  387. if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
  388. sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
  389. else
  390. sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
  391. if (readl(&regs->dckcfgr2) & sdmmcxsel_bit)
  392. /* System clock is selected as SDMMC1 clock */
  393. return sysclk;
  394. /*
  395. * 48 MHz can be generated by either PLLSAIP
  396. * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
  397. */
  398. if (stm32_clk_get_ck48msel(priv))
  399. return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
  400. else
  401. return (vco / pllq);
  402. break;
  403. /* For timer clock, an additionnal prescaler is used*/
  404. case STM32F7_APB2_CLOCK(TIM1):
  405. case STM32F7_APB2_CLOCK(TIM8):
  406. case STM32F7_APB2_CLOCK(TIM9):
  407. case STM32F7_APB2_CLOCK(TIM10):
  408. case STM32F7_APB2_CLOCK(TIM11):
  409. return stm32_get_timer_rate(priv, sysclk, APB2);
  410. break;
  411. /* particular case for LTDC clock */
  412. case STM32F7_APB2_CLOCK(LTDC):
  413. saidivr = readl(&regs->dckcfgr);
  414. saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
  415. >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
  416. pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
  417. return pllsai_rate / pllsaidivr_table[saidivr];
  418. }
  419. return (sysclk >> stm32_get_apb_shift(regs, APB2));
  420. default:
  421. pr_err("clock index %ld out of range\n", clk->id);
  422. return -EINVAL;
  423. }
  424. }
  425. static ulong stm32_set_rate(struct clk *clk, ulong rate)
  426. {
  427. #ifdef CONFIG_VIDEO_STM32
  428. struct stm32_clk *priv = dev_get_priv(clk->dev);
  429. struct stm32_rcc_regs *regs = priv->base;
  430. u32 pllsair_rate, pllsai_vco_rate, current_rate;
  431. u32 best_div, best_diff, diff;
  432. u16 div;
  433. u8 best_plldivr, best_pllsaidivr;
  434. u8 i, j;
  435. bool found = false;
  436. /* Only set_rate for LTDC clock is implemented */
  437. if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
  438. pr_err("set_rate not implemented for clock index %ld\n",
  439. clk->id);
  440. return 0;
  441. }
  442. if (rate == stm32_clk_get_rate(clk))
  443. /* already set to requested rate */
  444. return rate;
  445. /* get the current PLLSAIR output freq */
  446. pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
  447. best_div = pllsair_rate / rate;
  448. /* look into pllsaidivr_table if this divider is available*/
  449. for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
  450. if (best_div == pllsaidivr_table[i]) {
  451. /* set pll_saidivr with found value */
  452. clrsetbits_le32(&regs->dckcfgr,
  453. RCC_DCKCFGR_PLLSAIDIVR_MASK,
  454. pllsaidivr_table[i]);
  455. return rate;
  456. }
  457. /*
  458. * As no pllsaidivr value is suitable to obtain requested freq,
  459. * test all combination of pllsaidivr * pllsair and find the one
  460. * which give freq closest to requested rate.
  461. */
  462. pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
  463. best_diff = ULONG_MAX;
  464. best_pllsaidivr = 0;
  465. best_plldivr = 0;
  466. /*
  467. * start at index 2 of plldivr_table as divider value at index 0
  468. * and 1 are 0)
  469. */
  470. for (i = 2; i < sizeof(plldivr_table); i++) {
  471. for (j = 0; j < sizeof(pllsaidivr_table); j++) {
  472. div = plldivr_table[i] * pllsaidivr_table[j];
  473. current_rate = pllsai_vco_rate / div;
  474. /* perfect combination is found ? */
  475. if (current_rate == rate) {
  476. best_pllsaidivr = j;
  477. best_plldivr = i;
  478. found = true;
  479. break;
  480. }
  481. diff = (current_rate > rate) ?
  482. current_rate - rate : rate - current_rate;
  483. /* found a better combination ? */
  484. if (diff < best_diff) {
  485. best_diff = diff;
  486. best_pllsaidivr = j;
  487. best_plldivr = i;
  488. }
  489. }
  490. if (found)
  491. break;
  492. }
  493. /* Disable the SAI PLL */
  494. clrbits_le32(&regs->cr, RCC_CR_PLLSAION);
  495. /* set pll_saidivr with found value */
  496. clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
  497. best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
  498. /* set pllsair with found value */
  499. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
  500. plldivr_table[best_plldivr]
  501. << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
  502. /* Enable the SAI PLL */
  503. setbits_le32(&regs->cr, RCC_CR_PLLSAION);
  504. while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
  505. ;
  506. div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
  507. return pllsai_vco_rate / div;
  508. #else
  509. return 0;
  510. #endif
  511. }
  512. static int stm32_clk_enable(struct clk *clk)
  513. {
  514. struct stm32_clk *priv = dev_get_priv(clk->dev);
  515. struct stm32_rcc_regs *regs = priv->base;
  516. u32 offset = clk->id / 32;
  517. u32 bit_index = clk->id % 32;
  518. debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
  519. __func__, clk->id, offset, bit_index);
  520. setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
  521. return 0;
  522. }
  523. static int stm32_clk_probe(struct udevice *dev)
  524. {
  525. struct ofnode_phandle_args args;
  526. struct udevice *fixed_clock_dev = NULL;
  527. struct clk clk;
  528. int err;
  529. debug("%s\n", __func__);
  530. struct stm32_clk *priv = dev_get_priv(dev);
  531. fdt_addr_t addr;
  532. addr = dev_read_addr(dev);
  533. if (addr == FDT_ADDR_T_NONE)
  534. return -EINVAL;
  535. priv->base = (struct stm32_rcc_regs *)addr;
  536. switch (dev_get_driver_data(dev)) {
  537. case STM32F4:
  538. memcpy(&priv->info, &stm32f4_clk_info,
  539. sizeof(struct stm32_clk_info));
  540. break;
  541. case STM32F7:
  542. memcpy(&priv->info, &stm32f7_clk_info,
  543. sizeof(struct stm32_clk_info));
  544. break;
  545. default:
  546. return -EINVAL;
  547. }
  548. /* retrieve HSE frequency (external oscillator) */
  549. err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
  550. &fixed_clock_dev);
  551. if (err) {
  552. pr_err("Can't find fixed clock (%d)", err);
  553. return err;
  554. }
  555. err = clk_request(fixed_clock_dev, &clk);
  556. if (err) {
  557. pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
  558. err);
  559. return err;
  560. }
  561. /*
  562. * set pllm factor accordingly to the external oscillator
  563. * frequency (HSE). For STM32F4 and STM32F7, we want VCO
  564. * freq at 1MHz
  565. * if input PLL frequency is 25Mhz, divide it by 25
  566. */
  567. clk.id = 0;
  568. priv->hse_rate = clk_get_rate(&clk);
  569. if (priv->hse_rate < 1000000) {
  570. pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
  571. priv->hse_rate);
  572. return -EINVAL;
  573. }
  574. priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
  575. if (priv->info.has_overdrive) {
  576. err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
  577. &args);
  578. if (err) {
  579. debug("%s: can't find syscon device (%d)\n", __func__,
  580. err);
  581. return err;
  582. }
  583. priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
  584. }
  585. configure_clocks(dev);
  586. return 0;
  587. }
  588. static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  589. {
  590. debug("%s(clk=%p)\n", __func__, clk);
  591. if (args->args_count != 2) {
  592. debug("Invaild args_count: %d\n", args->args_count);
  593. return -EINVAL;
  594. }
  595. if (args->args_count)
  596. clk->id = args->args[1];
  597. else
  598. clk->id = 0;
  599. return 0;
  600. }
  601. static struct clk_ops stm32_clk_ops = {
  602. .of_xlate = stm32_clk_of_xlate,
  603. .enable = stm32_clk_enable,
  604. .get_rate = stm32_clk_get_rate,
  605. .set_rate = stm32_set_rate,
  606. };
  607. U_BOOT_DRIVER(stm32fx_clk) = {
  608. .name = "stm32fx_rcc_clock",
  609. .id = UCLASS_CLK,
  610. .ops = &stm32_clk_ops,
  611. .probe = stm32_clk_probe,
  612. .priv_auto_alloc_size = sizeof(struct stm32_clk),
  613. .flags = DM_FLAG_PRE_RELOC,
  614. };