clk-hsdk-cgu.c 20 KB

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  1. /*
  2. * Synopsys HSDK SDP CGU clock driver
  3. *
  4. * Copyright (C) 2017 Synopsys
  5. * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <common.h>
  12. #include <clk-uclass.h>
  13. #include <div64.h>
  14. #include <dm.h>
  15. #include <linux/io.h>
  16. /*
  17. * Synopsys ARC HSDK clock tree.
  18. *
  19. * ------------------
  20. * | 33.33 MHz xtal |
  21. * ------------------
  22. * |
  23. * | -----------
  24. * |-->| ARC PLL |
  25. * | -----------
  26. * | |
  27. * | |-->|CGU_ARC_IDIV|----------->
  28. * | |-->|CREG_CORE_IF_DIV|------->
  29. * |
  30. * | --------------
  31. * |-->| SYSTEM PLL |
  32. * | --------------
  33. * | |
  34. * | |-->|CGU_SYS_IDIV_APB|------->
  35. * | |-->|CGU_SYS_IDIV_AXI|------->
  36. * | |-->|CGU_SYS_IDIV_*|--------->
  37. * | |-->|CGU_SYS_IDIV_EBI_REF|--->
  38. * |
  39. * | --------------
  40. * |-->| TUNNEL PLL |
  41. * | --------------
  42. * | |
  43. * | |-->|CGU_TUN_IDIV_TUN|----------->
  44. * | |-->|CGU_TUN_IDIV_ROM|----------->
  45. * | |-->|CGU_TUN_IDIV_PWM|----------->
  46. * |
  47. * | ------------
  48. * |-->| HDMI PLL |
  49. * | ------------
  50. * | |
  51. * | |-->|CGU_HDMI_IDIV_APB|------>
  52. * |
  53. * | -----------
  54. * |-->| DDR PLL |
  55. * -----------
  56. * |
  57. * |---------------------------->
  58. */
  59. #define CGU_ARC_IDIV 0x080
  60. #define CGU_TUN_IDIV_TUN 0x380
  61. #define CGU_TUN_IDIV_ROM 0x390
  62. #define CGU_TUN_IDIV_PWM 0x3A0
  63. #define CGU_HDMI_IDIV_APB 0x480
  64. #define CGU_SYS_IDIV_APB 0x180
  65. #define CGU_SYS_IDIV_AXI 0x190
  66. #define CGU_SYS_IDIV_ETH 0x1A0
  67. #define CGU_SYS_IDIV_USB 0x1B0
  68. #define CGU_SYS_IDIV_SDIO 0x1C0
  69. #define CGU_SYS_IDIV_HDMI 0x1D0
  70. #define CGU_SYS_IDIV_GFX_CORE 0x1E0
  71. #define CGU_SYS_IDIV_GFX_DMA 0x1F0
  72. #define CGU_SYS_IDIV_GFX_CFG 0x200
  73. #define CGU_SYS_IDIV_DMAC_CORE 0x210
  74. #define CGU_SYS_IDIV_DMAC_CFG 0x220
  75. #define CGU_SYS_IDIV_SDIO_REF 0x230
  76. #define CGU_SYS_IDIV_SPI_REF 0x240
  77. #define CGU_SYS_IDIV_I2C_REF 0x250
  78. #define CGU_SYS_IDIV_UART_REF 0x260
  79. #define CGU_SYS_IDIV_EBI_REF 0x270
  80. #define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
  81. #define CGU_ARC_PLL 0x0
  82. #define CGU_SYS_PLL 0x10
  83. #define CGU_DDR_PLL 0x20
  84. #define CGU_TUN_PLL 0x30
  85. #define CGU_HDMI_PLL 0x40
  86. #define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
  87. #define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
  88. #define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
  89. #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
  90. #define CGU_PLL_CTRL_ODIV_SHIFT 2
  91. #define CGU_PLL_CTRL_IDIV_SHIFT 4
  92. #define CGU_PLL_CTRL_FBDIV_SHIFT 9
  93. #define CGU_PLL_CTRL_BAND_SHIFT 20
  94. #define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
  95. #define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
  96. #define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
  97. #define CGU_PLL_CTRL_PD BIT(0)
  98. #define CGU_PLL_CTRL_BYPASS BIT(1)
  99. #define CGU_PLL_STATUS_LOCK BIT(0)
  100. #define CGU_PLL_STATUS_ERR BIT(1)
  101. #define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
  102. #define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
  103. #define CORE_IF_CLK_THRESHOLD_HZ 500000000
  104. #define CREG_CORE_IF_CLK_DIV_1 0x0
  105. #define CREG_CORE_IF_CLK_DIV_2 0x1
  106. #define MIN_PLL_RATE 100000000 /* 100 MHz */
  107. #define PARENT_RATE 33333333 /* fixed clock - xtal */
  108. #define CGU_MAX_CLOCKS 26
  109. #define CGU_SYS_CLOCKS 16
  110. #define MAX_AXI_CLOCKS 4
  111. #define CGU_TUN_CLOCKS 3
  112. #define MAX_TUN_CLOCKS 6
  113. struct hsdk_tun_idiv_cfg {
  114. u32 oft;
  115. u8 val[MAX_TUN_CLOCKS];
  116. };
  117. struct hsdk_tun_clk_cfg {
  118. const u32 clk_rate[MAX_TUN_CLOCKS];
  119. const u32 pll_rate[MAX_TUN_CLOCKS];
  120. const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
  121. };
  122. static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
  123. { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
  124. { 600000000, 600000000, 600000000, 600000000, 700000000, 600000000 }, {
  125. { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
  126. { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
  127. { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } }
  128. }
  129. };
  130. struct hsdk_sys_idiv_cfg {
  131. u32 oft;
  132. u8 val[MAX_AXI_CLOCKS];
  133. };
  134. struct hsdk_axi_clk_cfg {
  135. const u32 clk_rate[MAX_AXI_CLOCKS];
  136. const u32 pll_rate[MAX_AXI_CLOCKS];
  137. const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
  138. };
  139. static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
  140. { 200000000, 400000000, 600000000, 800000000 },
  141. { 800000000, 800000000, 600000000, 800000000 }, {
  142. { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
  143. { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
  144. { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
  145. { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
  146. { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
  147. { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
  148. { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
  149. { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
  150. { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
  151. { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
  152. { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
  153. { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
  154. { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
  155. { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
  156. { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
  157. { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
  158. }
  159. };
  160. struct hsdk_pll_cfg {
  161. u32 rate;
  162. u32 idiv;
  163. u32 fbdiv;
  164. u32 odiv;
  165. u32 band;
  166. };
  167. static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
  168. { 100000000, 0, 11, 3, 0 },
  169. { 125000000, 0, 14, 3, 0 },
  170. { 133000000, 0, 15, 3, 0 },
  171. { 150000000, 0, 17, 3, 0 },
  172. { 200000000, 1, 47, 3, 0 },
  173. { 233000000, 1, 27, 2, 0 },
  174. { 300000000, 1, 35, 2, 0 },
  175. { 333000000, 1, 39, 2, 0 },
  176. { 400000000, 1, 47, 2, 0 },
  177. { 500000000, 0, 14, 1, 0 },
  178. { 600000000, 0, 17, 1, 0 },
  179. { 700000000, 0, 20, 1, 0 },
  180. { 800000000, 0, 23, 1, 0 },
  181. { 900000000, 1, 26, 0, 0 },
  182. { 1000000000, 1, 29, 0, 0 },
  183. { 1100000000, 1, 32, 0, 0 },
  184. { 1200000000, 1, 35, 0, 0 },
  185. { 1300000000, 1, 38, 0, 0 },
  186. { 1400000000, 1, 41, 0, 0 },
  187. { 1500000000, 1, 44, 0, 0 },
  188. { 1600000000, 1, 47, 0, 0 },
  189. {}
  190. };
  191. static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
  192. { 297000000, 0, 21, 2, 0 },
  193. { 540000000, 0, 19, 1, 0 },
  194. { 594000000, 0, 21, 1, 0 },
  195. {}
  196. };
  197. struct hsdk_cgu_clk {
  198. /* CGU block register */
  199. void __iomem *cgu_regs;
  200. /* CREG block register */
  201. void __iomem *creg_regs;
  202. /* PLLs registers */
  203. void __iomem *regs;
  204. /* PLLs special registers */
  205. void __iomem *spec_regs;
  206. /* PLLs devdata */
  207. const struct hsdk_pll_devdata *pll_devdata;
  208. /* Dividers registers */
  209. void __iomem *idiv_regs;
  210. };
  211. struct hsdk_pll_devdata {
  212. const struct hsdk_pll_cfg *pll_cfg;
  213. int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
  214. const struct hsdk_pll_cfg *cfg);
  215. };
  216. static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
  217. const struct hsdk_pll_cfg *);
  218. static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
  219. const struct hsdk_pll_cfg *);
  220. static const struct hsdk_pll_devdata core_pll_dat = {
  221. .pll_cfg = asdt_pll_cfg,
  222. .update_rate = hsdk_pll_core_update_rate,
  223. };
  224. static const struct hsdk_pll_devdata sdt_pll_dat = {
  225. .pll_cfg = asdt_pll_cfg,
  226. .update_rate = hsdk_pll_comm_update_rate,
  227. };
  228. static const struct hsdk_pll_devdata hdmi_pll_dat = {
  229. .pll_cfg = hdmi_pll_cfg,
  230. .update_rate = hsdk_pll_comm_update_rate,
  231. };
  232. static ulong idiv_set(struct clk *, ulong);
  233. static ulong cpu_clk_set(struct clk *, ulong);
  234. static ulong axi_clk_set(struct clk *, ulong);
  235. static ulong tun_clk_set(struct clk *, ulong);
  236. static ulong idiv_get(struct clk *);
  237. static int idiv_off(struct clk *);
  238. static ulong pll_set(struct clk *, ulong);
  239. static ulong pll_get(struct clk *);
  240. struct hsdk_cgu_clock_map {
  241. u32 cgu_pll_oft;
  242. u32 creg_div_oft;
  243. u32 cgu_div_oft;
  244. const struct hsdk_pll_devdata *pll_devdata;
  245. ulong (*get_rate)(struct clk *clk);
  246. ulong (*set_rate)(struct clk *clk, ulong rate);
  247. int (*disable)(struct clk *clk);
  248. };
  249. static const struct hsdk_cgu_clock_map clock_map[] = {
  250. { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
  251. { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
  252. { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
  253. { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
  254. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  255. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
  256. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  257. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  258. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  259. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  260. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  261. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  262. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  263. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  264. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  265. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  266. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  267. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  268. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  269. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  270. { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
  271. { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
  272. { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  273. { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  274. { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
  275. { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
  276. };
  277. static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
  278. {
  279. iowrite32(val, clk->idiv_regs);
  280. }
  281. static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
  282. {
  283. return ioread32(clk->idiv_regs);
  284. }
  285. static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
  286. {
  287. iowrite32(val, clk->regs + reg);
  288. }
  289. static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
  290. {
  291. return ioread32(clk->regs + reg);
  292. }
  293. static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
  294. {
  295. iowrite32(val, clk->spec_regs + reg);
  296. }
  297. static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
  298. {
  299. return ioread32(clk->spec_regs + reg);
  300. }
  301. static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
  302. const struct hsdk_pll_cfg *cfg)
  303. {
  304. u32 val = 0;
  305. /* Powerdown and Bypass bits should be cleared */
  306. val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
  307. val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
  308. val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
  309. val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
  310. pr_debug("write configurarion: %#x\n", val);
  311. hsdk_pll_write(clk, CGU_PLL_CTRL, val);
  312. }
  313. static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
  314. {
  315. return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
  316. }
  317. static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
  318. {
  319. return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
  320. }
  321. static ulong pll_get(struct clk *sclk)
  322. {
  323. u32 val;
  324. u64 rate;
  325. u32 idiv, fbdiv, odiv;
  326. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  327. val = hsdk_pll_read(clk, CGU_PLL_CTRL);
  328. pr_debug("current configurarion: %#x\n", val);
  329. /* Check if PLL is disabled */
  330. if (val & CGU_PLL_CTRL_PD)
  331. return 0;
  332. /* Check if PLL is bypassed */
  333. if (val & CGU_PLL_CTRL_BYPASS)
  334. return PARENT_RATE;
  335. /* input divider = reg.idiv + 1 */
  336. idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
  337. /* fb divider = 2*(reg.fbdiv + 1) */
  338. fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
  339. /* output divider = 2^(reg.odiv) */
  340. odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
  341. rate = (u64)PARENT_RATE * fbdiv;
  342. do_div(rate, idiv * odiv);
  343. return rate;
  344. }
  345. static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
  346. {
  347. int i;
  348. unsigned long best_rate;
  349. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  350. const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
  351. if (pll_cfg[0].rate == 0)
  352. return -EINVAL;
  353. best_rate = pll_cfg[0].rate;
  354. for (i = 1; pll_cfg[i].rate != 0; i++) {
  355. if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
  356. best_rate = pll_cfg[i].rate;
  357. }
  358. pr_debug("chosen best rate: %lu\n", best_rate);
  359. return best_rate;
  360. }
  361. static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
  362. unsigned long rate,
  363. const struct hsdk_pll_cfg *cfg)
  364. {
  365. hsdk_pll_set_cfg(clk, cfg);
  366. /*
  367. * Wait until CGU relocks and check error status.
  368. * If after timeout CGU is unlocked yet return error.
  369. */
  370. udelay(HSDK_PLL_MAX_LOCK_TIME);
  371. if (!hsdk_pll_is_locked(clk))
  372. return -ETIMEDOUT;
  373. if (hsdk_pll_is_err(clk))
  374. return -EINVAL;
  375. return 0;
  376. }
  377. static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
  378. unsigned long rate,
  379. const struct hsdk_pll_cfg *cfg)
  380. {
  381. /*
  382. * When core clock exceeds 500MHz, the divider for the interface
  383. * clock must be programmed to div-by-2.
  384. */
  385. if (rate > CORE_IF_CLK_THRESHOLD_HZ)
  386. hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
  387. hsdk_pll_set_cfg(clk, cfg);
  388. /*
  389. * Wait until CGU relocks and check error status.
  390. * If after timeout CGU is unlocked yet return error.
  391. */
  392. udelay(HSDK_PLL_MAX_LOCK_TIME);
  393. if (!hsdk_pll_is_locked(clk))
  394. return -ETIMEDOUT;
  395. if (hsdk_pll_is_err(clk))
  396. return -EINVAL;
  397. /*
  398. * Program divider to div-by-1 if we succesfuly set core clock below
  399. * 500MHz threshold.
  400. */
  401. if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
  402. hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
  403. return 0;
  404. }
  405. static ulong pll_set(struct clk *sclk, ulong rate)
  406. {
  407. int i;
  408. unsigned long best_rate;
  409. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  410. const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
  411. best_rate = hsdk_pll_round_rate(sclk, rate);
  412. for (i = 0; pll_cfg[i].rate != 0; i++) {
  413. if (pll_cfg[i].rate == best_rate) {
  414. return clk->pll_devdata->update_rate(clk, best_rate,
  415. &pll_cfg[i]);
  416. }
  417. }
  418. pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
  419. return -EINVAL;
  420. }
  421. static int idiv_off(struct clk *sclk)
  422. {
  423. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  424. hsdk_idiv_write(clk, 0);
  425. return 0;
  426. }
  427. static ulong idiv_get(struct clk *sclk)
  428. {
  429. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  430. ulong parent_rate = pll_get(sclk);
  431. u32 div_factor = hsdk_idiv_read(clk);
  432. div_factor &= CGU_IDIV_MASK;
  433. pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
  434. if (div_factor == 0)
  435. return 0;
  436. return parent_rate / div_factor;
  437. }
  438. /* Special behavior: wen we set this clock we set both idiv and pll */
  439. static ulong cpu_clk_set(struct clk *sclk, ulong rate)
  440. {
  441. ulong ret;
  442. ret = pll_set(sclk, rate);
  443. idiv_set(sclk, rate);
  444. return ret;
  445. }
  446. /* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
  447. static ulong axi_clk_set(struct clk *sclk, ulong rate)
  448. {
  449. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  450. ulong pll_rate;
  451. int i, freq_idx = -1;
  452. ulong ret = 0;
  453. pll_rate = pll_get(sclk);
  454. for (i = 0; i < MAX_AXI_CLOCKS; i++) {
  455. if (axi_clk_cfg.clk_rate[i] == rate) {
  456. freq_idx = i;
  457. break;
  458. }
  459. }
  460. if (freq_idx < 0) {
  461. pr_err("axi clk: invalid rate=%ld Hz\n", rate);
  462. return -EINVAL;
  463. }
  464. /* configure PLL before dividers */
  465. if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
  466. ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
  467. /* configure SYS dividers */
  468. for (i = 0; i < CGU_SYS_CLOCKS; i++) {
  469. clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
  470. hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
  471. }
  472. /* configure PLL after dividers */
  473. if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
  474. ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
  475. return ret;
  476. }
  477. static ulong tun_clk_set(struct clk *sclk, ulong rate)
  478. {
  479. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  480. ulong pll_rate;
  481. int i, freq_idx = -1;
  482. ulong ret = 0;
  483. pll_rate = pll_get(sclk);
  484. for (i = 0; i < MAX_TUN_CLOCKS; i++) {
  485. if (tun_clk_cfg.clk_rate[i] == rate) {
  486. freq_idx = i;
  487. break;
  488. }
  489. }
  490. if (freq_idx < 0) {
  491. pr_err("tun clk: invalid rate=%ld Hz\n", rate);
  492. return -EINVAL;
  493. }
  494. /* configure PLL before dividers */
  495. if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
  496. ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
  497. /* configure SYS dividers */
  498. for (i = 0; i < CGU_TUN_CLOCKS; i++) {
  499. clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
  500. hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
  501. }
  502. /* configure PLL after dividers */
  503. if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
  504. ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
  505. return ret;
  506. }
  507. static ulong idiv_set(struct clk *sclk, ulong rate)
  508. {
  509. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  510. ulong parent_rate = pll_get(sclk);
  511. u32 div_factor;
  512. div_factor = parent_rate / rate;
  513. if (abs(rate - parent_rate / (div_factor + 1)) <=
  514. abs(rate - parent_rate / div_factor)) {
  515. div_factor += 1;
  516. }
  517. if (div_factor & ~CGU_IDIV_MASK) {
  518. pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
  519. rate, parent_rate, div_factor, CGU_IDIV_MASK);
  520. div_factor = CGU_IDIV_MASK;
  521. }
  522. if (div_factor == 0) {
  523. pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
  524. rate, parent_rate, div_factor);
  525. div_factor = 1;
  526. }
  527. hsdk_idiv_write(clk, div_factor);
  528. return 0;
  529. }
  530. static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
  531. {
  532. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  533. if (sclk->id >= CGU_MAX_CLOCKS)
  534. return -EINVAL;
  535. clk->pll_devdata = clock_map[sclk->id].pll_devdata;
  536. clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
  537. clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft;
  538. clk->idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
  539. return 0;
  540. }
  541. static ulong hsdk_cgu_get_rate(struct clk *sclk)
  542. {
  543. if (hsdk_prepare_clock_tree_branch(sclk))
  544. return -EINVAL;
  545. return clock_map[sclk->id].get_rate(sclk);
  546. }
  547. static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
  548. {
  549. if (hsdk_prepare_clock_tree_branch(sclk))
  550. return -EINVAL;
  551. return clock_map[sclk->id].set_rate(sclk, rate);
  552. }
  553. static int hsdk_cgu_disable(struct clk *sclk)
  554. {
  555. if (hsdk_prepare_clock_tree_branch(sclk))
  556. return -EINVAL;
  557. if (clock_map[sclk->id].disable)
  558. return clock_map[sclk->id].disable(sclk);
  559. return -ENOTSUPP;
  560. }
  561. static const struct clk_ops hsdk_cgu_ops = {
  562. .set_rate = hsdk_cgu_set_rate,
  563. .get_rate = hsdk_cgu_get_rate,
  564. .disable = hsdk_cgu_disable,
  565. };
  566. static int hsdk_cgu_clk_probe(struct udevice *dev)
  567. {
  568. struct hsdk_cgu_clk *pll_clk = dev_get_priv(dev);
  569. BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
  570. pll_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
  571. if (!pll_clk->cgu_regs)
  572. return -EINVAL;
  573. pll_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
  574. if (!pll_clk->creg_regs)
  575. return -EINVAL;
  576. return 0;
  577. }
  578. static const struct udevice_id hsdk_cgu_clk_id[] = {
  579. { .compatible = "snps,hsdk-cgu-clock" },
  580. { }
  581. };
  582. U_BOOT_DRIVER(hsdk_cgu_clk) = {
  583. .name = "hsdk-cgu-clk",
  584. .id = UCLASS_CLK,
  585. .of_match = hsdk_cgu_clk_id,
  586. .probe = hsdk_cgu_clk_probe,
  587. .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
  588. .ops = &hsdk_cgu_ops,
  589. };