board.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/ddr.h>
  9. #include <power/pmic.h>
  10. #include <power/stpmu1.h>
  11. #ifdef CONFIG_PMIC_STPMU1
  12. int board_ddr_power_init(void)
  13. {
  14. struct udevice *dev;
  15. int ret;
  16. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  17. DM_GET_DRIVER(pmic_stpmu1), &dev);
  18. if (ret)
  19. /* No PMIC on board */
  20. return 0;
  21. /* Set LDO3 to sync mode */
  22. ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
  23. if (ret < 0)
  24. return ret;
  25. ret &= ~STPMU1_LDO3_MODE;
  26. ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
  27. ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
  28. ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
  29. ret);
  30. if (ret < 0)
  31. return ret;
  32. /* Set BUCK2 to 1.35V */
  33. ret = pmic_clrsetbits(dev,
  34. STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
  35. STPMU1_BUCK_OUTPUT_MASK,
  36. STPMU1_BUCK2_1350000V);
  37. if (ret < 0)
  38. return ret;
  39. /* Enable BUCK2 and VREF */
  40. ret = pmic_clrsetbits(dev,
  41. STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
  42. STPMU1_BUCK_EN, STPMU1_BUCK_EN);
  43. if (ret < 0)
  44. return ret;
  45. mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
  46. ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
  47. STPMU1_VREF_EN, STPMU1_VREF_EN);
  48. if (ret < 0)
  49. return ret;
  50. mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
  51. /* Enable LDO3 */
  52. ret = pmic_clrsetbits(dev,
  53. STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
  54. STPMU1_LDO_EN, STPMU1_LDO_EN);
  55. if (ret < 0)
  56. return ret;
  57. mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
  58. return 0;
  59. }
  60. #endif