ucp1020.c 8.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013-2015 Arcturus Networks, Inc.
  4. * http://www.arcturusnetworks.com/products/ucp1020/
  5. * by Oleksandr G Zhadan et al.
  6. * based on board/freescale/p1_p2_rdb_pc/spl.c
  7. * original copyright follows:
  8. * Copyright 2013 Freescale Semiconductor, Inc.
  9. */
  10. #include <common.h>
  11. #include <command.h>
  12. #include <hwconfig.h>
  13. #include <pci.h>
  14. #include <i2c.h>
  15. #include <miiphy.h>
  16. #include <linux/libfdt.h>
  17. #include <fdt_support.h>
  18. #include <fsl_mdio.h>
  19. #include <tsec.h>
  20. #include <ioports.h>
  21. #include <netdev.h>
  22. #include <micrel.h>
  23. #include <spi_flash.h>
  24. #include <mmc.h>
  25. #include <linux/ctype.h>
  26. #include <asm/fsl_serdes.h>
  27. #include <asm/gpio.h>
  28. #include <asm/processor.h>
  29. #include <asm/mmu.h>
  30. #include <asm/cache.h>
  31. #include <asm/immap_85xx.h>
  32. #include <asm/fsl_pci.h>
  33. #include <fsl_ddr_sdram.h>
  34. #include <asm/io.h>
  35. #include <asm/fsl_law.h>
  36. #include <asm/fsl_lbc.h>
  37. #include <asm/mp.h>
  38. #include "ucp1020.h"
  39. void spi_set_speed(struct spi_slave *slave, uint hz)
  40. {
  41. /* TO DO: It's actially have to be in spi/ */
  42. }
  43. /*
  44. * To be compatible with cmd_gpio
  45. */
  46. int name_to_gpio(const char *name)
  47. {
  48. int gpio = 31 - simple_strtoul(name, NULL, 10);
  49. if (gpio < 16)
  50. gpio = -1;
  51. return gpio;
  52. }
  53. void board_gpio_init(void)
  54. {
  55. int i;
  56. char envname[8], *val;
  57. for (i = 0; i < GPIO_MAX_NUM; i++) {
  58. sprintf(envname, "GPIO%d", i);
  59. val = env_get(envname);
  60. if (val) {
  61. char direction = toupper(val[0]);
  62. char level = toupper(val[1]);
  63. if (direction == 'I') {
  64. gpio_direction_input(i);
  65. } else {
  66. if (direction == 'O') {
  67. if (level == '1')
  68. gpio_direction_output(i, 1);
  69. else
  70. gpio_direction_output(i, 0);
  71. }
  72. }
  73. }
  74. }
  75. val = env_get("PCIE_OFF");
  76. if (val) {
  77. gpio_direction_input(GPIO_PCIE1_EN);
  78. gpio_direction_input(GPIO_PCIE2_EN);
  79. } else {
  80. gpio_direction_output(GPIO_PCIE1_EN, 1);
  81. gpio_direction_output(GPIO_PCIE2_EN, 1);
  82. }
  83. val = env_get("SDHC_CDWP_OFF");
  84. if (!val) {
  85. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  86. setbits_be32(&gur->pmuxcr,
  87. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  88. }
  89. }
  90. int board_early_init_f(void)
  91. {
  92. return 0; /* Just in case. Could be disable in config file */
  93. }
  94. int checkboard(void)
  95. {
  96. printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
  97. board_gpio_init();
  98. printf("SD/MMC: 4-bit Mode\n");
  99. return 0;
  100. }
  101. #ifdef CONFIG_PCI
  102. void pci_init_board(void)
  103. {
  104. fsl_pcie_init_board(0);
  105. }
  106. #endif
  107. int board_early_init_r(void)
  108. {
  109. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  110. const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  111. /*
  112. * Remap Boot flash region to caching-inhibited
  113. * so that flash can be erased properly.
  114. */
  115. /* Flush d-cache and invalidate i-cache of any FLASH data */
  116. flush_dcache();
  117. invalidate_icache();
  118. /* invalidate existing TLB entry for flash */
  119. disable_tlb(flash_esel);
  120. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  121. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
  122. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  123. return 0;
  124. }
  125. int board_phy_config(struct phy_device *phydev)
  126. {
  127. #if defined(CONFIG_PHY_MICREL_KSZ9021)
  128. int regval;
  129. static int cnt;
  130. if (cnt++ == 0)
  131. printf("PHYs address [");
  132. if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
  133. regval =
  134. ksz9021_phy_extended_read(phydev,
  135. MII_KSZ9021_EXT_STRAP_STATUS);
  136. /*
  137. * min rx data delay
  138. */
  139. ksz9021_phy_extended_write(phydev,
  140. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  141. 0x6666);
  142. /*
  143. * max rx/tx clock delay, min rx/tx control
  144. */
  145. ksz9021_phy_extended_write(phydev,
  146. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  147. 0xf6f6);
  148. printf("0x%x", (regval & 0x1f));
  149. } else {
  150. printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
  151. }
  152. if (cnt == 3)
  153. printf("] ");
  154. else
  155. printf(",");
  156. #endif
  157. #if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
  158. regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
  159. if (regval >= 0)
  160. printf(" (ADDR 0x%x) ", regval & 0x1f);
  161. #endif
  162. return 0;
  163. }
  164. int last_stage_init(void)
  165. {
  166. static char newkernelargs[256];
  167. static u8 id1[16];
  168. static u8 id2;
  169. struct mmc *mmc;
  170. char *sval, *kval;
  171. if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
  172. printf("Error reading i2c IDT6V49205B information!\n");
  173. } else {
  174. printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
  175. i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  176. if (!(id1[1] & 0x02)) {
  177. id1[1] |= 0x02;
  178. i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  179. asm("nop; nop");
  180. }
  181. }
  182. if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
  183. printf("Error reading i2c NCT72 information!\n");
  184. else
  185. printf("NCT72(0x%x): ready\n", id2);
  186. kval = env_get("kernelargs");
  187. mmc = find_mmc_device(0);
  188. if (mmc)
  189. if (!mmc_init(mmc)) {
  190. printf("MMC/SD card detected\n");
  191. if (kval) {
  192. int n = strlen(defkargs);
  193. char *tmp = strstr(kval, defkargs);
  194. *tmp = 0;
  195. strcpy(newkernelargs, kval);
  196. strcat(newkernelargs, " ");
  197. strcat(newkernelargs, mmckargs);
  198. strcat(newkernelargs, " ");
  199. strcat(newkernelargs, &tmp[n]);
  200. env_set("kernelargs", newkernelargs);
  201. } else {
  202. env_set("kernelargs", mmckargs);
  203. }
  204. }
  205. get_arc_info();
  206. if (kval) {
  207. sval = env_get("SERIAL");
  208. if (sval) {
  209. strcpy(newkernelargs, "SN=");
  210. strcat(newkernelargs, sval);
  211. strcat(newkernelargs, " ");
  212. strcat(newkernelargs, kval);
  213. env_set("kernelargs", newkernelargs);
  214. }
  215. } else {
  216. printf("Error reading kernelargs env variable!\n");
  217. }
  218. return 0;
  219. }
  220. int board_eth_init(bd_t *bis)
  221. {
  222. struct fsl_pq_mdio_info mdio_info;
  223. struct tsec_info_struct tsec_info[4];
  224. #ifdef CONFIG_TSEC2
  225. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  226. #endif
  227. int num = 0;
  228. #ifdef CONFIG_TSEC1
  229. SET_STD_TSEC_INFO(tsec_info[num], 1);
  230. num++;
  231. #endif
  232. #ifdef CONFIG_TSEC2
  233. SET_STD_TSEC_INFO(tsec_info[num], 2);
  234. if (is_serdes_configured(SGMII_TSEC2)) {
  235. if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
  236. puts("eTSEC2 is in sgmii mode.\n");
  237. tsec_info[num].flags |= TSEC_SGMII;
  238. tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
  239. }
  240. }
  241. num++;
  242. #endif
  243. #ifdef CONFIG_TSEC3
  244. SET_STD_TSEC_INFO(tsec_info[num], 3);
  245. num++;
  246. #endif
  247. if (!num) {
  248. printf("No TSECs initialized\n");
  249. return 0;
  250. }
  251. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  252. mdio_info.name = DEFAULT_MII_NAME;
  253. fsl_pq_mdio_init(bis, &mdio_info);
  254. tsec_eth_init(bis, tsec_info, num);
  255. return pci_eth_init(bis);
  256. }
  257. #ifdef CONFIG_OF_BOARD_SETUP
  258. int ft_board_setup(void *blob, bd_t *bd)
  259. {
  260. phys_addr_t base;
  261. phys_size_t size;
  262. const char *soc_usb_compat = "fsl-usb2-dr";
  263. int err, usb1_off, usb2_off;
  264. ft_cpu_setup(blob, bd);
  265. base = env_get_bootm_low();
  266. size = env_get_bootm_size();
  267. fdt_fixup_memory(blob, (u64)base, (u64)size);
  268. FT_FSL_PCI_SETUP;
  269. #if defined(CONFIG_HAS_FSL_DR_USB)
  270. fsl_fdt_fixup_dr_usb(blob, bd);
  271. #endif
  272. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  273. /* Delete eLBC node as it is muxed with USB2 controller */
  274. if (hwconfig("usb2")) {
  275. const char *soc_elbc_compat = "fsl,p1020-elbc";
  276. int off = fdt_node_offset_by_compatible(blob, -1,
  277. soc_elbc_compat);
  278. if (off < 0) {
  279. printf
  280. ("WARNING: could not find compatible node %s: %s\n",
  281. soc_elbc_compat, fdt_strerror(off));
  282. return off;
  283. }
  284. err = fdt_del_node(blob, off);
  285. if (err < 0) {
  286. printf("WARNING: could not remove %s: %s\n",
  287. soc_elbc_compat, fdt_strerror(err));
  288. }
  289. return err;
  290. }
  291. #endif
  292. /* Delete USB2 node as it is muxed with eLBC */
  293. usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
  294. if (usb1_off < 0) {
  295. printf("WARNING: could not find compatible node %s: %s.\n",
  296. soc_usb_compat, fdt_strerror(usb1_off));
  297. return usb1_off;
  298. }
  299. usb2_off =
  300. fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
  301. if (usb2_off < 0) {
  302. printf("WARNING: could not find compatible node %s: %s.\n",
  303. soc_usb_compat, fdt_strerror(usb2_off));
  304. return usb2_off;
  305. }
  306. err = fdt_del_node(blob, usb2_off);
  307. if (err < 0) {
  308. printf("WARNING: could not remove %s: %s.\n",
  309. soc_usb_compat, fdt_strerror(err));
  310. }
  311. return 0;
  312. }
  313. #endif