cpu.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/stm32.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <dm/uclass.h>
  11. /* RCC register */
  12. #define RCC_TZCR (STM32_RCC_BASE + 0x00)
  13. #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
  14. #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
  15. #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
  16. #define RCC_BDCR_VSWRST BIT(31)
  17. #define RCC_BDCR_RTCSRC GENMASK(17, 16)
  18. #define RCC_DBGCFGR_DBGCKEN BIT(8)
  19. /* Security register */
  20. #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
  21. #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
  22. #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
  23. #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
  24. #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
  25. #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
  26. #define PWR_CR1 (STM32_PWR_BASE + 0x00)
  27. #define PWR_CR1_DBP BIT(8)
  28. /* DBGMCU register */
  29. #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
  30. #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
  31. #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
  32. #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
  33. #define DBGMCU_IDC_DEV_ID_SHIFT 0
  34. #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
  35. #define DBGMCU_IDC_REV_ID_SHIFT 16
  36. /* boot interface from Bootrom
  37. * - boot instance = bit 31:16
  38. * - boot device = bit 15:0
  39. */
  40. #define BOOTROM_PARAM_ADDR 0x2FFC0078
  41. #define BOOTROM_MODE_MASK GENMASK(15, 0)
  42. #define BOOTROM_MODE_SHIFT 0
  43. #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
  44. #define BOOTROM_INSTANCE_SHIFT 16
  45. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  46. static void security_init(void)
  47. {
  48. /* Disable the backup domain write protection */
  49. /* the protection is enable at each reset by hardware */
  50. /* And must be disable by software */
  51. setbits_le32(PWR_CR1, PWR_CR1_DBP);
  52. while (!(readl(PWR_CR1) & PWR_CR1_DBP))
  53. ;
  54. /* If RTC clock isn't enable so this is a cold boot then we need
  55. * to reset the backup domain
  56. */
  57. if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
  58. setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  59. while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
  60. ;
  61. clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  62. }
  63. /* allow non secure access in Write/Read for all peripheral */
  64. writel(GENMASK(25, 0), ETZPC_DECPROT0);
  65. /* Open SYSRAM for no secure access */
  66. writel(0x0, ETZPC_TZMA1_SIZE);
  67. /* enable TZC1 TZC2 clock */
  68. writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
  69. /* Region 0 set to no access by default */
  70. /* bit 0 / 16 => nsaid0 read/write Enable
  71. * bit 1 / 17 => nsaid1 read/write Enable
  72. * ...
  73. * bit 15 / 31 => nsaid15 read/write Enable
  74. */
  75. writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
  76. /* bit 30 / 31 => Secure Global Enable : write/read */
  77. /* bit 0 / 1 => Region Enable for filter 0/1 */
  78. writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
  79. /* Enable Filter 0 and 1 */
  80. setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
  81. /* RCC trust zone deactivated */
  82. writel(0x0, RCC_TZCR);
  83. /* TAMP: deactivate the internal tamper
  84. * Bit 23 ITAMP8E: monotonic counter overflow
  85. * Bit 20 ITAMP5E: RTC calendar overflow
  86. * Bit 19 ITAMP4E: HSE monitoring
  87. * Bit 18 ITAMP3E: LSE monitoring
  88. * Bit 16 ITAMP1E: RTC power domain supply monitoring
  89. */
  90. writel(0x0, TAMP_CR1);
  91. }
  92. /*
  93. * Debug init
  94. */
  95. static void dbgmcu_init(void)
  96. {
  97. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  98. /* Freeze IWDG2 if Cortex-A7 is in debug mode */
  99. setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
  100. }
  101. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  102. static u32 get_bootmode(void)
  103. {
  104. u32 boot_mode;
  105. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  106. u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
  107. u32 bootrom_device, bootrom_instance;
  108. bootrom_device =
  109. (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
  110. bootrom_instance =
  111. (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
  112. boot_mode =
  113. ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
  114. ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
  115. BOOT_INSTANCE_MASK);
  116. /* save the boot mode in TAMP backup register */
  117. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  118. TAMP_BOOT_MODE_MASK,
  119. boot_mode << TAMP_BOOT_MODE_SHIFT);
  120. #else
  121. /* read TAMP backup register */
  122. boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
  123. TAMP_BOOT_MODE_SHIFT;
  124. #endif
  125. return boot_mode;
  126. }
  127. /*
  128. * Early system init
  129. */
  130. int arch_cpu_init(void)
  131. {
  132. /* early armv7 timer init: needed for polling */
  133. timer_init();
  134. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  135. dbgmcu_init();
  136. security_init();
  137. #endif
  138. /* get bootmode from BootRom context: saved in TAMP register */
  139. get_bootmode();
  140. return 0;
  141. }
  142. void enable_caches(void)
  143. {
  144. /* Enable D-cache. I-cache is already enabled in start.S */
  145. dcache_enable();
  146. }
  147. static u32 read_idc(void)
  148. {
  149. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  150. return readl(DBGMCU_IDC);
  151. }
  152. u32 get_cpu_rev(void)
  153. {
  154. return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
  155. }
  156. u32 get_cpu_type(void)
  157. {
  158. return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
  159. }
  160. #if defined(CONFIG_DISPLAY_CPUINFO)
  161. int print_cpuinfo(void)
  162. {
  163. char *cpu_s, *cpu_r;
  164. switch (get_cpu_type()) {
  165. case CPU_STMP32MP15x:
  166. cpu_s = "15x";
  167. break;
  168. default:
  169. cpu_s = "?";
  170. break;
  171. }
  172. switch (get_cpu_rev()) {
  173. case CPU_REVA:
  174. cpu_r = "A";
  175. break;
  176. case CPU_REVB:
  177. cpu_r = "B";
  178. break;
  179. default:
  180. cpu_r = "?";
  181. break;
  182. }
  183. printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r);
  184. return 0;
  185. }
  186. #endif /* CONFIG_DISPLAY_CPUINFO */
  187. static void setup_boot_mode(void)
  188. {
  189. char cmd[60];
  190. u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
  191. u32 boot_mode =
  192. (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
  193. int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
  194. pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n",
  195. __func__, boot_ctx, boot_mode, instance);
  196. switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
  197. case BOOT_SERIAL_UART:
  198. sprintf(cmd, "%d", instance);
  199. env_set("boot_device", "uart");
  200. env_set("boot_instance", cmd);
  201. break;
  202. case BOOT_SERIAL_USB:
  203. env_set("boot_device", "usb");
  204. env_set("boot_instance", "0");
  205. break;
  206. case BOOT_FLASH_SD:
  207. case BOOT_FLASH_EMMC:
  208. sprintf(cmd, "%d", instance);
  209. env_set("boot_device", "mmc");
  210. env_set("boot_instance", cmd);
  211. break;
  212. case BOOT_FLASH_NAND:
  213. env_set("boot_device", "nand");
  214. env_set("boot_instance", "0");
  215. break;
  216. case BOOT_FLASH_NOR:
  217. env_set("boot_device", "nor");
  218. env_set("boot_instance", "0");
  219. break;
  220. default:
  221. pr_debug("unexpected boot mode = %x\n", boot_mode);
  222. break;
  223. }
  224. }
  225. int arch_misc_init(void)
  226. {
  227. setup_boot_mode();
  228. return 0;
  229. }