vf.dtsi 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. /include/ "skeleton.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. / {
  8. aliases {
  9. gpio0 = &gpio0;
  10. gpio1 = &gpio1;
  11. gpio2 = &gpio2;
  12. gpio3 = &gpio3;
  13. gpio4 = &gpio4;
  14. serial0 = &uart0;
  15. serial1 = &uart1;
  16. serial2 = &uart2;
  17. serial3 = &uart3;
  18. serial4 = &uart4;
  19. serial5 = &uart5;
  20. spi0 = &dspi0;
  21. spi1 = &dspi1;
  22. ehci0 = &ehci0;
  23. ehci1 = &ehci1;
  24. };
  25. soc {
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. compatible = "simple-bus";
  29. ranges;
  30. aips0: aips-bus@40000000 {
  31. compatible = "fsl,aips-bus", "simple-bus";
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. reg = <0x40000000 0x00070000>;
  35. ranges;
  36. uart0: serial@40027000 {
  37. compatible = "fsl,vf610-lpuart";
  38. reg = <0x40027000 0x1000>;
  39. status = "disabled";
  40. };
  41. uart1: serial@40028000 {
  42. compatible = "fsl,vf610-lpuart";
  43. reg = <0x40028000 0x1000>;
  44. status = "disabled";
  45. };
  46. uart2: serial@40029000 {
  47. compatible = "fsl,vf610-lpuart";
  48. reg = <0x40029000 0x1000>;
  49. status = "disabled";
  50. };
  51. uart3: serial@4002a000 {
  52. compatible = "fsl,vf610-lpuart";
  53. reg = <0x4002a000 0x1000>;
  54. status = "disabled";
  55. };
  56. dspi0: dspi0@4002c000 {
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. compatible = "fsl,vf610-dspi";
  60. reg = <0x4002c000 0x1000>;
  61. num-cs = <5>;
  62. status = "disabled";
  63. };
  64. dspi1: dspi1@4002d000 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. compatible = "fsl,vf610-dspi";
  68. reg = <0x4002d000 0x1000>;
  69. num-cs = <5>;
  70. status = "disabled";
  71. };
  72. qspi0: quadspi@40044000 {
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. compatible = "fsl,vf610-qspi";
  76. reg = <0x40044000 0x1000>,
  77. <0x20000000 0x10000000>;
  78. reg-names = "QuadSPI", "QuadSPI-memory";
  79. status = "disabled";
  80. };
  81. gpio0: gpio@40049000 {
  82. compatible = "fsl,vf610-gpio";
  83. reg = <0x400ff000 0x40>;
  84. #gpio-cells = <2>;
  85. };
  86. gpio1: gpio@4004a000 {
  87. compatible = "fsl,vf610-gpio";
  88. reg = <0x400ff040 0x40>;
  89. #gpio-cells = <2>;
  90. };
  91. gpio2: gpio@4004b000 {
  92. compatible = "fsl,vf610-gpio";
  93. reg = <0x400ff080 0x40>;
  94. #gpio-cells = <2>;
  95. };
  96. gpio3: gpio@4004c000 {
  97. compatible = "fsl,vf610-gpio";
  98. reg = <0x400ff0c0 0x40>;
  99. #gpio-cells = <2>;
  100. };
  101. gpio4: gpio@4004d000 {
  102. compatible = "fsl,vf610-gpio";
  103. reg = <0x400ff100 0x40>;
  104. #gpio-cells = <2>;
  105. };
  106. ehci0: ehci@40034000 {
  107. compatible = "fsl,vf610-usb";
  108. reg = <0x40034000 0x800>;
  109. status = "disabled";
  110. };
  111. };
  112. aips1: aips-bus@40080000 {
  113. compatible = "fsl,aips-bus", "simple-bus";
  114. #address-cells = <1>;
  115. #size-cells = <1>;
  116. reg = <0x40080000 0x0007f000>;
  117. ranges;
  118. uart4: serial@400a9000 {
  119. compatible = "fsl,vf610-lpuart";
  120. reg = <0x400a9000 0x1000>;
  121. status = "disabled";
  122. };
  123. uart5: serial@400aa000 {
  124. compatible = "fsl,vf610-lpuart";
  125. reg = <0x400aa000 0x1000>;
  126. status = "disabled";
  127. };
  128. ehci1: ehci@400b4000 {
  129. compatible = "fsl,vf610-usb";
  130. reg = <0x400b4000 0x800>;
  131. status = "disabled";
  132. };
  133. };
  134. };
  135. };