stm32mp157c-ed1-u-boot.dtsi 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp157-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  8. / {
  9. aliases {
  10. mmc0 = &sdmmc1;
  11. mmc1 = &sdmmc2;
  12. i2c3 = &i2c4;
  13. };
  14. };
  15. &uart4_pins_a {
  16. u-boot,dm-pre-reloc;
  17. pins1 {
  18. u-boot,dm-pre-reloc;
  19. };
  20. pins2 {
  21. u-boot,dm-pre-reloc;
  22. };
  23. };
  24. &i2c4_pins_a {
  25. u-boot,dm-pre-reloc;
  26. pins {
  27. u-boot,dm-pre-reloc;
  28. };
  29. };
  30. &uart4 {
  31. u-boot,dm-pre-reloc;
  32. };
  33. &i2c4 {
  34. u-boot,dm-pre-reloc;
  35. };
  36. &pmic {
  37. u-boot,dm-pre-reloc;
  38. };
  39. /* CLOCK init */
  40. &rcc_clk {
  41. st,clksrc = <
  42. CLK_MPU_PLL1P
  43. CLK_AXI_PLL2P
  44. CLK_MCU_PLL3P
  45. CLK_PLL12_HSE
  46. CLK_PLL3_HSE
  47. CLK_PLL4_HSE
  48. CLK_RTC_LSE
  49. CLK_MCO1_DISABLED
  50. CLK_MCO2_DISABLED
  51. >;
  52. st,clkdiv = <
  53. 1 /*MPU*/
  54. 0 /*AXI*/
  55. 0 /*MCU*/
  56. 1 /*APB1*/
  57. 1 /*APB2*/
  58. 1 /*APB3*/
  59. 1 /*APB4*/
  60. 2 /*APB5*/
  61. 23 /*RTC*/
  62. 0 /*MCO1*/
  63. 0 /*MCO2*/
  64. >;
  65. st,pkcs = <
  66. CLK_CKPER_DISABLED
  67. CLK_SDMMC12_PLL3R
  68. CLK_STGEN_HSE
  69. CLK_I2C46_PCLK5
  70. CLK_I2C12_PCLK1
  71. CLK_SDMMC3_PLL3R
  72. CLK_I2C35_PCLK1
  73. CLK_UART1_PCLK5
  74. CLK_UART24_PCLK1
  75. CLK_UART35_PCLK1
  76. CLK_UART6_PCLK2
  77. CLK_UART78_PCLK1
  78. >;
  79. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  80. pll1: st,pll@0 {
  81. cfg = < 2 80 0 0 0 PQR(1,0,0) >;
  82. frac = < 0x800 >;
  83. u-boot,dm-pre-reloc;
  84. };
  85. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  86. pll2: st,pll@1 {
  87. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  88. frac = < 0x1400 >;
  89. u-boot,dm-pre-reloc;
  90. };
  91. /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
  92. pll3: st,pll@2 {
  93. cfg = < 3 128 3 20 7 PQR(1,1,1) >;
  94. u-boot,dm-pre-reloc;
  95. };
  96. /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
  97. pll4: st,pll@3 {
  98. cfg = < 5 126 8 8 8 PQR(1,1,1) >;
  99. u-boot,dm-pre-reloc;
  100. };
  101. };
  102. /* SPL part **************************************/
  103. /* MMC1 boot */
  104. &sdmmc1_b4_pins_a {
  105. u-boot,dm-spl;
  106. pins {
  107. u-boot,dm-spl;
  108. };
  109. };
  110. &sdmmc1_dir_pins_a {
  111. u-boot,dm-spl;
  112. pins {
  113. u-boot,dm-spl;
  114. };
  115. };
  116. &sdmmc1 {
  117. u-boot,dm-spl;
  118. };
  119. /* MMC2 boot */
  120. &sdmmc2_b4_pins_a {
  121. u-boot,dm-spl;
  122. pins {
  123. u-boot,dm-spl;
  124. };
  125. };
  126. &sdmmc2_d47_pins_a {
  127. u-boot,dm-spl;
  128. pins {
  129. u-boot,dm-spl;
  130. };
  131. };
  132. &sdmmc2 {
  133. u-boot,dm-spl;
  134. };