stm32mp15-ddr.dtsi 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. / {
  6. soc {
  7. ddr: ddr@0x5A003000{
  8. u-boot,dm-pre-reloc;
  9. compatible = "st,stm32mp1-ddr";
  10. reg = <0x5A003000 0x550
  11. 0x5A004000 0x234>;
  12. clocks = <&rcc_clk AXIDCG>,
  13. <&rcc_clk DDRC1>,
  14. <&rcc_clk DDRC2>,
  15. <&rcc_clk DDRPHYC>,
  16. <&rcc_clk DDRCAPB>,
  17. <&rcc_clk DDRPHYCAPB>;
  18. clock-names = "axidcg",
  19. "ddrc1",
  20. "ddrc2",
  21. "ddrphyc",
  22. "ddrcapb",
  23. "ddrphycapb";
  24. st,mem-name = DDR_MEM_NAME;
  25. st,mem-speed = <DDR_MEM_SPEED>;
  26. st,mem-size = <DDR_MEM_SIZE>;
  27. st,ctl-reg = <
  28. DDR_MSTR
  29. DDR_MRCTRL0
  30. DDR_MRCTRL1
  31. DDR_DERATEEN
  32. DDR_DERATEINT
  33. DDR_PWRCTL
  34. DDR_PWRTMG
  35. DDR_HWLPCTL
  36. DDR_RFSHCTL0
  37. DDR_RFSHCTL3
  38. DDR_CRCPARCTL0
  39. DDR_ZQCTL0
  40. DDR_DFITMG0
  41. DDR_DFITMG1
  42. DDR_DFILPCFG0
  43. DDR_DFIUPD0
  44. DDR_DFIUPD1
  45. DDR_DFIUPD2
  46. DDR_DFIPHYMSTR
  47. DDR_ODTMAP
  48. DDR_DBG0
  49. DDR_DBG1
  50. DDR_DBGCMD
  51. DDR_POISONCFG
  52. DDR_PCCFG
  53. >;
  54. st,ctl-timing = <
  55. DDR_RFSHTMG
  56. DDR_DRAMTMG0
  57. DDR_DRAMTMG1
  58. DDR_DRAMTMG2
  59. DDR_DRAMTMG3
  60. DDR_DRAMTMG4
  61. DDR_DRAMTMG5
  62. DDR_DRAMTMG6
  63. DDR_DRAMTMG7
  64. DDR_DRAMTMG8
  65. DDR_DRAMTMG14
  66. DDR_ODTCFG
  67. >;
  68. st,ctl-map = <
  69. DDR_ADDRMAP1
  70. DDR_ADDRMAP2
  71. DDR_ADDRMAP3
  72. DDR_ADDRMAP4
  73. DDR_ADDRMAP5
  74. DDR_ADDRMAP6
  75. DDR_ADDRMAP9
  76. DDR_ADDRMAP10
  77. DDR_ADDRMAP11
  78. >;
  79. st,ctl-perf = <
  80. DDR_SCHED
  81. DDR_SCHED1
  82. DDR_PERFHPR1
  83. DDR_PERFLPR1
  84. DDR_PERFWR1
  85. DDR_PCFGR_0
  86. DDR_PCFGW_0
  87. DDR_PCFGQOS0_0
  88. DDR_PCFGQOS1_0
  89. DDR_PCFGWQOS0_0
  90. DDR_PCFGWQOS1_0
  91. DDR_PCFGR_1
  92. DDR_PCFGW_1
  93. DDR_PCFGQOS0_1
  94. DDR_PCFGQOS1_1
  95. DDR_PCFGWQOS0_1
  96. DDR_PCFGWQOS1_1
  97. >;
  98. st,phy-reg = <
  99. DDR_PGCR
  100. DDR_ACIOCR
  101. DDR_DXCCR
  102. DDR_DSGCR
  103. DDR_DCR
  104. DDR_ODTCR
  105. DDR_ZQ0CR1
  106. DDR_DX0GCR
  107. DDR_DX1GCR
  108. DDR_DX2GCR
  109. DDR_DX3GCR
  110. >;
  111. st,phy-timing = <
  112. DDR_PTR0
  113. DDR_PTR1
  114. DDR_PTR2
  115. DDR_DTPR0
  116. DDR_DTPR1
  117. DDR_DTPR2
  118. DDR_MR0
  119. DDR_MR1
  120. DDR_MR2
  121. DDR_MR3
  122. >;
  123. st,phy-cal = <
  124. DDR_DX0DLLCR
  125. DDR_DX0DQTR
  126. DDR_DX0DQSTR
  127. DDR_DX1DLLCR
  128. DDR_DX1DQTR
  129. DDR_DX1DQSTR
  130. DDR_DX2DLLCR
  131. DDR_DX2DQTR
  132. DDR_DX2DQSTR
  133. DDR_DX3DLLCR
  134. DDR_DX3DQTR
  135. DDR_DX3DQSTR
  136. >;
  137. status = "okay";
  138. };
  139. };
  140. };